Patent Application
20180358321
The present invention relates generally to the field of semiconductor device fabrication, and more particularly to a pressing structure and method for enhancing probe array contact during wafer level testing.
During semiconductor device fabrication, wafer level testing is performed to determine the functionality of individual, partially fabricated integrated circuits (IC(s)), semiconductor devices, or semiconductor chips (“chip(s)”), of wafers or devices under test.
A method of pressing a plurality of solder bumps using a pressing apparatus prior to testing a wafer. The method includes loading the wafer into the pressing apparatus, where the wafer includes a number of chips, and the wafer is aligned with respect to a test head of the pressing apparatus. The test head includes a substrate which has pressing structures arranged across a surface of the substrate facing the wafer. The pressing structures are caused to contact a plurality of solder bumps disposed across a surface of the wafer, where the solder bumps include a first surface topology and the pressing structures comprise a pressing surface topology prior to the contact. The caused contact includes altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps include a second surface topology subsequent to the caused contact, and the second surface topology of the solder bumps substantially matches the pressing surface topology subsequent to the caused contact.
A method of testing a wafer using a pressing apparatus and a testing apparatus including loading the wafer into the pressing apparatus, the wafer including a plurality of chips, and aligning the wafer with respect to a test head of the pressing apparatus, the test head including a substrate having pressing structures disposed across a surface of the substrate facing the wafer, and causing the pressing structures to contact a plurality of solder bumps disposed across a surface of the wafer, the plurality of solder bumps comprise a first surface topology and the pressing structures comprise a pressing surface topology prior to contact, causing the contact comprises altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps comprise a second surface topology subsequent to the caused contact, such that the second surface topology of the plurality of solder bumps substantially matches the pressing surface topology subsequent to the caused contact, and testing the wafer subsequent to the caused contact by causing a plurality of probes to contact the plurality of solder bumps, wherein the plurality of probes comprise a probe surface topology substantially matching the second surface topology during testing of the wafer.
A pressing apparatus including a first chuck including a flat mounting surface, a bottom surface of a wafer is removably mounted flush to the mounting surface of the first chuck, and the wafer includes solder bumps disposed across a top surface of the wafer, and a first test head includes first testing circuitry and a first plurality of pogo pins connected to the first testing circuitry, where the first plurality of pogo pins extending perpendicularly from a bottom surface of the first test head, a pressing card removably connected to the first test head by the first plurality of pogo pins, the pressing card including a first substrate disposed on a bottom surface of the pressing card, the pressing card includes a pressing structure for each of the plurality of solder bumps, the pressing structures extend perpendicularly from a bottom surface of the first substrate, the bottom surface of the first substrate is parallel to the top surface of the wafer, the pressing card and the wafer are moveable relative to each other in a first linear direction perpendicular to the top surface of the wafer. Movement of the wafer towards the pressing card in the first linear direction causes the pressing structures to contact the plurality of solder bumps, such that the contact results in a surface topology of the plurality of solder bumps that substantially matches the pressing surface topology.
The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings.
The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.
Detailed embodiments of the present invention are disclosed herein for purposes of describing and illustrating claimed structures and methods that may be embodied in various forms, and are not intended to be exhaustive in any way, or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein was chosen to best explain the principles of the one or more embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. As described, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the embodiments of the present invention.
References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, or the like, indicate that the embodiment described may include one or more particular features, structures, or characteristics, but it shall be understood that such particular features, structures, or characteristics may or may not be common to each and every disclosed embodiment of the present invention herein. Moreover, such phrases do not necessarily refer to any one particular embodiment per se. As such, when one or more particular features, structures, or characteristics is described in connection with an embodiment, it is submitted that it is within the knowledge of those skilled in the art to affect such one or more features, structures, or characteristics in connection with other embodiments, where applicable, whether or not explicitly described.
For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, “perpendicular”, “parallel”, and the like, and any derivatives thereof, shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating, or semiconductor layers at the interface of the two elements.
In the interest of not obscuring disclosure of embodiments of the present invention, the following detailed description may contain certain processing steps or operations that are known in the art which may have been combined for purposes of clear description and illustration. In some instances certain processing steps or operations that are known in the art may not be described in detail, and/or may not be described at all. It shall be understood that the following disclosure of embodiments of the present invention is relatively focused on distinctive elements, features, structures, or characteristics thereof.
Some types of wafer level testing require forming electrical connections between interconnects of a device under test and conductors of automated test equipment. The interconnects of the device under test may implement flip chip or controlled collapse chip connections (“C4(s)”), which use solder bumps formed on top of contact pads. During testing, such solder bumps may alternatively be referred to as test bumps. The conductors of the automated test equipment often include specialized testing structures, such as probes, which are used to form the requisite electrical connections with the solder bumps during testing. In such cases, the probes may be aligned, moved, or positioned, to achieve contact or engagement with the solder bumps in order to form the electrical connections.
The automated test equipment may then apply and subsequently receive test signals, input and output with respect to each of the chips of the wafer under test. Levels of functionality of each of the chips may be determined by comparison of received output test signals and expected output test signals characteristic of properly functioning chips, to distinguish between functional and dysfunctional chips.
Generally, such wafer level testing may be performed on each chip of a wafer under test simultaneously, in one “step,” or may be performed on one or more of the chips, in sequence, in a series of “steps,” until all of the chips have been tested. These types of tests may be referred to as full cluster probe testing, and step and repeat cluster testing, respectively.
The present invention relates generally to the field of semiconductor device fabrication, and more particularly, to a pressing method and structure for enhancing probe array contact during wafer testing. An array of pressing structures arranged to form a surface topology matching that formed by an array of probes used during testing. Doing so will ensure a surface topology of the array of solder bumps matches that of the array of probes during testing, thereby improving probe array contact during wafer testing. For purposes of the present description, pressing may otherwise include coining, minting, stamping, striking, molding, or otherwise forging.
Advantageously, the enhanced probe array contact according to the present disclosure can be readily implemented in current wafer level testing process flows. To that end, embodiments of the present invention allow for effective pressing operations to occur prior to testing, thereby increasing levels of accuracy and reducing the number of wafers discarded based on erroneous or inconclusive test results.
Ideally, uniform contact and low electrical resistance, also referred to in the art as contact resistance, formed between and across an array of probe contacts and an array of solder bumps residing atop chips of a wafer under test is preferable during wafer level testing. One way to achieve uniform contact and low electrical resistance includes pressing the array of solder bumps prior to testing. An embodiment by which to press the array of solder bumps is described in detail below with reference to the accompanying figures. In embodiments of the present invention, the array of solder bumps may be pressed prior to testing by using a pressing apparatus with an array of a pressing structures, to produce a surface topology of the solder bumps that matches a surface topology of the probes used during testing.
The first test apparatus 100 represents automated test equipment, such as a wafer prober, which may perform functionality testing on a wafer under test 108 (hereinafter “wafer”). The first test apparatus 100 may include hardware and software components including instrumentation and control systems, to spatially align and position, either individually or in combination, each of the chuck 106 and the test head 102, in order to perform wafer level testing of the wafer 108. The test head 102 may be physically and electrically connected, in a removable manner, to the card apparatus 104 by pogo pins 110. The chuck 106 may removably mount, grasp, grip, or otherwise manipulate the wafer 108 prior to, during, and after testing.
In an embodiment of the present invention, the test head 102 may include wafer testing circuitry including components such as a multilayered printed circuit board (“PCB”) or a load board PCB, configured to connect to corresponding wafer testing circuitry of the card apparatus 104. The connection may be formed by, for example, a spring pin tower including the pogo pins 110.
In an embodiment of the present invention, the card apparatus 104 represents test equipment such as a probe card, which may be used in conjunction with automated test equipment. The card apparatus 104 may include a substrate 112, to which a plurality of discrete testing structures, such as probes 114, may be connected or attached. The probes 114 may be used to form electrical connections between the test head 102 and the wafer 108 during testing.
The chuck 106 may include a stage or surface configured to mount and maintain a substantially planar configuration of the wafer 108 during testing. The chuck 106 may be, for example, vacuum-actuated or electromechanically actuated.
Spatial alignment and positioning may occur along or about each of the X-axis, the Y-axis, and the Z-axis, as previously described. The wafer 108 and the card apparatus 104 may be aligned and positioned relative to each other such that mutually-facing surfaces of each are parallel and spaced apart from one another. Known probe alignment and positioning systems, for example, which use optical and electromechanical systems and techniques, may be used to position the wafer 108 with respect to the probes 114, or vice versa. As may be appreciated by those of skill in the art, any other known method of alignment and/or positioning may otherwise be used.
In an embodiment of the present invention, the card apparatus 104 may include wafer testing circuitry configured to connect to the wafer testing circuitry of the test head 102. The card apparatus 104 may include components such as a PCB, an interposer, and a substrate 112, which may include the probes 114. The PCB may be electrically connected by the interposer to the substrate 112 by, for example, interposer probes attached at one end to electrical contacts of the PCB, and at the other end to electrical contacts formed on a surface of the substrate 112. The electrical contacts formed on the surface of the substrate 112 may be electrically connected to corresponding electrical contacts, such as the probes 114, formed on an opposing surface of the substrate 112. The electrical contacts formed on opposite surfaces of the substrate 112 may be electrically connected through a thickness of the substrate 112, by way of, for example, vias, traces, or the like. The probes 114 formed on the opposing surface of the substrate 112 may generally be arranged about its center, and may be configured to form the electrical connections with the wafer 108. The substrate 112 is generally supported around its perimeter, while its center is occupied by various electrical connections and/or circuitry.
With reference to
Prior to testing, a reflow process may be performed with respect to the solder bumps 202. An overall volume of each of the solder bumps 202, both prior to and following the reflow process, may remain substantially the same; however, each of the solder bumps 202 may vary in height after the reflow process has been completed. That is, each of the solder bumps 202A-E may include relative variations in height or vertical profile with respect to each other during testing, which may have been produced as a byproduct of the reflow process. For illustrative purposes only, each of the solder bumps 202A-E are shown with exaggerated variations in height, relative to a reference line 204. Generally, each of the solder bumps 202 may have a diameter of approximately 100 micrometers, and may vary in height from approximately 5 micrometers to approximately 15 micrometers, and more particularly, from approximately 8 to 10 micrometers. For purposes of the present disclosure, the variations in height of the solder bumps 202A-E is referred to as forming or including a first topology or a first surface topology. The first topology collectively describes the variations in height, or height variation, across all of the solder bumps 202A-E.
In embodiments of the present invention, variations in height or length of the probe tips caused by manufacturing form a topology, as will be described in further detail below. Such variation may be caused, for example, by milling or forming processes used in the fabrication of the probes 114. For illustrative purposes only, each of the probes 114, and more specifically, each of the probe tips, are shown with exaggerated variations in height or length, relative to a reference line 206. Generally, each of the probe tips may vary in height from approximately 1 micrometers to approximately 10 micrometers, and more particularly, from approximately 3 to 5 micrometers. For purposes of the present disclosure, the variations in height of the probes 114 is referred to as forming or including a second topology or a second surface topology. The second topology collectively describes the variations in height, or height variation, across all of the probes 114.
With continued reference to
With reference to
Most notably, the above techniques often produce undesirable testing results. Specifically, the first topology of the probes 114 with respect to the second topology of the solder bumps 202 may inhibit consistent or reliable contact between the probes 114 and the solder bumps 202. Stated differently, the variations in height of the probes 114, combined with the variations in height of the solder bumps 202, may result in varying or non-uniform contact across the probes 114 and the solder bumps 202 during testing, as well as variable electrical resistance across the established interface during testing. The substrate 112 or the card apparatus 104, either individually or in combination, may experience undesirable deflection in the form of flexing, warping, or bowing, caused by contact between the probes 114 and the solder bumps 202. The most notable variations in contact and electrical resistance across the established interface due to flexing may manifest, for example, with respect to the substrate 112 from its center to its outer edges, defined by its perimeter, or vice versa. Stated differently, flexing of the substrate 112, for example, typically allows for sufficient mutual contact with respect to connections located about its perimeter, while resulting in poor mutual contact with respect to the connections located about its center. In various embodiments of the present invention, the substrate 112 may experience a maximum deflection in a direction parallel with the Z-axis that may vary approximately from 5 to 15 micrometers, and more particularly from 8 to 10 micrometers.
For example, with continued reference to
For purposes of the present disclosure, the two dimensional curve of the substrate 112 is exaggerated in
For example, overdrive may be applied under such testing conditions in an attempt to achieve more uniform contact and lower electrical resistance. Generally, overdrive may refer to the driving or moving of either the card apparatus 104 or the chuck 106, as previously described, after already achieving contact between one or more of the probes 114 and the solder bumps 202. Such overdrive distance may exceed the predetermined distance. Overdrive may achieve more uniform contact and lower electrical resistance at the risk of causing damage to, for example, components of the wafer 108 or components of the card apparatus 104, among other components of the first test apparatus 100. For example, an excessive application of overdrive may cause an application of a contact force capable of damaging one or more chips of the wafer 108. Furthermore, the excessive application of overdrive may further induce flexing of the substrate 112.
In an embodiment of the present invention, the probe tip 302 and the probe base 304 may be electrically conductive, and may be configured for electrical connection to the substrate 112, as previously described. The probe tip 302 may be configured to contact and interconnect with a corresponding solder bump, as previously described, to thereby form an electrical connection with the wafer 108.
In an embodiment of the present invention, each of the probes 114 may be formed of one or more electrically conductive materials. Additionally, each of the probes 114, that is, with respect to the probe base 304, the surface 303, and the probe tip 302, either individually or in combination, may include metallic or alloy plating to obtain high conductivity, wear-resistance, non-cohesiveness, low impedance, or the like. For example, the probes 114 may be formed of copper material, and may include alloy plating in the form of nickel and gold.
In an embodiment of the present invention, the probe tip 302 may be concentrically-arranged and integrally formed with respect to a corresponding probe base 304, so as to extend in a generally perpendicular direction away from a surface 303 of the corresponding probe base 304. The probe tip 302 may be shaped so as to form a flat surface or a point, and may generally include a substantially circular cross-section. The probe base 304 may be cylindrical or tubular in form, and may include a diameter of approximately 130 micrometers and a height of approximately 18 micrometers. The probe tip 302 may be cylindrical or tubular in form, and may include a diameter of approximately 25 micrometers and a height of approximately 20 micrometers. The probe tip 302 may be configured to exert a pressure upon a corresponding solder bump 202 during testing, sufficient to overcome a surface tension upon contact thereof.
The second testing apparatus 400 represents automated test equipment, such as a pressing apparatus, which may be configured to perform one or more pressing operations on the wafer 108 prior to testing, as previously described, by the first test apparatus 100. The second test apparatus 400 may be completely or substantially similar to the first test apparatus 100; however, the second test apparatus 400 may include differences with respect to pressing structures 402, which may replace the probes 114.
In an embodiment of the present invention, the card apparatus 404 represents test equipment, such as a pressing card, which may be used in conjunction with automated test equipment. The card apparatus 404 may be completely or substantially similar to the card apparatus 104, as previously described; however, the card apparatus 404 may include differences with respect to the pressing structures 402, which may replace the probes 114. As such, the card apparatus 404 may include circuitry, which is identical or substantially similar to, the wafer testing circuitry of the card apparatus 104. The pressing circuitry may be configured to connect to the wafer testing circuitry of the test head 102, as previously described. The card apparatus 404 may include the substrate 112, as previously described, to which the pressing structures 402, may be attached in place of the probes 114. The pressing structures 402 may be used to press the solder bumps 202 prior to testing of the wafer 108. In various embodiments, the card apparatus 404 may be interchangeable with the card apparatus 104, or may take the form of a modified card apparatus 104, as described in further detail below.
With reference to
Prior to testing, one or more pressing operations may be performed after the performance of the reflow process described above. Like above with respect to
In embodiments of the present invention, a topology or surface topology formed by the pressing structures 402, and more particularly, by the pressing surfaces of the pressing structures 402, may exhibit variation which may resemble that of the probe tips 302 of the probes 114, as previously described. Such variation may be formed or caused in completely or substantially the same manner as that of the probes 114, as previously described.
With continued reference to
With reference to
Preferably, the predetermined drive distance used during pressing will match the predetermined drive distance used during testing. Alternatively or in combination, rather than driving the chuck 106 the predetermined distance, it may be driven until sufficient contact between the pressing structures 402 and the corresponding solder bumps 202 is established. Sufficient contact between the pressing structures 402 and the corresponding solder bumps 202 may be determined by, for example, measuring the electrical resistance at each of the pressing structures. The electrical resistance may be measured, for example, by way of the pressing circuitry of the card apparatus 404.
In various embodiments, the substrate 112 of the card apparatus 404 may experience deflection during pressing in a manner completely or substantially similar to that experienced by the substrate 112 of the card apparatus 104 during testing, as previously described above with reference to
Advantageously, the above pressing techniques may result in pressing of the solder bumps 202, such that the second topology of the solder bumps 202 may completely or substantially match, or conform to, a third topology of the pressing structures 402. Because the pressing structures 402 are substantially similar to the probes 114, but without probes tips, then the second topology of the solder bumps 202 will completely or substantially match, or conform to, the first topology of the probes 114. Stated differently, the variations in height of the solder bumps 202 produced by pressing, now after pressing, may completely or substantially match the variations in height of the pressing structures 402, as previously described, resulting in more uniform contact across the probes 114 and the solder bumps 202, and consequently enable low and uniform electrical resistance across the established interface during subsequent testing. Further, results produced by pressing may also reduce or eliminate the application of overdrive during testing, as previously described, reducing the degree to which flexing of the substrate 112 during testing may exacerbate inaccurate testing results, as previously described. This may be a result of, for example, similar flexing of the substrate 112 during pressing by the second testing apparatus 400.
For example, with continued reference to
In an embodiment of the present invention, the pressing surface 603 and the pressing base 604 may be electrically conductive, and may be configured for electrical connection to the substrate 112, as previously described. The pressing surface 603 may be configured to contact and press a corresponding solder bump 202, as previously described, to thereby press the corresponding solder bump 202 of the with the wafer 108 prior to testing.
In an embodiment of the present invention, each of the pressing structures 402 may be formed of one or more electrically conductive materials, in a manner completely or substantially similar to that of the probes 114, as previously described. Additionally, each of the pressing structures 402, that is, with respect to the pressing base 604 and the pressing surface 603, either individually or in combination, may include metallic or alloy plating completely or substantially similar to that of the probes 114, as previously described. In various embodiments, portions of testing structures, such as the probes 114, may be used to form or produce the pressing structures 402. For example, the probe tips 302 of the probes 114, as previously described, may be removed to produce or form the pressing structures 402.
In an embodiment of the present invention, the pressing surface 603 may be shaped so as to include one or more facets or sides configured to perform pressing of solder bumps. The one or more facets may be configured to completely or substantially resemble the probe surface 303, as previously described. The pressing base 604 may be cylindrical or tubular in form, and may generally include a substantially circular cross-section. In various embodiments, the pressing base 604 may include a diameter of approximately 130 micrometers and a height of approximately 18 micrometers. The pressing surface 603 may be configured to exert a pressure upon a corresponding solder bump 202 during pressing, sufficient to shape or form the solder bump 202.
As depicted in
