Process for determining an overflow to the format of the result of an arithmetic operation carried out on two operands

Abstract

A process is for determining an overflow to the format of the result of an arithmetic operation carried out by an arithmetic unit on two operands A and B and an input carry digit Cin. This process is executed in parallel to the processing done by the AU on operands A and B, before the AU has determined the result S of the operation.

Description

FIELD OF THE INVENTION

This invention relates to electronic circuits performing arithmetic operations, and, more particularly, to a process for determining if the format (or size) of the binary result S of an arithmetic operation between two operands A and B, and an input carry digit Cin exceeds the format allowed for this result.

BACKGROUND OF THE INVENTION

Techniques are known in the domain of integrated circuits using calculation units for verifying if the format allowed for the result of an arithmetic operation carried out by an AU (Arithmetic Unit) on two operands A and B and an input carry digit Cin does not exceed a given format. This technique has applications in most calculation units, such as, calculation units included in programmable circuits, such as, a digital signal processor (DSP) or a microcontroller. When it does, an “overflow beyond n bits” occurs and in this case a result saturation may be applied. In general, this type of overflow is determined after the result has been determined, that is, when the AU has finished processing of operands A and B and the input carry digit Cin. In other words, considering FIG. 1 which schematically shows the various processing steps between when operands A and B and the input carry digit Cin are input into the AU, and when the result S is written in the accumulator, the determination of an overflow is classically done after the calculation step E 2 .

Therefore, to determine if an overflow has occurred, it is necessary to wait until the AU has finished the calculation. In this case there is a time loss that is particularly long if the calculation done by the AU is complex.

SUMMARY OF THE INVENTION

An object of the invention is to overcome this disadvantage. Accordingly, the present invention is directed to a process capable of determining whether or not there will be an overflow of the result format at the same time as the calculation is being done by the AU, and, if so, to propose a saturation value for this result.

More precisely, the invention relates to a process for determining an overflow for an arithmetic operation carried out by an arithmetic unit (AU) on two operands A and B and an input carry digit Cin input to the AU. This process is characterized in that it is executed in parallel to the process done by the AU on the operands A and B and the input carry digit Cin, and before the AU has determined the result of the arithmetic operation.

Throughout the following description, reference will be made to an arithmetic operation carried out by an arithmetic unit (AU). However, this operation may also be done by an arithmetic and logic unit (ALU).

According to one embodiment of the invention, in which the operands A and B are binary numbers, at least one of the operands A and B has m bits and the format of the required result S has n bits (where n<m), the process includes the steps of: considering only the m−n+1 highest order bits denoted A H for operand A, and B H for operand B and an output carry digit Cout n−2 of rank n−2; and checking if A H , B H and Cout n−2 satisfy a saturation condition, and if so, deducing that the size of the result S exceeds n bits. According to this embodiment, the positive saturation condition in the case of an addition is:

A H +B H +Cout n−2 ≧1,

and the negative saturation condition in the case of an addition is:

A H +B H +Cout n−2 <−1,

where Cout n−2 is the output carry digit of rank n−2 in the arithmetic operation of A, B and Cin.

According to another embodiment of the invention in which the operands A and B are binary numbers, at least one of the operands A and B has m bits and the format of the searched result S has n bits where n<m, the process includes the steps of:

determining the propagation terms p i and generation terms g i each defined by a logical relation between components a i and b i of operands A and B;

considering only the m−n+1 highest order bits, denoted P H for propagation terms p i and G H for generation terms g i , and the output carry digit of rank n−2; and

checking if P H , G H and Cout n−2 satisfy a saturation condition, and if so deducing that the size of the result S exceeds n bits.

If A is expressed on 40 bits and B on 32 bits with n=32 and m=40, the positive saturation conditions are:

g 31 =1 and (∀iε [39:32], p i =1) and Cout 30 =1;

or p 39 =1 and g 39 =0 and (∃iε [38:32], g i =1);

or g 39 =0 and (∀iε [39:31], p i =0) and Cout 30 =1;

or p 39 =0 and (∃iε [38:31], p i =1) and g 39 =0;

and the negative saturation conditions are:

g 39 =1 and (∃iε [38:31], g i =0);

or (∀iε [39:31], g i =1) and Cout 30 =0;

or p 39 =1 and (∃iε [38:32], p i =0) and ∀iε [38:32], g i =0

or (∀iε [39:32], p i =1) and p 31 =0 and g 31 =0 and

Cout 30 =0

In the following description of the process according to the invention, it will be considered that A and B are two binary numbers, that at least one of A and B has m bits, and that the result S is a binary number with m bits corrected to format with n bits (where A, B and S are coded in two's complement), where n and m depend on the use of the calculation unit. The process according to the invention checks whether the format of the result S that the AU has to calculate will have n bits or less than n bits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically shows the main steps in the process according to the invention;

FIG. 2 shows a table representing the various saturation conditions for a DSP 950 if operands A and B are written with terms A H , A L , B H , B L ; and

FIG. 3 shows a table containing saturation conditions for an ST10 microcontroller if operands A and B are written with terms A H , A L , B H , B L .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 schematically shows the various steps in the process according to the invention. This FIG. 1 shows the AU 1 into which operands A and B and the input carry digit Cin are input, and which carries out processing (step E 1 , step E 2 ) on operands A and B and Cin to produce an output result S. This result S is sent to a multiplexer 2 during a step E 3 .

At the same time as the processing done by the AU during steps E 1 to E 3 , the process according to the invention determines whether or not the format of the result S will exceed the format allowed for it. This determination is done during a step E 4 by an evaluation unit 4 which receives the data supplied by the AU as input. These data may be of two different types, which will be described later.

If the format of the result S exceeds the specified format, the evaluation unit 4 generates a SAT − negative saturation flag or a SAT + positive saturation flag. This information may be used either as flags or to control multiplexer 2 which receives the value of the result S, the negative saturation value −2 n−1 and the positive saturation value 2 n−1 −1, as an input. If this is not the case, the evaluation unit 4 sends a NON-SAT message to multiplexer 2 , meaning that saturation did not occur (in other words there was no overflow of the format) and that the result S may be loaded as soon as it has been determined. The result S or the saturation value chosen by the evaluation unit 4 may then be written in an accumulator 3 , in a step E 6 .

In the following description of the process according to the invention, it will be considered that A and B are two binary numbers with m bits, and that the result S is a binary number with m bits corrected to format with n bits (where A, B and S are coded in two's complement), where n and m depend on the use of the calculation unit. The process according to the invention checks whether the format of the result S that the AU has to calculate will have n bits or less than n bits.

In general, determining an overflow (also called “saturation”) of the format of result S includes checking if one of the positive or negative saturation conditions expressed as a function of A H , B H and Cout n−2 (Cout n−2 is the output carry digit of rank n−2) is satisfied, where:

A H and B H are such that A=A H ·2 n−1 +A L and B=B H ·2 n−1 +B L

More precisely: $$ A = ∑ i = 0 m - 1 ⁢   ⁢ a i ⁢ 2 i = ∑ i = n - 1 m - 1 ⁢   ⁢ a i ⁢ 2 i + ∑ i = 0 n - 2 ⁢   ⁢ a i ⁢ 2 i = A H ⁢ 2 n - 1 + A L $$ where $$ A H = ∑ i = n - 1 m - 1 ⁢   ⁢ a i ⁢ 2 i - n + 1 ⁢   ⁢ and ⁢   ⁢ A L = ∑ i = 0 n - 2 ⁢   ⁢ a i ⁢ 2 i

Therefore, the term A H corresponds to the m−n+1 highest order bits which include a sign bit and the m−n highest order bits. Similarly: $$ B = ∑ i = 0 m - 1 ⁢   ⁢ b i ⁢ 2 i = ∑ i = n - 1 m - 1 ⁢   ⁢ b i ⁢ 2 ⁢ i + ∑ i = 0 n - 2 ⁢   ⁢ b i ⁢ 2 i = B H ⁢ 2 ⁢ n - 1 + B L $$ where $$ B H = ∑ i = n - 1 m - 1 ⁢   ⁢ b i ⁢ 2 i - n + 1 ⁢   ⁢ and ⁢   ⁢ B L = ∑ i = 0 n - 2 ⁢   ⁢ b i ⁢ 2 i

Therefore, the term B H corresponds to the m−n+1 highest order bits that include a sign bit and the m−n highest order value bits.

For example, for the case of an addition, it is necessary to positively saturate the result S as soon as its format exceeds n bits, namely S≧2 n−1 , which is equivalent to writing A+B+Cin≧2 n−1 .

Furthermore: $$ S = ∑ i = 0 m - 1 ⁢   ⁢ S i ⁢ 2 i = ∑ i = n - 1 m - 1 ⁢   ⁢ S i ⁢ 2 i + ∑ i = 0 n - 2 ⁢   ⁢ S i ⁢ 2 i = S H ⁢ 2 n - 1 + S L $$ where $$ S H = ∑ i = n - 1 m - 1 ⁢   ⁢ s i ⁢ 2 i - n + 1 ⁢   ⁢ and ⁢   ⁢ S L = ∑ i = 0 n - 2 ⁢   ⁢ s i ⁢ 2 i

Moreover, S≧2 n−1 means S H ≧1, hence a positive saturation condition:

A H +B H +Cout n−2 ≧1,

where Cout n−2 is the output carry digit of rank n−2.

A negative saturation of the result S results in S<−2 n−1 , which is equivalent to writing A+B+Cin<−2 n−1 . Furthermore, S<−2 n−1 means S H <1; therefore the negative saturation condition can be written:

A H +B H +Cout n−2 <−1

where Cout n−2 is the output carry digit of rank n−2.

We will now describe two example applications of the process according to the invention. For these examples, the process is applied firstly to a DSP 950 signal processor, and secondly to an ST 10 microcontroller. In these two examples, m is equal to 40 and n is equal to 32. In other words, the arithmetic operation for these two examples is carried out on 40 bits and the saturation format is 32 bits. Furthermore, restrictive assumptions concerning operand B are used in the DSP 950 and the ST 10. In particular for the DSP 950, it is considered that A is expressed on 40 bits and B can be expressed on 32 bits and then extended to 40 bits; therefore the 9 highest order bits are identical; and we then have:

B H =111111111 or B H =000000000, in other words:

B H −1 or B h =0.

In this case, four positive saturation conditions of S can be determined which are summarized in the right part of the table in FIG. 2 .

More precisely, these four conditions are:

B H =0 and A H >0;

or B H −1 and A H >1;

or B H =0 and A H =0 and Cout 30 =1;

or B H −1 and A H =1 and Cout 30 =1.

Considering the previous assumption about B H , in other words B H −1 or B H =0, four negative saturation conditions of S are also determined. These four conditions are summarized in the left part of the table in FIG. 2 .

More precisely, these conditions are:

B H =0 and A H <−2;

or B H =−1 and A H <−1;

or B H =0 and A H =−2 and Cout 30 =0;

or B H =−1 and A H =−1 and Cout 30 =0.

In the case of the ST 10 microcontroller, the assumption is made that A is expressed on 40 bits and B is expressed on 33 bits and then extended to 40 bits; therefore the 8 highest order bits are identical; we then have:

B H =111111110 or B H =111111111,

or B H =000000000 or B H =000000001, in other words:

B H −2 or B H −1 or B H =0 or B H =1.

In this case, 8 positive saturation conditions of S can be determined, which are summarized in the right part of the table in FIG. 3 .

More precisely, these conditions are:

B H =−2 and A H >2;

or B H =−1 and A H >1;

or B H =0 and A H >0;

or B H =1 and A H >−1;

or B H =−2 and A H =2 and Cout 30 =1;

or B H =−1 and A H =1 and Cout 30 =1;

or B H =0 and A H =0 and Cout 30 =1;

or B H =1 and A H =−1 and Cout 30 =1.

Considering the previous assumption about B H , it is also possible to determine 8 negative saturation conditions that are summarized in the left part of the table in FIG. 3 .

More precisely, these conditions are:

B H =−2 and A H <0;

or B H =−1 and A H <−1;

or B H =0 and A H <−2;

or B H =1 and A H <−3;

or B H =−2 and A H =0 and Cout 30 =0;

or B H =−1 and A H =−1 and Cout 30 =0;

or B H =0 and A H =−2 and Cout 30 =0;

or B H =1 and A H =−3 and Cout 30 =0.

Therefore as we have just seen, the first embodiment of the invention includes determining a possible overflow by checking if the values A H , B H and Cout n−2 satisfy the saturation conditions given above. A second embodiment of the invention includes using the propagation term P and the generation term G determined by the AU to determine if there will be an overflow of the format.

To accelerate processing by the AU, there are known methods of determining propagation terms p i and generation term g i , both of which are functions of a i and b i . In other words, the AU determines terms p i and g i such that:

p i =f 1 (a i , b i , NP, NG);

and g i =f 2 (a i , b i , NP, NG),

where NP and NG are two vectors that are used to choose the arithmetic operation to be done (addition, subtraction, etc.).

p i and g i are defined differently as a function of a i and b i depending on the operation to be done.

In particular in the case of an addition, the propagation and generation terms are as follows:

p i =a i ⊕ b i ;

and g i =a i ·b i ,

where the symbol “⊕” means exclusive OR and “.” means AND.

In the case of a subtraction, p i and g i may be determined as follows:

p i ={overscore (a i +L ⊕b i +L )}; and g i =a i ·{overscore (b i +L )}.

Therefore, the result S of the operation is expressed as a function of the terms p i and g i :

S=f 3 (A, B, C in );

therefore S=f 4 (P, G, C in ).

The bits of S with order m−1 to n−1 are the only bits that are useful for detecting an overflow; they may be expressed as a function of the output carry digit of rank n−2, Cout n−2 , and the highest order terms p i and g i :

S m−1,n−1 =f 5 (p j , g j , Cout n−2 ) where n−1≦j≦m−1.

Thus, the P and G terms are defined differently with respect to operands A and B, depending on the arithmetic operation chosen. On the other hand, the relation given above for S m−1,n−1 is always the same, such that saturation detection is the same for an addition, a subtraction and all operations for which P and G may be defined as a function of the operands A and B.

Therefore, the process according to the invention includes using these terms P and G to determine a possible overflow of the result S. When the AU has determined these terms P and G (step E 1 ), it transmits them to the evaluation unit 4 which determines whether or not there will be an overflow, by checking whether or not one of the saturation conditions is verified.

These saturation conditions based on the terms P H and G H are determined from the previously given conditions on A H and B H , and considering that: $$ P = ∑ i = 0 m - 1 ⁢   ⁢ p i ⁢ 2 i = ∑ i = n - 1 m - 1 ⁢   ⁢ p i ⁢ 2 i + ∑ i = 0 n - 2 ⁢   ⁢ p i ⁢ 2 i = P H ⁢ 2 ⁢ n - 1 + P L $$ where $$ P H = ∑ i = n - 1 m - 1 ⁢   ⁢ p i ⁢ 2 i - n + 1 ⁢   ⁢ and ⁢   ⁢ P L = ∑ i = 0 n - 2 ⁢   ⁢ p i ⁢ 2 i $$ G = ∑ i = 0 m - 1 ⁢   ⁢ g i ⁢ 2 i = ∑ i = n - 1 m - 1 ⁢   ⁢ g i ⁢ 2 i + ∑ i = 0 n - 2 ⁢   ⁢ g i ⁢ 2 i = G H ⁢ 2 n - 1 + G L $$ where $$ G H = ∑ i = n - 1 m - 1 ⁢   ⁢ g i ⁢ 2 i - n + 1 ⁢   ⁢ and ⁢   ⁢ G L = ∑ i = 0 n - 2 ⁢   ⁢ g i ⁢ 2 i

Using the assumptions given above for A H and B H for a DSP 950 signal processor, the following saturation conditions are determined:

Positive saturation conditions:

B H =0 and A H >O,

if B H =0 then $$ &AutoLeftMatch; { P H = A H ⁢   and ⁢   ⁢ G H = 000000000 ⁢   ⁢  

if A H >0 then $$ &AutoLeftMatch; { a 39 = 0 ⁢   and ⁢   ⁢ ∃ i ⁢   ⁢ ϵ ⁡ [ 38 ⁢ : ⁢ 31 ] , a i = 1

then: p 39 =0 and (∃iε [38:31], p i =1) and g 39 =0;

B H =−1 and A H >1,

if B H =0 then $$ &AutoLeftMatch; { P H = A H _ ⁢   and ⁢   ⁢ G H = A H

if A H >1 then $$ &AutoLeftMatch; { a 39 = 0 ⁢   and ⁢   ⁢ ∃ i ⁢   ⁢ ϵ ⁡ [ 38 ⁢ : ⁢ 32 ] , a i = 1

then p 39 =1 and (∃iε [38:32], g i =1) and g 39

if B H =0 and A H =0 and Cout 30 =1,

then $$ &AutoLeftMatch; { P H = 0 ⁢   and ⁢   ⁢ G H = 0

then: ∀iε [39:31], p i =0 and g 39 =0 and Cout 30 =1;

B H =−1 and A H =+1 and Cout 30 =1,

if B H =−1 then

since A H =1,

then (∀iε [39:32], p i =1) and g 31 =1 and Cout 30 =1.

Negative saturation conditions:

B H =0 and A H <−2,

if B H =0 then $$ &AutoLeftMatch; { P H = A H ⁢   and ⁢   ⁢ G H = 000000000 ⁢   ⁢  

if A H <−2 then $$ { a 39 = 1 and ⁢   ⁢ ∃ i ∈ [38:32] , a i = 0 &AutoLeftMatch;

then p 39 =1 and ∃iε [38:32], p i =0

and ∀iε [38:32], g i =0;

B H =−1 and if A H <−1,

if B H =−1 then

if A H <−1 then $$ { a 39 = 1 and ⁢   ⁢ ∃ i ∈ [38:31] , a i = 0 &AutoLeftMatch;

then g 39 =1 and ∃iε [38:31], g i =0;

B H =0 and A H =−2 and Cout 30 =0,

if B H =0 then $$ { P H = A H and ⁢   ⁢ G H = 0 &AutoLeftMatch;

if A H =−2 then $$ { a 31 = 0 and ⁢   ⁢ ∀ i ∈ [39:32] , a i = 1 &AutoLeftMatch;

then (∀iε [39:32], p i =1) and p 31 =0 and g 31 =0

and Cout 30 =0;

B H =−1 and A H =−1 and Cout 30 =0,

if B H =−1 then

if A H =−1 then ∀iε [39:31], a 1 =1

then (∀iε [39:31], g i =1) and Cout 30 =0.

The assumptions given above are used in the case of the ST 10 microcontroller. The following positive saturation conditions are then deduced:

if B H =−2 and A H >2

or if B H =−1 and A H >1

then p 39 1 and g 32 =1 and (p 31 )XOR (g 31 )=1

or p 39 =1 and ∃iε [38:33], g i =1;

if B H =0 and A H >0

or if B H 1 and A H >−1,

which corresponds to $$ { B H ≥ 0 ⁢   ⁢ and ⁢   ⁢ A > - 1 and ⁢   ⁢ not ⁢   ⁢ ( B H = 0 ⁢   ⁢ and ⁢   ⁢ A H = 0 ) &AutoLeftMatch;

then p 39 =0 and g 39 =0

and NOT (∀iε [38:31], p i =0 and g 31 =0)

if B H =−2 and A H =2 and Cout 30= 1,

which corresponds to $$ { ( ∀ i ∈ [39:32] , p i = a i _ ⁢   ⁢ and ⁢   ⁢ g i = a i ) and ⁢   ⁢ p 31 = a 31 and ⁢   ⁢ g 31 = 0 and ⁢   ⁢ Cout 30 = 1 &AutoLeftMatch;

then: (∀iε [39:32], p i =1) and p 31 =0 and g 32 =1

and g 31 =0 and Cout 30 =1;

B H =−1 and A H =1 and Cout 30 =1,

if B H =−1 then $$ { P H = A H _ and ⁢   ⁢ G H = A H &AutoLeftMatch;

the condition becomes $$ { p 39 = 1 and ⁢   ⁢ ∀ i ∈ [38:32] , p i = 1 and ⁢   ⁢ g 31 = 1 and ⁢   ⁢ Cout 30 = 0 &AutoLeftMatch;

then: (∀iε [39:32], p i =1) and g 31 =1 and Cout 30 =1;

B H =0 and A H =0 and Cout 30 =1,

when A H =0 and $$ B H = 0 , { P H = 0 and ⁢   ⁢ G H = 0

then: (∀iε [39:31], p i =0) and g 39 =0 and g 31 =0 and Cout 30 =1;

B H =1 and A H =−1 and Cout 30 =1,

when A H =−1 then $$ { P H = B _ H and ⁢   ⁢ G H = B H &AutoLeftMatch;

when A H =−1 and $$ B H = 1 , { P 39 = 1 and ⁢   ⁢ ∀ i ∈ [38:32] , p i = 1 and ⁢   ⁢ g 31 = 1

then (∀iε [39:32], p i =1) and g 31 =1 and Cout 30 =1,

and the negative saturation conditions:

if B H =−2 and A H <0

or if B H =−1 and A H <−1,

which corresponds to $$ { B H < 0 and ⁢   ⁢ A H < 0 and ⁢   ⁢ not ⁢   ⁢ ( B H = - 1 ⁢   ⁢ and ⁢   ⁢ A H = - 1 ) &AutoLeftMatch;

then g 39 =1 and ∃iε [38:31], g i =0;

B H =0 and A H <−2,

when B H =0 then $$ { P H = A H and ⁢   ⁢ G H = 000000000 &AutoLeftMatch;

then $$ { a 39 = 1 and ⁢   ⁢ ∃ i = [38:32] , a i = 0 &AutoLeftMatch;

then: p 39 =1 and ∃iε [38:32], p i =0

and ∀iε [38:32], g i =0;

B H =1 and A H <−3,

when $$ B H = 1 , { ( ∀ i ∈ [39:32] , p i = a i ⁢   ⁢ and ⁢   ⁢ g 1 = 0 ) and ⁢   ⁢ p 31 = a 31 ⁢   _ ⁢   ⁢ and ⁢   ⁢ g 31 = a 31 &AutoLeftMatch;

when $$ A H < - 3 , { A H < 0 and ⁢   ⁢ A H ≠ - 1 and ⁢   ⁢ A H ≠ - 2 and ⁢   ⁢ A H ≠ - 3

then: p 39 =1 and ∃iε [38:32], g i =0

and not (∀iε [38:32], p i =1)

and not (∀iε [38:33],p i =1 and p 32 =0 and g 31 =1);

B H =−2 and A H =0 and Cout 30 =0,

when $$ B H = - 2 , { ( ∀ i ∈ [39:32] , p i = a i _ ⁢   ⁢ and ⁢   ⁢ g i = a i ) and ⁢   ⁢ p 31 = a 31 ⁢   and ⁢   ⁢ g 31 = 0

when A H =0, ∀iε [39:31], a i =0

then (∀iε [39:32], p i =1) and p 31 =0 and g 31 =0 and Cout 30 =0;

B H =−1 and A H =−1 and Cout 30 =0,

when $$ B H = - 1 , { P H = A _ H and ⁢   ⁢ G H = A H

when A H =−1, ∀iε [39:31], a i =1

when A H =−1, ∀iε [39:31], a i =1

then (∀iε [39:31], g i =1) and Cout 30 =0;

if B H =0 and A H =−2 and Cout 30 =0,

when $$ B H = 0 , { P H = A _ H and ⁢   ⁢ G H = 0

when $$ A H = - 2 , { a 31 = 0 and ⁢   ⁢ ∀ i ∈ [39:32] , a i = 1

then (∀iε [39:32], p i =1) and p 31 =0 and g 31 =0 and Cout 30 =0;

if B H =1 and A H =−3 and Cout 30 =0,

when $$ B H = 1 , { ( ∀ i ∈ [39:32] , p i = a i ⁢   ⁢ and ⁢   ⁢ g i = 0 ) and ⁢   ⁢ p 31 = a 31 ⁢   ⁢ and ⁢   ⁢ g 31 = a 31

then (∀iε [39:33], p i =1) and p 32 =0 and g 32 =0 and g 31 =1 and Cout 30 =0.

Regardless of the method used to determine if there is an overflow, the process according to the invention includes supplying the multiplexer with a positive saturation value VALSAT+ or a negative saturation value VALSAT−, if an overflow is detected.

where VALSAT + =2 n−1 −1

VALSAT − =−2 n−1

If the format that must not be exceeded is 32 bits, then:

VALSAT − =FF 8 000 0000 h;

and VALSAT + =00 7 FFF FFFF h.

If no overflow is detected, the evaluation unit 4 sends a NON-SAT message to the multiplexer 2 informing it that it can load the result S as soon as it has been determined.

Claims

1. A method for determining an overflow to a format of a result of an arithmetic operation carried out by an arithmetic unit on two operands A and B and an input carry digit Cin input to the arithmetic unit, operands A and B being binary numbers and at least one of the operands A and B having m bits, the format of the result having n bits where n<m, the method comprising the steps of:considering only the m−n+1 highest order bits of operand A and operand B and an output carry digit Coutn−2 of rank n−2; and checking whether or not the m−n+1 bits satisfy a saturation condition, and if so deducing a size the result will exceed n bits; both the considering and checking steps being carried out in parallel with processing done by the arithmetic unit on operands A and B before the arithmetic unit has determined the result of the arithmetic operation.

2. A method according to claim 1, wherein the m−n+1 highest order bits of operand A are denoted AH and the m−n+1 highest order bits of operand B are denoted BH and wherein the positive saturation condition is:AH+BH+Coutn−2≧1, and a negative saturation condition is: AH+BH+Coutn−2<−1.

3. A method according to claim 2, wherein when A is expressed on 40 bits and B is expressed on 32 bits with n=32 and m=40, the positive saturation conditions are:BH=0 and AH>0; BH=−1 and AH>1; BH=0 and AH=0 and Cout30=1; BH=−1 and AH=1 and Cout30=1; and the negative saturation conditions are: BH=0 and AH<−2; BH=−1 and AH<−1; BH=0 and AH=−2 and Cout30=0; BH=−1 and AH=−1 and Cout30=0.

4. A method according to claim 3, wherein when A is expressed on 40 bits and B is expressed on 33 bits, with n=32 and m=40, the positive saturation conditions are:BH=−2 and AH>2; BH=−1 and AH>1; BH=0 and AH>0; BH=1 and AH>−1; BH=−2 and AH=2 and Cout30=1; BH=−1 and AH=1 and Cout30=1; BH=0 and AH=0 and Cout30=1; BH=1 and AH=−1 and Cout30=1; and the negative saturation conditions are: BH=−2 and AH<0; BH=−1 and AH<−1; BH=0 and AH<−2; BH=1 and AH<−3; BH=−2 and AH=0 and Cout30=0; BH=−1 and AH=−1 and Cout30=0; BH=0 and AH=−2 and Cout30=0; BH=1 and AH=−3 and Cout30=0.

5. A method according to claim 1, further comprising the step of determining propagation terms pi and generation terms gi each defined by a logical relation between components ai and bi of operands A and B before the considering or checking steps; and wherein the step of checking is based on using the m−n+1 highest order bits, denoted PH for propagation terms pi and denoted GH for generation terms gi, and the output carry digit Coutn−2 of rank n−2.

6. A method according to claim 5, wherein when A is expressed on 40 bits and B is expressed on 32 bits with n=32 and m=40, the positive saturation conditions are:g31=1 and (∀iε (39:32), pi=1) and Cout30=1; p39=1 and g39=0 and ∃iε (38:32), gi=1; ∀iε (39:31), pi=0 and Cout30=1; p39=0 and (∃iε (38:31), pi=1) and g39=0; and the negative saturation conditions are: g39=1 and (∃iε (38:31), gi=0); ∀iε (39:31), gi=1 and Cout30=0; p39=1 and ∃iε (38:32), pi=0 and ∀iε (38:32), gi=0 (∀iε (39:32), pi=1) and g31=0 and Cout30=0 and p31=0.

7. A method according to claim 6, wherein when A is expressed on 40 bits and B is expressed on 33 bits with n=32 and m=40, the positive saturation conditions are:P39=1 and g32=1 and (p31) XOR (g31)=1 p39=1 and ∃iε (38:33), gi=1; p39=0 and g39=0 and NOT (∀iε (38:31), pi=0 and g31=0); (∀iε (39:32), pi=1) and p31=0 and g32=1 and g31=0 and Cout30=1; (∀iε (39:32), pi=1) and g31=1 and Cout30=1; (∀iε (39:31), pi=0) and g39=0 and g31=0 and Cout30=1; and the negative saturation conditions are: g39=1 and ∃iε (38:31), gi=0 p39=1 and ∃iε (38:32), pi=0; and ∀iε (38:32), gi=0; p39=1 and ∀iε (38:32), gi=0; and not (∀iε (38:32), pi=1) and not (∀iε (38:33), pi=1 and p32=0 and g31=1) (∀iε (39:32), pi=1) and p31=0 and g31=0 and Cout30=0; (∀iε (39:31), gi=1) and Cout30=0; (∀iε (39:33), pi=1) and p32=0 and g32=0 and g31=1 and Cout30=0.

8. A method according to claim 1, further comprising the step of saturating the result to a binary value 2n−1−1 for a positive saturation of a format with n bits, and to a binary value −2n−1 for a negative saturation of a format with n bits responsive to an overflow.

9. A method for determining an overflow to a format of a result of an arithmetic operation carried out by an arithmetic unit on two operands A and B and an input carry digit Cin input to the arithmetic unit, operands A and B being binary numbers and at least one of the operands A and B having m bits, the format of the result having n bits where n<m, the method comprising the steps of:considering only the m−n+1 highest order bits of operand A and operand B and an output carry digit Coutn−2 of rank n−2; checking whether or not the m−n+1 bits satisfy a saturation condition, and if so deducing a size the result will exceed n bits; both the considering and checking steps being carried out in parallel with processing done by the arithmetic unit on operands A and B before the arithmetic unit has determined the result of the arithmetic operation; wherein the m−n+1 highest order bits of operand A are denoted AH and the m−n+1 highest order bits of operand B are denoted BH and wherein the positive saturation condition is: AH+BH+Coutn−2≦1, and a negative saturation condition is: AH+BH+Coutn−2<−1; and saturating the result to a binary value 2n−1−1 for a positive saturation of a format with n bits, and to a binary value −2n−1 for a negative saturation of a format with n bits.

10. A method according to claim 9, wherein when A is expressed on 40 bits and B is expressed on 32 bits with n=32 and m=40, the positive saturation conditions are:BH=0 and AH>0; BH=−1 and AH>1; BH=0 and AH=0 and Cout30=1; BH=−1 and AH=1 and Cout30=1; and the negative saturation conditions are: BH=0 and AH<−2; BH=−1 and AH<−1; BH=0 and AH=−2 and Cout30=0; BH=−1 and AH=−1 and Cout30=0.

11. A method according to claim 9, wherein when A is expressed on 40 bits and B is expressed on 33 bits, with n=32 and m=40, the positive saturation conditions are:BH=−2 and AH>2; BH=−1 and AH>1; BH=0 and AH>0; BH=1 and AH>−1; BH=−2 and AH=2 and Cout30=1; BH=−1 and AH=1 and Cout30=1; BH=0 and AH=0 and Cout30=1; BH=1 and AH=−1 and Cout30=1; and the negative saturation conditions are: BH=−2 and AH<0; BH=−1 and AH<−1; BH=0 and AH<−2; BH=1 and AH<−3; BH=−2 and AH=0 and Cout30=0; BH=−1 and AH=−1 and Cout30=0; BH=0 and AH=−2 and Cout30=0; BH=1 and AH=−3 and Cout30=0.

12. A method for determining an overflow to a format of a result of an arithmetic operation carried out by an arithmetic unit on two operands A and B and an input carry digit Cin input to the arithmetic unit, operands A and B being binary numbers and at least one of the operands A and B having m bits, the format of the result having n bits where n<m, the method comprising the steps of:considering only the m−n+1 highest order bits of operand A and operand B and an output carry digit Coutn−2 of rank n−2; checking whether or not the m−n+1 bits satisfy a saturation condition, and if so deducing a size the result will exceed n bits; both the considering and checking steps being carried out in parallel with processing done by the arithmetic unit on operands A and B before the arithmetic unit has determined the result of the arithmetic operation; determining propagation terms pi and generation terms gi each defined by a logical relation between components ai and bi of operands A and B before the considering or checking steps; wherein the step of checking is based on using the m−n+1 highest order bits, denoted PH for propagation terms pi and denoted GH for generation terms gi, and the output carry digit Coutn−2 of rank n−2; and saturating the result to a binary value 2n−1−1 for a positive saturation of a format with n bits, and to a binary value −2n−1 for a negative saturation of a format with n bits.

13. A method according to claim 12, wherein when A is expressed on 40 bits and B is expressed on 32 bits with n=32 and m=40, the positive saturation conditions are:g31=1 and (∀iε (39:32), pi=1) and Cout30=1; p39=1 and g39=0 and ∃iε (38:32), gi=1; ∀iε (39:31), pi=0 and Cout30=1; p39=0 and (∃iε (38:31), pi=1) and g39=0; and the negative saturation conditions are: g39=1 and (∃iε (38:31), gi=0); ∀iε (39:31), gi=1 and Cout30=0; p39=1 and ∃iε (38:32), pi=0 and ∀iε (38:32), gi=0 (∀iε (39:32), pi=1) and g31=0 and Cout30=0 and p31=0.

14. A method according to claim 12, wherein when A is expressed on 40 bits and B is expressed on 33 bits with n=32 and m=40, the positive saturation conditions are:p39=1 and g32=1 and (p31) XOR (g31)=1 p39=1 and ∃iε (38:33), gi=1; p39=0 and g39=0 and NOT (∀iε (38:31), pi=0 and g31=0); (∀iε (39:32), pi=1) and p31=0 and g32=1 and g31=0 and Cout30=1; (∀iε (39:32), pi=1) and g31=1 and Cout30=1; (∀iε (39:31), pi=0) and g39=0 and g31=0 and Cout30=1; and the negative saturation conditions are: g39=1 and ∃iε (38:31), gi=0 p39=1 and ∃iε (38:32), pi=0; and ∀iε (38:32), gi=0; p39=1 and ∃iε (38:32), gi=0; and not (∀iε (38:32), pi=1) and not (∀iε (38:33), pi=1 and p32=0 and g31=1) (∀iε (39:32), pi=1) and p31=0 and g31=0 and Cout30=0; (∀iε (39:31), gi=1) and Cout30=0; (∀iε (39:33), pi=1) and p32=0 and g32=0 and g31=1 and Cout30=0.

15. An apparatus for performing an arithmetic operation comprising:an arithmetic unit; and overflow determining means for determining an overflow to a format of a result of an arithmetic operation carried out by the arithmetic unit on two operands A and B and an input carry digit Cin input to the arithmetic unit, operands A and B being binary numbers and at least one of the operands A and B having m bits, the format of the result having n bits where n<m, the overflow determining means comprising considering means for considering only the m−n+1 highest order bits of operand A and operand B and an output carry digit Coutn−2 of rank n−2; and checking means for checking whether or not the m−n+1 bits satisfy a saturation condition, and if so deducing a size of the result S will exceed n bits; both the considering and checking means carrying out operations in parallel with processing done by the arithmetic unit on operands A and B before the arithmetic unit has determined the result of the arithmetic operation.

16. An apparatus according to claim 15, further comprising means for saturating the result to a binary value 2n−1−1 for a positive saturation of a format with n bits, and for saturating the result to a binary value −2n−1 for a negative saturation of a format with n bits based upon an overflow.

17. An apparatus for performing an arithmetic operation comprising:an arithmetic unit; and an overflow determining unit for determining an overflow to a format of a result of an arithmetic operation carried out by said arithmetic unit on two operands A and B and an input carry digit Cin input to said arithmetic unit, operands A and B being binary numbers and at least one of the operands A and B having m bits, the format of the result having n bits where n<m, said overflow determining unit considering only the m−n+1 highest order bits of operand A and operand B and an output carry digit Coutn−2 of rank n−2, said overflow determining unit also checking whether or not the m−n+1 bits satisfy a saturation condition, and if so deducing a size of the result S will exceed n bits; said overflow determining unit carrying out operations in parallel with processing done by said arithmetic unit on operands A and B before said arithmetic unit has determined the result of the arithmetic operation.

18. An apparatus according to claim 17 wherein said overflow determining unit saturates the result to a binary value 2n−1−1 for a positive saturation of a format with n bits, and saturates the result to a binary value −2n−1 for a negative saturation of a format with n bits based upon an overflow.