Patent Application
20090197407
The present invention relates to a process by which optimized polysilicon structures, in particular for gate electrodes of memory cells, can be produced.
In many semiconductor components, interconnects or electrodes made of polysilicon are patterned on a top side. For this purpose, a polysilicon layer is applied over the whole area, and subsequently patterned using a mask, in particular by means of a photoresist and photolithography. In the region of the mask openings, the polysilicon is removed by etching, which may be effected for example by means of RIE (reactive ion etching). The gate electrodes of transistor structures which are also used for memory cells of semiconductor memory components are produced in this way. EEPROM components are provided so-called floating gate electrodes, which are arranged between a control gate electrode above the channel region of the transistor and are electrically insulated all around. Charge carriers are accumulated on said floating gate electrodes during programming.
In the customary production process, such electrodes in polysilicon are produced with rather sharp, at least approximately right-angled edges. What is disadvantageous in this case is that the electric field assumes particularly high values at edges and points of conductor surfaces, with the result that conditions are present there for a breakdown and a discharge through the electrically insulating material. This fact adversely affects a multiplicity of applications of the semiconductor components. Therefore, it is desirable to have available a simple process by which the electrode structures can be formed without excessively sharp edges or corners. One possibility for achieving this is reoxidation of the polysilicon surfaces at a high oxidation temperature. However, rounded corners can be produced by this process only as long as the dimensions of the structures produced lie above a specific limit. This is because the temperatures that can be employed are limited depending on the structure width, so that in the case of very small structures, rounded edges cannot be produced by means of the oxidation steps and in fact that sharpness of the edges becomes even more greatly pronounced.
The customary mask technique for patterning semiconductor layers uses photolithography, by means of which an applied photoresist is exposed in a manner corresponding to the structures to be produced and is then developed. Depending on the type of photoresist, the exposed portions or the unexposed portions are removed after development. In order to improve the optical conditions during photolithography, an antireflection layer is provided below the photoresist. The antireflection layers are usually very thin in relation to the resist layers. One commercially available material used as BARC (bottom antireflective coating) is WIDE-15 from the company Brewer Science.
It is an object of the present invention to specify a process for producing polysilicon electrodes with sufficient rounded edges which is suitable even for very small structure dimensions.
This object is achieved by means of the process having the features of claim 1. Refinements emerge from the dependent claims.
In this process, an auxiliary layer is applied to a polysilicon layer to be patterned, said auxiliary layer preferably being made of a material that is suitable for an antireflection layer. A resist mask is applied thereon, and the auxiliary layer is provided laterally with hollowed-out recesses, so that rounded edges are produced in a subsequent etching step for the envisaged patterning of the polysilicon layer. The etching step is effected essentially anisotropically in a direction perpendicular to the topside of the component, the resist mask shielding the etching attack. In the narrow regions of the lateral hollowed-out recesses of the auxiliary layer present below the resist mask, the upper edges of the polysilicon are also exposed to the etching attack, albeit to a smaller extent. Consequently, the polysilicon is removed at these locations to an extent such that the upper edges of the polysilicon electrodes produced are not formed in sharp-edged or pointed fashion, but rather with roundings. This results in a significantly better operating characteristic (performance) of the components thus produced, which is manifested particularly in the case of the semiconductor memory components with floating gate electrodes as mentioned in the introduction.
The use of a soluble material as the auxiliary layer is particularly preferred. The lateral hollowed-out recesses may be produced in this case by application of a suitable solvent, which may be water, in particular. The additional process step described can be integrated into the customary production process without significant outlay, so that the process step for laterally hollowing out the auxiliary layer can be inserted without any problems after the development and patterning of the photoresist layer to form the photoresist mask.
Examples of the process are described in more detail below with reference to the accompanying figures.
The auxiliary layer 4 is preferably made of a material suitable for antireflection layers in particular BARC WIDE-15 specified in the introduction. According to the invention, it has a thickness of at most 120 nm and particularly when using WIDE-15, preferably has a thickness of 70 nm to 80 nm. For the production of polysilicon electrodes for the application as floating gate electrodes, the polysilicon layer 3 typically has a thickness of 100 nm to 400 nm. The polysilicon electrode is produced in strip-type fashion for this purpose; in
A typical and preferred exemplary embodiment of the production of the auxiliary layer 4 is, when using WIDE-15, a layer thickness of 110 nm, a first hotplate temperature, corresponding to an application of the auxiliary layer as an antireflection layer of 100° C. (for 60 seconds) and a second hotplate temperature of 172° C. to 178° C. (for 60 seconds). The hotplate temperature determines the solubility of the material; the higher the temperature, the lower the solubility. The development time is preferably approximately 60 seconds.
In principle, a wet-chemical etching process, a dry etching process or a thermal process is possible as the etching process. RIE is preferred, during which a chemical attack of the etchant takes place at those locations of the auxiliary layer 4 at which owing to the lateral hollowed-out recesses 6 present, the auxiliary layer 4 only thinly covers the polysilicon layer 3 or no longer covers it at all. Said etching attack suffices to produce the desired edge rounding.
One particular advantage of this process is that only one further process step follows the photolithography and patterning of the resist mask in order to produce the lateral hollowed-out recesses in the auxiliary layer 4, without having to modify the subsequent etching step relative to a standard process. This results in an exact patterning of the polysilicon electrode 8 with the envisaged dimensions designed by the resist mask 5, the desired rounding of the edges additionally being achieved without alteration of the lateral dimensions of the polysilicon electrode 8. A base layer 2, if present as illustrated in the figures, may function as an etching stop layer during the etching of the polysilicon layer 3.
1: Substrate
2: Base layer
3: Polysilicon layer
4: Auxiliary layer
5: Resist mask
6: Lateral hollowed-out recess
7: Rounded edge
8: Polysilicon electrode
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2005 004 596.0 | Feb 2005 | DE | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/EP06/00287 | 1/13/2006 | WO | 00 | 4/22/2008 |
