This application is a national phase entry under 35 U.S.C. §371 of International Patent Application PCT/FR2014/051478, filed Jun. 16, 2014, designating the United States of America and published as International Patent Publication WO 2014/202886 A1 on Dec. 24, 2014, which claims the benefit under Article 8 of the Patent Cooperation Treaty and under 35 U.S.C. §119(e) to French Patent Application Serial No. 1355765, filed Jun. 19, 2013, the disclosure of each of which is hereby incorporated herein in its entirety by this reference.
The disclosure lies in the field of electronics, optics and/or optoelectronics. This disclosure relates more specifically to a process for transferring a buried circuit layer.
Various electronic components are manufactured from a substrate that includes such a buried circuit layer. Among these, mention may be made, by way of example, of the sensors using backside illumination technology (known to a person skilled in the art under the acronym of “BSI sensor” for “backside illumination sensor”). They are based on a novel arrangement of the various layers forming them. These sensors make it possible to increase the amount of light captured and are, therefore, more efficient. They are intended to be used, in particular, in the screens of the latest generation tablets and telephones.
The thinning of a substrate used in the aforementioned technical fields may be carried out, for example, by chemical etching.
When a substrate of semiconductor-on-insulator (SeOI) type is thinned, the chemical etching is relatively easy to use since the buried oxide layer serves as an etch stop layer. When it is a question of a solid substrate, the thinning is slightly more complex since it is then necessary to create an etch stop layer, for example, by p- or n-type doping of the solid substrate.
However, in the particular case where the donor substrate comprises a buried circuit layer, the chemical etching of the layer of material that covers the buried circuit layer becomes truly problematic. Specifically, the chemical solutions used (for example, sulfuric acid (H2SO4), phosphoric acid (H3PO4) or hydrofluoric acid (HF) in the case of the etching of silicon) are particularly aggressive with respect to metals and, therefore, with respect to the layer comprising the circuits.
This results in a lateral etching of the buried circuit layer, which may reach a centimeter or more from the edge. The BSI sensors manufactured in the vicinity of this damaged zone are then unusable.
A process is already known from European Pat. No. EP 1 962 325 (hereinafter the '325 patent) for manufacturing a bonded substrate, by transfer of layers, which comprises steps of producing a peripheral groove on the front side of a donor substrate, of thermal oxidation of this substrate, of bonding a receiver substrate to the front side and of thinning the donor substrate from its back side, until the bottom of the groove is reached.
Such a process makes it possible to transfer to the receiver substrate only the central portion of the donor substrate and to remove the poorly bonded peripheral portion thereof.
However, the '325 patent absolutely does not describe the treatment of donor substrates comprising a buried circuit layer and, furthermore, such a layer would not withstand the thermal oxidation carried out, or the thermal treatment after bonding at more than 1000° C., which are described in the '325 patent.
The objective of the disclosure is, therefore, to propose a process for transferring a buried circuit layer that resolves the aforementioned drawbacks of the prior art and, in particular, that avoids damaging these circuits.
For this purpose, the disclosure relates to a process for transferring a buried circuit layer (2).
In accordance with the disclosure, this process comprises the following steps:
According to other advantageous and nonlimiting features of the disclosure, taken alone or in combination:
Other features and advantages of the disclosure will appear from the description that will now be given, with reference to the accoumpanying drawings, which represent, by way of indication but nonlimitingly, possible embodiments thereof.
In these drawings:
A first embodiment of the disclosure will now be described with reference to
In
The front side 12 is covered with a circuit layer 2.
Moreover, this donor substrate 1 has an internal etch stop zone.
According to a first embodiment of the disclosure, this etch stop zone is a layer 7 of material referred to as a “first stop layer.”
The first stop layer 7 thus divides the donor substrate 1 between a portion 102, referred to as a “front” portion, which extends between this first stop layer 7 and the circuit layer 2 and a portion 101, referred to as a “back” portion, which extends between this first stop layer 7 and the back side 11.
In the example represented, these front 102 and back 101 portions are monolayers. However, front portion 102 and back portion 101 could also be multilayers.
The first stop layer 7 is produced from a material that is selective with respect to the material(s) forming the donor substrate 1 and, in particular, to its back portion 101.
This first stop layer 7 may be obtained by deposition, for example, by chemical vapor deposition (CVD), or by epitaxy on the back portion 101. It may also be obtained by layer transfer.
The front portion 102 may be obtained after the formation of the first stop layer 7 by the same techniques as those mentioned above for the first stop layer 7.
According to another embodiment variant, the first stop layer 7 may also be implanted in the donor substrate 1 by doping. This technique makes it possible to avoid the step of adding the front portion 102 mentioned above.
By way of purely illustrative example, the donor substrate 1 may be of “semiconductor-on-insulator” (SeOI) or “silicon-on-insulator” (SOI) type. In this case, the first stop layer 7 consists of silicon oxide (SiO2).
According to a second embodiment of the disclosure, the etch stop zone may be simply an interface between two layers of the donor substrate. This embodiment variant is represented in
Preferably, the front layer 102′ is a layer of the same chemical nature as the layer 101′, but highly doped.
It will be noted that irrespective of the embodiment of the etch stop zone 7, 7′, this is always produced before the formation of the circuit layer 2.
The next step of the process is represented in
The trench 3 is produced over a depth such that it passes entirely through the circuit layer 2 and such that it extends into the donor substrate 1 to a depth that will be described in detail subsequently in connection with
Preferably, the peripheral trench 3 is produced with the aid of a technique selected from laser etching, dry etching and wet etching. With the first two techniques, it is not necessary to protect the circuit layer 2; on the other hand, with wet etching, it is necessary to add an etching mask on top of the circuit layer 2 in order to etch only the desired portion.
By way of example, the trench 3 advantageously has a width L1 of between 10 μm and 500 μm. Furthermore, the peripheral trench 3 is preferably located at a distance D1 from the lateral edge 13 of the donor substrate 1 of less than or equal to 5 mm. Such a distance makes it possible to maximize the retained central portion of the circuit layer 2, since it is this that will be subsequently used for the fabrication of electronic components.
The exposed side 21 of the circuit layer 2, that is to say its front side, and also the side and bottom internal walls of the trench 3, are then covered with a layer 4 of an etch stop material, which is selective with respect to the etching of the circuit layer 2 and is referred to as a “second stop layer.”
This step takes place by deposition, preferably by a technique selected from chemical vapor deposition (CVD) or spin coating. Spin coating consists in depositing a viscous material over the central portion of the substrate and in spinning the substrate about a central axis.
The step of forming the second stop layer 4, illustrated in
The materials forming the first stop layer 7 and the second stop layer 4 are preferably selected from oxides or nitrides, more preferably selected from silicon oxide (SiO2), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy) or silicon nitride (Si3N4).
Silicon oxide may, for example, be deposited using tetraethyl orthosilicate (TEOS) in an oxygen or oxygen-argon plasma.
Advantageously, but not necessarily, the materials forming the first stop layer 7 and the second stop layer 4 are identical.
The peripheral ring of materials that extends radially beyond the trench 3 bears the reference 14.
As represented in
This bonding preferably takes place by molecular adhesion. It will be noted that the receiver substrate 5 may optionally be covered with a bonding layer 50, for example, a layer of silicon oxide (SiO2) or a layer of silicon nitride (Si3N4).
As can be seen in
This step also has the effect of removing the peripheral ring 14 of the donor substrate 1, not bonded to the receiver substrate 5, either directly, or after an additional mechanical thinning step, as will be described subsequently in greater detail.
The circuit layer 2 buried beneath the front portion 102, transferred to the receiver substrate 5, is thus obtained. The final substrate thus obtained bears the reference 6 (see
The presence of the first stop layer 7 and of the second stop layer 4 on the exposed side 21 and the lateral edge of the circuit layer 2 guarantees that the circuits are not damaged during the chemical etching thinning phase and prevents infiltrations.
In the case where the stop zone is a silicon oxide stop layer 7 and where the material of the back portion 101 is silicon, the chemical etching thinning will advantageously be carried out using a bath of tetramethylammonium hydroxide (TMAH) or KOH (potassium hydroxide).
In the case where the stop zone is a stop interface 7′, and where the back layer 101′ is silicon and the front layer 102′ is highly doped silicon, the chemical etching thinning may be carried out using a solution of sulfuric acid (H2SO4), a solution of phosphoric acid (H3PO4), hydrofluoric acid (HF) or propanoic acid (C2H5COOH).
The transfer process represented in
In this case, the donor substrate, referenced 1′, is subjected to a peripheral routing. The routed portion bears the reference 3′.
This routing is carried out over the entire circumference of the donor substrate 1′ and to a depth such that it passes entirely through the circuit layer 2 and extends into the donor substrate 1′.
This routing may be carried out by polishing or grinding, for example, using a tool applied to a portion of the lateral edge 13 of the donor substrate 1′.
The second stop layer 4 is, therefore, deposited both on the exposed side 21 of the circuit layer 2 and on the routed lateral side 13′ of the donor substrate 1′.
After bonding to the receiver substrate 5 (see
The final substrate referenced 6′ is obtained, which differs from the substrate 6 from
Although the option of peripheral annular routing has been described solely in connection with
Conversely, the donor substrate 1′ from
In the various embodiments described above, the thicknesses of the first stop layer 7 and of the second stop layer 4 preferably lie between 0.01 μm and 100 μm.
The parameter regarding the depth of the peripheral trench 3 in the donor substrate 1′ will now be described in connection with
In
In the variant represented in
In both scenarios, after the step of chemical thinning of the back portion 101, and as can be seen respectively in
In the embodiment variant represented in
In this case, the chemical etching is sufficient to remove the peripheral ring 14. Indeed, the residual thickness 40 of the second stop layer 4 is too small and, therefore, too fragile to retain the peripheral ring 14. This variant is, therefore, the preferential embodiment variant of the disclosure (see
Finally, according to a fourth embodiment variant of the disclosure, the peripheral trench 3 has a depth such that, not only does it pass through the etch stop layer 7, but it extends into the back portion 101 (see
In this case, and as represented in
Owing to the features of the disclosure, the circuit layer 2 is protected during its transfer and the layer 102′ or the front portion 102 that covers it may be adjusted to the desired thickness by choosing the position of the stop layer 7.
Number | Date | Country | Kind |
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13 55765 | Jun 2013 | FR | national |
Filing Document | Filing Date | Country | Kind |
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PCT/FR2014/051478 | 6/16/2014 | WO | 00 |
Publishing Document | Publishing Date | Country | Kind |
---|---|---|---|
WO2014/202886 | 12/24/2014 | WO | A |
Number | Name | Date | Kind |
---|---|---|---|
5071792 | VanVonno et al. | Dec 1991 | A |
5897333 | Goossen | Apr 1999 | A |
20030181001 | Aga | Sep 2003 | A1 |
20050074954 | Yamanaka | Apr 2005 | A1 |
20050266657 | Moriwaki | Dec 2005 | A1 |
20070020873 | Yeh et al. | Jan 2007 | A1 |
20070148912 | Morita | Jun 2007 | A1 |
20090203167 | Mitani | Aug 2009 | A1 |
20110097874 | Broekaart | Apr 2011 | A1 |
20110117691 | Broekaart | May 2011 | A1 |
20110189834 | Castex | Aug 2011 | A1 |
Number | Date | Country |
---|---|---|
1962325 | Aug 2008 | EP |
2011082857 | Jul 2011 | WO |
Entry |
---|
French Search Report for French Application No. FR1355765 dated Mar. 4, 2014, 2 pages. |
International Search Report for International Application No. PCT/FR2014/051478 dated Oct. 20, 2014, 2 pages. |
Number | Date | Country | |
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20160148971 A1 | May 2016 | US |