Patent Application
20150093893
The present invention relates to a process of forming a seed layer, and more particularly to a process of forming a seed layer in a vertical trench/via.
Conventionally, multi-level interconnection is formed in an integrated circuit by dry-etching a metal layer, e.g. aluminum layer, into a desired metal conductor pattern and then performing dielectric gap filling. The conventional process, however, would encounter problems when the metal material is changed from aluminum to copper that has a lower resistivity and is difficult to be dry etched. Therefore, a copper damascene process becomes popular for forming the multi-level interconnection. As is known to those skilled in the art, a copper damascene process is advantageous as not involving any etching procedure of metal layer. Instead, a trench or via is first formed in a dielectric layer, followed by filling the trench or via with a metal conductor and performing a planarization process.
For filling the metal conductor into the trench or via, a seed layer of the metal conductor needs to be formed in the trench or via first. Subsequently, an electroplating process is performed with the seed layer. Unfortunately, copper aggregation likely occurs while forming the seed layer in the copper damascene process, which might narrow or seal the opening of the trench or via. The gap filling capability would thus be deteriorated.
Therefore, the present invention provides a process of forming a seed layer, which is applicable to the copper damascene process and capable of solving the aggregation problem.
In an embodiment, the present invention provides a process of forming a seed layer, which includes providing a semiconductor substrate having a dielectric structure and a hard mask structure thereon, an opening being formed in the hard mask structure, a trench or via being formed in the dielectric structure in communication with the opening, and an area of the opening being greater than that of an entrance of the trench or via; depositing a seed layer in the trench or via through the opening; and reflowing the seed layer.
For example, the reflowing step may be implemented with thermal reflow. The seed layer may be deposited by way of physical vapor deposition (PVD) or chemical vapor deposition (CVD). The process according to the present invention may optionally include a redeposition step of the seed layer by way of PVD and CVD after the thermal reflow.
In an embodiment, the opening can be formed in the hard mask structure by: partially removing the SiON layer, the Ti layer and the TiN layer to form a trench-defining opening; and performing a pull back procedure to partially remove the TiN layer and the Ti layer of the hard mask structure in the trench-defining opening after completing the formation of the trench or via, thereby forming the opening having the area greater than that of the entrance of the trench or via and rendering a rounded corner of the TiN layer while retaining a sharp corner of the SiON layer in the opening.
For example, the pull back procedure is performed with an EKC™ 580 CuSolve™ Post-Etch Residue Remover produced by DuPont™, which has an etch rate of about 10˜250 Å/min for the TiN layer/Ti layer and an etch rate less than 1 Å/min for the SiON layer.
Preferably, the process according to the present invention further includes forming a barrier layer of tantalum (Ta) or tantalum nitride (TaN) in the trench or via before depositing the seed layer in the trench or via.
Other objectives, features and advantages of the present invention will be further understood from the further technological features disclosed by the embodiments of the present invention wherein there are shown and described preferred embodiments of this invention, simply by way of illustration of modes best suited to carry out the invention.
These and other features and advantages of the various embodiments disclosed herein will be better understood with respect to the following description and drawings, in which like numbers refer to like parts throughout, and in which:
It is to be understood that other embodiment may be utilized and structural changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
Please refer to
Now refer to
In the subsequent procedure as illustrated in
After the pull back process is completed, a barrier layer 15 and a seed layer 16 are formed in the trench 14 through the enlarged opening 130, as shown in
Subsequently, in the procedure step as illustrated in
Afterwards, a redeposition process step can be optionally performed on the seed layer 16 for repairing the loss of the seed layer 16 from the side wall of the trench 14 in the thermal reflow process. For example, the reposition process is another PVD or CVD process using Cu, Ru or the mixture. The resulting seed layer 16 preferably has a vertical-like profile angle of 90 degrees plus/minus 5 degrees, and a thickness range of 150-600 angstroms.
The seed layer 16 is then used in an electroplating process or an electroless plating process to conduct the filling of a copper conductor 19 in the trench 14. Subsequently, a planarization process is performed to remove the hard mask structure 13 and a part of the copper conductor 19 so as to form the multi-level interconnection structure as shown in
The above description is given by way of example, and not limitation. Given the above disclosure, one skilled in the art could devise variations that are within the scope and spirit of the invention disclosed herein, including configurations ways of the recessed portions and materials or designs of the attaching structures. Further, the various features of the embodiments disclosed herein can be used alone, or in varying combinations with each other and are not intended to be limited to the specific combination described herein. Thus, the scope of the claims is not to be limited by the illustrated embodiments.
