Claims
- 1. A process of operating a microprocessor comprising:A. setting a first number, defining a number of wait states, in a first register by loading data signals representing the first number into the first register from a data bus that extends to an external address space; B. setting a second number, defining a number of wait states, in a second register by loading data signals representing the second number into the second register from the data bus; C. using the first number in the first register to insert that first number of wait states between addressing a first segment of the external address space and receiving data from the first segment of external address space; and D. using the second number in the second register to insert that second number of wait states between addressing a second segment of the external address space and receiving data from the second segment of external address space.
- 2. The process of claim 1 in which the setting a first number includes setting a first number to be a binary number of from zero through fifteen and the setting a second number includes setting a second number to be a binary number of from zero through fifteen.
- 3. The process of claim 1 in which the setting a first number includes setting a first number to be a binary number of four bits and the setting a second number includes setting a second number to be a binary number of four bits.
CROSS REFERENCE TO RELATED APPLICATIONS
This patent is related to co-assigned U.S. Pat. Nos. 5,586,275; 5,072,418; 5,142,677; 5,155,812; 5,829,054; and 5,724,248, all filed contemporaneously herewith and incorporated herein by reference.
This application is a divisional of application Ser. No. 09/360,488, filed Jul. 23, 1999, now pending; which is a divisional of application Ser. No. 08/906,863, filed Aug. 6, 1997, now U.S. Pat. No. 5,946,483; which is a divisional of application Ser. No. 08/293,259, filed Aug. 19, 1994, now U.S. Pat. No. 5,907,714; which is a continuation of application Ser. No. 07/967,942, filed Oct. 28, 1992, now abandoned; which is a continuation of application Ser. No. 07/347,967, filed May 4, 1989, now abandoned.
US Referenced Citations (26)
Non-Patent Literature Citations (5)
Entry |
Second Generation TMS320 User's Guide ; p. 3-6.* |
“DSP56000 Digital Signal Processor's User's Manual”, Motorola, 1986, pp. 2-12-18, 3-2, 7-1-3. |
“DSP96001”, Motorola, 1988, pp. 1, 2, 6, 9, 10. |
Second-Generation TMS320 User's Guide, Texas Instruments, pp. 6-10-26,Dec. 1987. |
First-Generation TMS320 User's Guide, Texas Instruments, pp. 3-9, A-1-20, 6-2-5, Apr. 1988. |
Continuations (2)
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Number |
Date |
Country |
Parent |
07/967942 |
Oct 1992 |
US |
Child |
08/293259 |
|
US |
Parent |
07/347967 |
May 1989 |
US |
Child |
07/967942 |
|
US |