Claims
- 1. In a process for manufacturing deep trench memory cells in a substrate covered by a pad nitride layer with a top surface and a bottom surface, and having a layer of oxide covering the top surface of said pad nitride layer, and a gate poly filling said trench to a level below the bottom surface of said paid nitride layer, said process further comprising the steps of:
forming a nitride layer over said layer of oxide and the said walls of said trench down to the top surface of said gate poly; etching said nitride layer to form a nitride spacer having a top shoulder proximate the top surface of said pad nitride layer and extending to the top surface of said gate poly thereby defining an aperture surrounded by said nitride spacer;
filing said aperture with a poly stud extending from said gate poly to a level above the top shoulder of said nitride spacer; and forming a nitride liner over said pad nitride layer and said poly stud.
- 2. The process of claim 1 wherein said top shoulder of said nitride spacer is etched to less than 40 nm below the top surface of said pad nitride layer.
- 3. The process of claim 2 wherein said poly stud extends to a level above the top surface of said pad nitride layer.
- 4. The process of claim 1 wherein said poly stud is integrated with said gate poly.
- 5. The process of claim 1 wherein said step of filing said aperture with a poly stud comprises the steps of over filing said aperture with poly and then planarizing said poly back to an oxide layer by CMP (chemical mechanical polishing).
- 6. The process of claim 1 and further comprising the step of wet etching after said filing step and prior to said step of forming a nitride liner.
- 7. The process of claim 1 wherein said nitride liner is between about 10 nm and 15 nm.
Parent Case Info
[0001] This patent claims the benefit of U.S. Provisional Patent Application Serial No. 60/325,915, filed on Sep. 28, 2001.
Provisional Applications (1)
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Number |
Date |
Country |
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60325915 |
Sep 2001 |
US |