This application contains subject matter that is related to the subject matter of the following co-pending applications, each of which is assigned to the same assignee as this application, International Business Machines Corporation of Armonk, N.Y. Each of the below listed applications is hereby incorporated herein by reference in its entirety: Early Directory Access of a Double Rate Elastic Interface, U.S. Ser. No. 11/426,675; Late Data Launch for a Double Data Rate Elastic Interface, U.S. Ser. No. 11/426,671; Mechanism for Windaging of a Double Rate Driver, U.S. Ser. No. 11/426,648, Double Rate Chaining for Synchronous DDR Interfaces, U.S. Ser. No 11/426,651.
This invention relates to synchronous interfaces in computer and other digital electronic systems that use multiple integrated circuits, and particularly relates to programmable cycle delays at the driver circuits to alleviate the synchronization requirement of signals from different driver circuits at one or more receiver circuits.
In digital data systems in general, and in computer systems in particular, there is an ever-increasing drive for larger bandwidth and higher performance. These systems are comprised of discreet integrated circuit chips that arc interconnected. Data moves through a chip and between chips in response to clock pulses, which are intended to maintain synchronization of the data in parallel paths. At the extremely high data rates in today's systems, variations in the propagation of data over a bus along one path as compared to another path on the bus (i.e. skew) can exceed one clock cycle. U.S. Pat. No. 6,334,163, which is assigned to the assignee of this application and is incorporated herein by reference, discloses a so called Elastic Interface (EI) that can compensate for bus skew greater than one clock cycle without a performance penalty. However, packaging technology has not been able scale up to match the performance and bandwidth of the chip and interface technologies. In order to reduce the number I/O terminals on a chip and the number of conductive paths in a bus between chips, the prior art transfers data at a so called Double Data Rate (DDR), in which data is launched onto the bus at both the rising and falling edges of the clock. This allows the same amount of data to be transferred (i.e. bandwidth) with only half the number of bus conductors and half the number of I/O ports, as compared with a system where data is transferred only on a rising or a falling edge. The higher frequency employed in a Double Data Rate bus requires a finer granularity in capturing data at the receiver end of the bus. This requires an increase in the number of latches in an elastic interface in order to maintain the same elasticity interval as compared with a bus operating at a lower frequency. For example, if there were four clock cycles of elasticity at a data transfer rate of x, going to a double data rate mode of data transfer doubles the number of receiver latches that may be required to maintain the same elasticity. This decreases the time duration of valid data being kept by the receiving logic, thus forcing the receiver to have more logic and storage circuits to yield the same valid data time. The receiver logic and storage circuits are especially important and become complicated when the packaging cannot force wire to de-skew arriving data among chip interfaces and all data is required to arrive at the receiving end on the same logical cycle.
It is also common and necessary to partition and transfer instructions and data signals across multiple integrated circuit chips. One of the requirements is that the signals at the receiving ends of one or multiple chips must be synchronized in the same cycle. Even though the driver chips send signals in the same cycle, the signals arrive at the receiver chip(s) not necessarily in the same cycle due to delay differences of the transmission lines of high-speed interfaces. To meet this receiver synchronization requirement, the receiver chip utilizes complicated logic and/or circuit techniques to resynchronize the signals back to the same cycle to compensate the delay differences. Due to the high computer clock frequency and data transfer rate, the signal delay differences from different driver chips are multiple cycles at the receiver chip(s). The multi-cycle delay differences can often be beyond the limit that the receiver chip(s) being able to compensate.
One object of the invention is the provision of a double data rate elastic interface that simplifies the implementation of the interface.
An object of this invention is the provision of a double data rate elastic interface in which the number of latch stages required for the elastic receiver is reduced.
Briefly, this invention contemplates the provision of a double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface. However, the invention is not limited to the driver side/chip, it can be implemented in the receiver side/chip as well. However, since the receiver side of an elastic interface already has complicated logic, the invention will be usually implemented on the driving side. The programmable latch stages on the driving chip side of the interface, can often operate at the local clock frequency (the same frequency as the elastic interface bus clock frequency), which in turn is half of the double data rate at which the receiving latch stages operate, thereby decreasing the logic and storage resources in the interface receivers. The programmable latch stages can also be used in the case that the local clock frequency is twice the elastic interface bus clock frequency, but without the slower on-chip data cycle time advantage. Thus, the receiver buffering storage/FIFO logic is only needed for the delay uncertainly due to process, voltage, temperature etc. (elasticity requirements) within a logical bus while the driver chip bus interface logic compensates for the delay differences among chips using the programmable latch stages. This invention also allows the flexibility to align signals to the required cycle boundaries but not necessarily the same cycle.
The subject matter, which is regarded as the invention, is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
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The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof. As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.
Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.
The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
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