Patent Application
20250107076
The present disclosure relates to the field of semiconductor technologies and relates to but is not limited to a programmable device, a programmable device array, operation methods therefor, and a memory.
A dynamic random access memory (DRAM) chip generally is provided with redundant memory cells. When a memory cell on the DRAM chip becomes defective, a redundant memory cell may replace the defective memory cell to repair the DRAM. When the DRAM chip is being repaired, a one time programmable (OTP) device, such as an anti-fuse cell, is used. At present, a programmable device includes a select transistor and a programming transistor, taking up a relatively large area.
In addition, with the rapid development of integrated circuit technologies, the size of a chip is increasingly smaller, and thus the distance between programmable devices is shorter. Consequently, in one aspect, a programming transistor and an adjacent transistor are subjected to false breakdown, affecting the effect of anti-fuse cell repair; in another aspect, there is tight coupling between a programmable transistor and a select transistor, affecting the performance of the programmable device.
In view of this, embodiments of the present disclosure provide a programmable device, a programmable device array, operation methods therefor, and a memory.
In a first aspect, an embodiment of the present disclosure provides a programmable device, which includes: a bit line; a select transistor, a first source/drain of the select transistor being electrically connected to the bit line; a select signal line, the select signal line being electrically connected to a gate of the select transistor; a plurality of diodes; a plurality of anti-fuse cells, a first end of each one of the plurality of anti-fuse cells being electrically connected to a second source/drain of the select transistor via a corresponding one of the plurality of diodes; and a plurality of word lines, each one of the plurality of word lines being electrically connected to a second end of a corresponding one of the plurality of anti-fuse cells.
In some embodiments, the plurality of diodes are disposed in a substrate and each one of the plurality of diodes includes a first region disposed adjacent to one of the plurality of anti-fuse cells and a second region disposed adjacent to the first region;
In some embodiments, the programmable device further includes a metal layer;
In some embodiments, the programmable device further includes a plurality of first conductive pillars; each one of the plurality of first conductive pillars being connected to the second region of the diode corresponding to the anti-fuse cell that is not adjacent to the select transistor, and the plurality of first conductive pillars being collectively connected to the metal layer.
In some embodiments, the select transistor and the plurality of anti-fuse cells are disposed in a same active region and spaced apart in sequence along a first direction; the programmable device further includes: a second conductive pillar connected between the first source/drain and the bit line; a first connection structure connected between the gate of the select transistor and the select signal line; and second connection structures, each one of the second connection structures being connected between the second end of one of the plurality of anti-fuse cells and one of the plurality of word lines.
In some embodiments, the select transistor includes a first gate dielectric layer and a first gate conductive layer on a surface of the first gate dielectric layer; the anti-fuse cell includes a second gate dielectric layer and a second gate conductive layer on a surface of the second gate dielectric layer, where a thickness of the second gate dielectric layer is less than a thickness of the first gate dielectric layer.
In some embodiments, the first region and the active region are N-type doped, and the second region and the first source/drain are P-type doped.
In a second aspect, an embodiment of the present disclosure provides a programmable device array, which includes: a plurality of programmable devices according to the first aspect arranged in sequence along a second direction, where the gates of the select transistors arranged in a row along the second direction are connected to each other, and the second ends of the anti-fuse cells arranged in a row along the second direction are connected to each other.
In some embodiments, the gates of the select transistors arranged in a row along the second direction are connected to a same select signal line;
In a third aspect, an embodiment of the present disclosure provides an operation method for a programmable device, which is applied to the programmable device according to the first aspect; the method includes: during a programming operation, setting the bit line corresponding to an anti-fuse cell required to be programmed to a first voltage, applying a second voltage to the select signal line, and applying a third voltage to a word line corresponding to the anti-fuse cell required to be programmed, thus breaking down the anti-fuse cell required to be programmed, and meanwhile, applying the first voltage to other word lines in the programmable device to avoid breakdown of other anti-fuse cells except for the anti-fuse cell required to be programmed, where the anti-fuse cell required to be programmed is any one of the plurality of anti-fuse cells; and during a reading operation, setting the bit line corresponding to an anti-fuse cell required to be read to a first voltage, applying a second voltage to the select signal line, and applying a fourth voltage to a word line corresponding to the anti-fuse cell required to be read, thus reading data in the anti-fuse cell required to be read, and meanwhile, applying the first voltage to other word lines in the programmable device, where the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage; the first voltage is a zero voltage or a grounding voltage; a difference between the third voltage and the first voltage is greater than or equal to a breakdown voltage of the anti-fuse cell required to be programmed; a difference between the second voltage and the first voltage is greater than or equal to a turn-on voltage of the select transistor.
In a fourth aspect, an embodiment of the present disclosure provides an operation method for a programmable device array, which is applied to the programmable device array according to the second aspect; the method includes: during a programming operation, setting a bit line corresponding to an anti-fuse cell required to be programmed to a first voltage, applying a second voltage to a select signal line, and applying a third voltage to a word line corresponding to the anti-fuse cell required to be programmed, thus breaking down the anti-fuse cell required to be programmed, and meanwhile, applying the first voltage to other word lines in the programmable device array and applying a fifth voltage to other bit lines in the programmable device array to avoid breakdown of other anti-fuse cells except for the anti-fuse cell required to be programmed, where the anti-fuse cell required to be programmed is any one of a plurality of anti-fuse cells; and during a reading operation, setting a bit line corresponding to an anti-fuse cell required to be read to a first voltage, applying a second voltage to a select signal line, and applying a fourth voltage to a word line corresponding to the anti-fuse cell required to be read, thus reading data in the anti-fuse cell required to be read, and meanwhile, applying the first voltage to other word lines in the programmable device array, and applying the fourth voltage to other bit lines in the programmable device array, where the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage; the first voltage is a zero voltage or a grounding voltage; a difference between the third voltage and the first voltage is greater than or equal to a breakdown voltage of the anti-fuse cell required to be programmed; a difference between the third voltage and the fifth voltage is less than a breakdown voltage of any one anti-fuse cell in the programmable device array; a difference between the second voltage and the first voltage is greater than or equal to a turn-on voltage of the select transistor.
In a fifth aspect, an embodiment of the present disclosure provides a memory, which includes the programmable device array according to the second aspect.
Embodiments of the present disclosure provide a programmable device, a programmable device array, operation methods therefor, and a memory. The programmable device includes: a bit line; a select transistor, a first source/drain of the select transistor being electrically connected to the bit line; a select signal line, the select signal line being electrically connected to a gate of the select transistor; a plurality of diodes; a plurality of anti-fuse cells, a first end of each one of the plurality of anti-fuse cells being electrically connected to a second source/drain of the select transistor via a corresponding one of the plurality of diodes; and a plurality of word lines, each one of the word line being electrically connected to a second end of a corresponding one of the plurality of anti-fuse cells. As the programmable device in the embodiments of the present disclosure includes one select transistor and a plurality of anti-fuse cells, an area of the programmable device can be reduced, and the coupling effect between the select transistor and the anti-fuse cells can be reduced, thereby improving the performance of the programmable device. In addition, as the programmable device in the embodiments of the present disclosure includes a plurality of diodes corresponding to the plurality of anti-fuse cells, and the anti-fuse cells are connected to the select transistor via the diodes, that is, no doped region (e.g., a lightly doped region) is provided below the anti-fuse cells, false breakdown between adjacent anti-fuse cells can be prevented.
In the drawings (may not necessarily be drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different suffix letters may represent similar components in different examples. The drawings show generally, by way of example without limitation, various embodiments discussed herein.
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be more thoroughly understood and the scope of the present disclosure will be fully conveyed to those skilled in the art.
In the following descriptions, many details are provided for a more thorough understanding of the present disclosure. However, it is apparent to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, to avoid confusion with the present disclosure, some technical features commonly known in the art are not described. That is, not all features of the practical embodiments are described herein, and well-known functions and structures are not described in detail.
In the drawings, the sizes of layers, regions, and elements and relative sizes thereof may be exaggerated for clarity. Identical reference numerals refer to identical elements throughout this specification.
It should be understood that when an element or layer is referred to as being “on”, “adjacent to”, “connected to”, or “coupled to” another element or layer, the element or layer may be directly on, adjacent to, connected to, or coupled to the another element or layer, or there may be an element or layer in between. On the contrary, when an element is referred to as being “directly on”, “directly adjacent to”, “directly connected to”, or “directly coupled to” another element or layer, there is no element or layer in between. It should be understood that, although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, and/or portions, the elements, components, regions, layers, and/or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be denoted as a second element, component, region, layer, or portion without departing from the instructions of the present disclosure. The discussion of a second element, component, region, layer, or portion does not necessarily imply that a first element, component, region, layer, or portion necessarily exists in the present disclosure.
The terms used herein are merely for describing specific embodiments and should not be construed as limiting the present disclosure. When used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the terms “comprise” and/or “include”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups. When used herein, the term “and/or” includes any and all combinations of related listed items.
In the embodiment mentioned above, each anti-fuse cell in the programmable device 100 includes a select transistor and a programming transistor, taking up a relatively large area. In addition, with the rapid development of integrated circuit technologies, the size of a chip is increasingly smaller, and thus the distance between programmable devices is shorter. Consequently, in one aspect, a programming transistor and an adjacent transistor are subjected to false breakdown, affecting the effect of anti-fuse cell repair; in another aspect, there is tight coupling between a programmable transistor and a select transistor, affecting the performance of the programmable device.
In view of this, embodiments of the present disclosure provide a programmable device, a programmable device array, operation methods therefor, and a memory. The programmable device includes: a bit line; a select transistor, a first source/drain of the select transistor being electrically connected to the bit line; a select signal line, the select signal line being electrically connected to a gate of the select transistor; a plurality of diodes; a plurality of anti-fuse cells, a first end of each one of the anti-fuse cells being electrically connected to a second source/drain of the select transistor via a corresponding one of the plurality of diodes; and a plurality of word lines, each one of the word lines being electrically connected to a second end of a corresponding one of the plurality of anti-fuse cells. As the programmable device in the embodiments of the present disclosure includes one select transistor and a plurality of anti-fuse cells, an area of the programmable device can be reduced, and the coupling effect between the select transistor and the anti-fuse cells can be reduced, thereby improving the performance of the programmable device. In addition, as the programmable device in the embodiments of the present disclosure includes a plurality of diodes corresponding to the plurality of anti-fuse cells, and the anti-fuse cells are connected to the select transistor via the diodes, that is, no doped region is provided below the anti-fuse cells, false breakdown between adjacent anti-fuse cells can be prevented.
The embodiments of the present disclosure are described in detail below with reference to the drawings.
Before describing the embodiments of the present disclosure, three directions for describing a three-dimensional structure that may be used in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include X-axis, Y-axis, and Z-axis directions. A base substrate may include a top surface at a front side and a bottom surface at a back side opposite the front side. A direction intersecting (for example, perpendicular to) the top surface and bottom surface of the base substrate is defined as a third direction, without considering the flatness of the top surface and bottom surface. In a direction of the top surface and the bottom surface of the base substrate (namely, a plane where the base substrate is located), two intersecting directions (for example, perpendicular to each other) are defined. For example, a direction in which the select transistor and the anti-fuse cells are arranged may be defined as a first direction, and a direction of the plane of the base substrate can be determined based on the first direction and a second direction. In the embodiments of the present disclosure, the first direction, the second direction, and the third direction may be perpendicular to one another. In other embodiments, the first direction, the second direction, and the third direction may not be perpendicular to one another. In the embodiments of the present disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.
In an embodiment of the present disclosure,
It should be noted that the programmable device 200 in the embodiments of the present disclosure is formed in a substrate 300, and the substrate 300 may be, for example, a semiconductor substrate. The semiconductor substrate may be a silicon substrate, and the semiconductor substrate may further include other semiconductor elements such as germanium (Ge); or include semiconductor compounds such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb); or include other semiconductor alloys such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP), or a combination thereof.
In some embodiments, a plurality of active regions 31 are formed in the substrate 300, and the plurality of active regions 31 are isolated from each other by using a shallow trench isolation (STI) structure 30. The active region 31 may be an ion-doped region, and for example, may be an N-type doped region or a P-type doped region.
In the embodiment of the present disclosure, the select transistor is disposed on the active region 31, and the select transistor includes a gate 44, a first source/drain 45, and a second source/drain 47. The first source/drain 45 and the second source/drain 47 are formed by an ion-doped region in the active region 31.
In the embodiment of the present disclosure, the select transistor may be a PMOS transistor. In other embodiments, the select transistor may be an NMOS transistor.
In some embodiments, with further reference to
In some embodiments, with further reference to
It should be noted that the first region 321 is located in the active region 31 below the anti-fuse cell. That is, the first region 321 is a part of the active region 31, and therefore, a doping type of the first region 321 is the same as a doping type of the active region 31. In the embodiment of the present disclosure, the first region 321 and the active region 31 are N-type doped, and the second region 322 and the first source/drain 45 are P-type doped. In this case, the first source/drain 45 is also P-type doped, and the select transistor is a PMOS transistor.
In other embodiments, the first region 321 and the active region 31 may also be both P-type doped. When the first region 321 is P-type doped, the second region 322 is N-type doped, and the second source/drain 47 and the first source/drain 45 are also N-type doped. In this case, the select transistor is an NMOS transistor.
In some embodiments, with further reference to
It should be noted that the first end of the anti-fuse cell is an end that is connected to the second gate dielectric layer 331, and the second end of the anti-fuse cell is an end that is connected to the second gate conductive layer 332.
In some embodiments, a thickness of the second gate dielectric layer 331 is less than a thickness of the first gate dielectric layer 441. As the second gate dielectric layer 331 needs to be broken down at a high voltage during a programming operation, allowing the thickness of the second gate dielectric layer 331 to be less than that of the first gate dielectric layer 441 can not only reduce the energy for breaking down the anti-fuse cell, but also can prevent the select transistor corresponding to the anti-fuse cell from being broken down and thereby prevent the failure of the select transistor resulting therefrom.
In the embodiment of the present disclosure, the first end of the anti-fuse cell is electrically connected to the second source/drain 47 of the select transistor via a corresponding diode 32. When the first end of the anti-fuse cell is at a high voltage, the diode is cut off, and when the second source/drain 47 is at a high voltage, the diode is conductive. That is, a current can flow to the second end of the anti-fuse cell from the second source/drain 47, but cannot flow to the second source/drain 47 from the second end of the anti-fuse cell.
In the embodiment of the present disclosure, the anti-fuse cell is connected to the second source/drain 47 of the select transistor via the diode 32. That is, no lightly doped region is provided below the anti-fuse cell, so that after the second gate dielectric layer 331 of the anti-fuse cell is broken down, a high transient current resulting from the breakdown enters the first region 321 below. In addition, as the current does not flow to the second source/drain from the second end of the anti-fuse cell, the high transient current cannot flow into the second regions 322. That is, after the second gate dielectric layer 331 of the anti-fuse cell is broken down, the diode 32 is cut off, so that false breakdown between adjacent anti-fuse cells can be prevented.
In the embodiment of the present disclosure, with further reference to
As the programmable device in the embodiments of the present disclosure includes one select transistor and a plurality of anti-fuse cells, an area of the programmable device can be reduced, and the coupling effect between the select transistor and the anti-fuse cells can be reduced, thereby improving the performance of the programmable device.
It should be noted that the second region 322 of one of the plurality of diodes 32 corresponding to one of the plurality of anti-fuse cells disposed adjacent to the select transistor occupies a same position as the second source/drain 47. In this way, an area of the anti-fuse structure can be further reduced, and miniaturization can be achieved.
In some embodiments, with further reference to
In some embodiments, with further reference to
In the embodiment of the present disclosure, materials of the bit line 48, the word line 36, and the select signal line 40 are any one material with good conductivity, for example, any one of or a combination of two or more of titanium, titanium nitride, tungsten nitride, tungsten, cobalt, platinum, palladium, ruthenium, and copper.
In some embodiments, with further reference to
In some embodiments, with further reference to
In the embodiment of the present disclosure, the metal layer 39 can allow the second end of the anti-fuse cell that is not adjacent to the select transistor to be connected to the second source/drain 47 of the select transistor. In this way, only one select transistor is needed for controlling a plurality of anti-fuse cells, so that an area of the programmable device 200 can be reduced in the presence of a same quantity of anti-fuses, or a quantity of anti-fuse cells can be increased while with the area remained the same, thereby improving the integration of the programmable device 200.
In some embodiments, with further reference to
It should be noted that the metal layer 39 is located on an upper layer of the first conductive pillars 38, and the first conductive pillars 38 and the second conductive pillar 42 are located on a same layer. Materials of the metal layer 39, the first conductive pillar 38, and the second conductive pillar 42 may be any one of or a combination of two or more of tungsten, cobalt, platinum, palladium, ruthenium, and copper.
The first connection structure 43 and the second connection structure 37 are located on a same layer and are respectively located above the first gate conductive layer 442 and the second gate conductive layer 332. The first connection structure 43 is configured to reduce a contact resistance between the gate 44 of the select transistor and the select signal line 40, and the second connection structure 37 is configured to reduce a contact resistance between the second end of the anti-fuse cell and the word line 36, thereby reducing a voltage drop on the select signal line 40 and the word line 36 and reducing power consumption.
In some embodiments, with further reference to
In some embodiments, with further reference to
In some embodiments, with further reference to
In other embodiments, the second sidewall layer 35 may not be disposed in the anti-fuse cell.
It should be noted that the gate of the select transistor and the anti-fuse cells are disposed in a dielectric layer 34 on a surface of the active region. A material of the dielectric layer 34 may be, for example, silicon dioxide.
It should be noted that it is shown in
In another embodiment of the present disclosure, an operation method for the programmable device 200 is further provided and is applied to the programmable device 200 shown in
In the embodiment of the present disclosure, when the anti-fuse cell required to be programmed is programmed, the first voltage is a zero voltage or a grounding voltage, and a difference between the second voltage and the first voltage is greater than or equal to a turn-on voltage of the select transistor, so that the select transistor can be turned on at the second voltage. For example, the second voltage may be 1.1 V to 3 V. The difference between the third voltage and the first voltage is greater than or equal to the breakdown voltage of the anti-fuse cell required to be programmed, and is less than the breakdown voltage of the select transistor, so that at the third voltage, the anti-fuse cell required to be broken down can be broken down while the select transistor is not broken down. Here, the third voltage may range from 4 V to 5.5 V, for example, 4.3 V, 4.8 V, or 5.4 V. When the anti-fuse cell required to be read is read, the fourth voltage is used to provide a current for reading, and the fourth voltage may be, for example, the power supply voltage Vdd.
A specific operation process of the programmable device is described below by taking an anti-fuse cell C0 in the programmable device in
During programming, a first voltage of 0 V is applied to a bit line BL, a second voltage of 1.1 V to 3 V is applied to a gate, X gate, of the select transistor to turn on the select transistor, and a third voltage of 4 V to 5.5 V is applied to a word line WL3 corresponding to the anti-fuse cell C0. In this case, a voltage difference between two ends of the anti-fuse cell C0 is 4 V to 5.5 V, so that a second gate dielectric layer of the anti-fuse cell C0 can be broken down, and the programming process is implemented. At the same time, the first voltage is applied to other word lines except for the word line WL3 in the programmable device, so that other anti-fuse cells are not broken down.
During reading, the first voltage of 0 V is applied to the bit line BL, the second voltage of 1.1 V to 3 V is applied to the gate, X gate, of the select transistor to turn on the select transistor, and the power supply voltage Vdd, which serves as the third voltage, is applied to the word line WL3 corresponding to the anti-fuse cell C0. In this case, a relatively large current flows through the bit line BL, and the reading process is implemented. At the same time, the first voltage is applied to other word lines except for the word line WL3 in the programmable device, so that no current flows through the other anti-fuse cells.
It should be noted that, in the embodiment of the present disclosure, there is no other doped region, that is, no LDD, in the first region 321 below an anti-fuse cell adjacent to the anti-fuse cell C0. The diode below the anti-fuse cell C0 includes a reverse PN junction and is cut off, so that a high transient current generated after the anti-fuse cell C0 is broken down cannot flow to the second region 322 through the first region 321. Therefore, even if the anti-fuse cell adjacent to the anti-fuse cell C0 is also broken down, the process of reading the anti-fuse cell C0 does not affect the adjacent anti-fuse cell.
In another embodiment of the present disclosure,
In some embodiments, with further reference to
In the embodiment of the present disclosure, the gates 44 of the select transistors arranged in a row along the second direction are connected to each other and connected to the same select signal line 40, so that the plurality of select transistors in a same row can be turned on or off through one control end. The second ends of the anti-fuse cells arranged in a row along the second direction are connected to each other and connected to the same word line 36, so that a programming voltage or a reading voltage can be applied to the plurality of anti-fuse cells in a same row at the same time. In this way, the wiring design of the programmable device array can be simplified, and the manufacturing costs can be reduced.
In some embodiments, sizes, in the X-axis direction, of the second gate dielectric layers 331 of the plurality of anti-fuse cells arranged along the X-axis direction and the Y-axis direction may be equal. In this way, it can be avoided that a voltage difference is too large to break down one row of anti-fuse cells via a same word line 36 when different anti-fuse cells are to be broken down.
In other embodiments, the sizes, in the X-axis direction, of the second gate dielectric layers 331 of the plurality of anti-fuse cells arranged along the X-axis direction and the Y-axis direction may not be equal.
The programmable device 200 in the programmable device array 400 according to this embodiment of the present disclosure has a structure similar to that of the programmable device 200 according to the embodiments described above. For technical features that are not disclosed in detail in this embodiment of the present disclosure, reference can be made to the embodiments described above for understanding and details are not described here again.
The programmable device array provided in this embodiment of the present disclosure includes a plurality of programmable devices, and the programmable device array takes up a relatively small area because the programmable devices each take up a small area.
It should be noted that only four columns of programmable devices 200 are shown in the programmable device array 400 in
In another embodiment of the present disclosure, an operation method for the programmable device array 400 is further provided and is applied to the programmable device array 400 shown in
In the embodiment of the present disclosure, when the anti-fuse cell required to be programmed is programmed, the first voltage is a zero voltage or a grounding voltage, and a difference between the second voltage and the first voltage is greater than or equal to a turn-on voltage of the select transistor, so that the select transistor can be turned on at the second voltage. For example, the second voltage may be 1.1 V to 3 V. The difference between the third voltage and the first voltage is greater than or equal to the breakdown voltage of the anti-fuse cell required to be programmed and is less than the breakdown voltage of the select transistor, so that at the third voltage, the anti-fuse cell required to be broken down can be broken down while the select transistor is not broken down. Here, the third voltage may range from 4 V to 5.5 V, for example, 4.3 V, 4.8 V, or 5.4 V. In this case, to avoid false breakdown of the other anti-fuse cells adjacent to the anti-fuse cell required to be programmed, the bit lines 48 of the other anti-fuse cells adjacent to the anti-fuse cell required to be programmed need to be set to the fifth voltage, the other word lines 36 adjacent to the anti-fuse cell required to be programmed need to be set to the first voltage, and a difference between the fifth voltage and the first voltage is allowed to be less than the breakdown voltage of any one anti-fuse cell in the programmable device array 400. Here, the fifth voltage may be, for example, 2.5 V.
When the anti-fuse cell required to be read is read, the fourth voltage is used to provide a current for reading, and the fourth voltage may be, for example, the power supply voltage Vdd.
A specific operation process of the programmable device array 400 is described below by taking an anti-fuse cell C1 in the programmable device array in
During programming, a first voltage of 0 V is applied to a bit line BL2 corresponding to the anti-fuse cell C1, a second voltage of 1.1 V to 3 V is applied to gates, X gates, of the select transistors to turn on all select transistors, and a third voltage of 4 V to 5.5 V is applied to a word line WL3 corresponding to the anti-fuse cell C1. In this case, a voltage difference between two ends of the anti-fuse cell C1 is 4 V to 5.5 V, so that a second gate dielectric layer of the anti-fuse cell C1 can be broken down, and the programming process is implemented. At the same time, the first voltage is applied to other word lines (for example, a word line WL1, a word line WL2, and a word line WL4) except for the word line WL3 in the programmable device array, and the fifth voltage of 2.5 V is applied to other BLs (for example, a bit line BL1, a bit line BL3, and a bit line BL4) except for the bit line BL2, so that other anti-fuse cells are not broken down.
In the embodiment of the present disclosure, when the anti-fuse cell C1 is programmed, although there are low voltages at the bit line BL2 end in an anti-fuse cell C2 and an anti-fuse cell C4, there is no voltage difference as voltages at the word line WL2 end and the word line WL4 end are low, and therefore the anti-fuse cell C2 and the anti-fuse cell C4 are not falsely broken down. In addition, the first region 321 below the anti-fuse cell C1 is not provided with an LDD and a PN junction is formed here, and a transient current generated after the anti-fuse cell C1 is broken down does not affect the anti-fuse cell C2 and the anti-fuse cell C4. Therefore, when the anti-fuse cell C1 is being broken down, its surrounding anti-fuse cells (fuses) will not be falsely broken down.
During reading, the first voltage of 0 V is applied to the bit line BL2 corresponding to the anti-fuse cell C1, the second voltage of 1.1 V to 3 V is applied to the gate, X gate, of the select transistor to turn on the select transistor, and the power supply voltage Vdd, which serves as the third voltage, is applied to the word line WL3 corresponding to the anti-fuse cell C1. In this case, a relatively large current flows through the bit line BL, and the reading process is implemented. At the same time, the first voltage is applied to other word lines (for example, the word line WL1, the word line WL2, and the word line WL4) except for the word line WL3 in the programmable device array, and the fourth voltage is applied to other bit lines (for example, the bit line BL1, the bit line BL3, and the bit line BL4) except for the bit line BL2 in the programmable device array, so that no current flows through the other anti-fuse cells.
In the embodiment of the present disclosure, when the anti-fuse cell C1 is being read, there is Vdd at the word line WL3 in an anti-fuse cell C5 and an anti-fuse cell C3, but there is also Vdd at the bit line BL1 and the bit line BL3, so that there is no current here. Therefore, when the anti-fuse cell C1 is read after being programmed, its surrounding anti-fuse cells (fuses) are not affected or subjected to electric leakage.
Another embodiment of the present disclosure further provides a memory including the programmable device array 400 (referring to
The programmable device 200 includes: a bit line 48; a select transistor, a first source/drain 45 of the select transistor being electrically connected to the bit line 48; a select signal line 40, the select signal line 40 being electrically connected to a gate 44 of the select transistor; a plurality of diodes 32; a plurality of anti-fuse cells, a first end of the anti-fuse cell being electrically connected to a second source/drain 47 of the select transistor via a corresponding diode 32; and a plurality of word lines 36, the word line 36 being electrically connected to a second end of a corresponding anti- fuse cell.
In some embodiments, the memory described above may include, but is not limited to, a random access memory (RAM), for example, a dynamic random access memory (DRAM).
In the embodiment of the present disclosure, the memory includes the programmable device array 400 described above, and as the programmable device array 400 takes up a relatively small area, the integration of the memory can be improved, and a storage capacity of the memory is effectively enhanced, improving the performance of the memory.
In the embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The structural embodiments described above are merely illustrative. For example, the division into the units is only a logical functional division, and in actual implementation, there may be other division manners. For example, a plurality of units or modules may be combined, or may be integrated into another system; or some features may be ignored or not implemented. In addition, the various components shown or discussed are coupled or directly coupled to each other.
The features disclosed in the method or structural embodiments provided in the present disclosure may be combined in any manner if without conflict to obtain new method or structural embodiments.
The foregoing descriptions are only some embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto. Changes or substitutions that any one skilled in the art can easily think of within the technical scope disclosed by the present disclosure shall all fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be defined by the protection scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311229610.4 | Sep 2023 | CN | national |
This application is a continuation application of International Patent Application No. PCT/CN2024/105196, filed on Jul. 12, 2024, which is based on and claims priority to Chinese Patent Application No. 202311229610.4 filed on Sep. 21, 2023 and entitled “PROGRAMMABLE DEVICE, PROGRAMMABLE DEVICE ARRAY, OPERATION METHODS THEREFOR, AND MEMORY”, which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2024/105196 | Jul 2024 | WO |
| Child | 18948559 | US |
