Claims
- 1. A programmable logic device comprising:
- a plurality of logic elements and connected to each logic element a switch circuit the state of which is controllable to determine connections between the logic elements;
- a storage circuit providing at least one storage location and operatively connected to the switch circuit;
- addressing circuitry operatively connected to a plurality of said storage locations whereby a selected one of said storage locations can be addressed, wherein each storage location can be programmed to hold in mode (a) routing data defining the state of its associated switch circuit or in mode (b) logic data representing the result of a logic function and which is output from a selectively addressed storage location; and
- programming circuitry operable to determine whether the storage circuits implement mode (a) or mode (b).
- 2. A programmable logic device as claimed in claim 1, wherein each logic element comprises a logic gate and each switch circuit comprises a selection circuit for selectively connecting from a set of input signals an input signal to an input of said logic gate.
- 3. A programmable logic device as claimed in claim 2, wherein each logic gate has a plurality of inputs, with a selection circuit associated with each input.
- 4. A programmable logic device as claimed in claim 2 or 3, wherein each logic gate has an output, the outputs of selected logic gates being connected to supply some or all of said set of input signals to the selection circuits of others of said logic gates.
- 5. A programmable logic device as claimed in claim 2, wherein each selection circuit comprises a multiplexer controllable by a data bit stored in said storage location.
- 6. A programmable logic device as claimed in claim 1, wherein each logic element is selectively connectable via said switch circuit to an output line of the device, the logic elements being arranged in sets and each set being selectively connectable to a common output line.
- 7. A programmable logic device as claimed in claim 6, wherein each logic element is a transistor having its gate connected to receive an input signals and its source/drain path selectively connectable to said output line.
Priority Claims (1)
Number |
Date |
Country |
Kind |
9303084 |
Feb 1993 |
GBX |
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Parent Case Info
This is a division of application Ser. No. 08/190,912, filed Feb. 3, 1994.
US Referenced Citations (13)
Foreign Referenced Citations (1)
Number |
Date |
Country |
1125124 |
Aug 1989 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
190912 |
Feb 1994 |
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