Claims
- 1. An apparatus comprising:
a first layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with each other; a second layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with either each other or any of the conductive array lines of the first layer; a plurality of memory plugs located at the intersections of the first layer of conductive array lines and the second layer of conductive array lines, each memory plug being in electrical contact with one of the conductive array lines from the first layer and one of the conductive array lines from the second layer such that each memory plug is associated with a unique pair of conductive array lines; and circuitry in electrical contact with the conductive array lines that provides a reference voltage to the conductive array lines when activated; wherein a single memory plug can be selected by
selecting a unique pair of conductive array lines that is associated with the single memory plug, the unique pair consisting of a first layer conductive array line and a second layer conductive array line; applying a first select voltage to the first layer conductive array line; and applying a second select voltage to the second layer conductive array line.
- 2. The apparatus of claim 1, wherein the reference voltage is applied to unselected conductive array lines.
- 3. The apparatus of claim 2, wherein the reference voltage providing circuitry includes a plurality of transistors, each transistor being capable of bringing a single conductive array line to the reference voltage when turned on.
- 4. The apparatus of claim 3, wherein the reference voltage providing circuitry includes a plurality of pass devices, each pass device being capable of bringing a single conductive array line to the reference voltage when turned on.
- 5. The apparatus of claim 3, wherein the reference voltage is not applied while the unique pair of conductive array lines is being selected.
- 6. The apparatus of claim 5, wherein the reference voltage is applied to all of the conductive array lines.
- 7. The apparatus of claim 3, wherein the reference voltage is applied while the unique pair of conductive array lines is being selected.
- 8. The apparatus of claim 7, wherein
a first layer select signal is used to select the first layer conductive array line; and the first layer select signal is also used to prevent the transistor associated with first layer conductive array line from turning on.
- 9. The apparatus of claim 8, wherein
the inverse of the first layer select signal is used as a gate voltage to the transistor associated with first layer conductive array line.
- 10. The apparatus of claim 1, wherein
the reference voltage is not applied while the unique pair of conductive array lines is being selected; and activation of the reference voltage providing circuitry brings all conductive array lines to the reference voltage.
- 11. The apparatus of claim 1, further comprising:
a plurality of first layer selection circuitry, each first layer selection circuitry:
being in electrical contact with a group of conductive array lines on the first layer; being capable of providing a first select voltage to any first layer conductive array line within the group; and a plurality of second layer selection circuitry, each second layer selection circuitry:
being in electrical contact with a group of conductive array lines on the second layer; being capable of providing a second select voltage to any second layer conductive array line within the group; and wherein
the first layer selection circuitry has integrated the reference voltage providing circuitry such that the first layer selection circuitry can provide either a select voltage to a first layer conductive array line within its associated group of conductive array lines or provide a reference voltage to its associated group of conductive array lines; and the second layer selection circuitry has integrated the reference voltage providing circuitry such that the second layer selection circuitry can provide either a select voltage to a second layer conductive array line within its associated group of conductive array lines or provide a reference voltage to its associated group of conductive array lines.
- 12. The apparatus of claim 11, wherein the reference voltage is, while the unique pair of conductive array lines are being selected, applied to the groups of conductive array lines that are not associated with the unique pair of conductive array lines.
- 13. The apparatus of claim 11, wherein the reference voltage is not applied to the conductive array lines during the selection of the unique pair of conductive array lines.
- 14. The apparatus of claim 1, wherein the reference voltage is ground.
- 15. A method of selecting a single memory plug on a cross point memory array and preventing unselected conductive array lines from floating to an undesired voltage comprising:
selecting a unique pair of conductive array lines associated with the single memory plug, the unique pair consisting of a first layer conductive array line and a second layer conductive array line; applying a first select voltage to the first layer conductive array line; and applying a second select voltage to the second layer conductive array line; and providing a reference voltage to the unselected conductive array lines.
- 16. A method of claim 15, wherein the reference voltage is not applied while the unique pair of conductive array lines is being selected.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Application No. 60/400,849, filed Aug. 02, 2002, the U.S. Provisional Application No. 60/422,922, filed Oct. 31, 2002, and the U.S. Provisional Application 60/424,083, filed Nov. 5, 2002, all of which are incorporated herein by reference in their entireties and for all purposes. This application is related to sister applications entitled “Cross Point Memory Array Using Multiple Thin Films,” “Cross Point Memory Array Using Multiple Modes of Operation,” “Cross Point Memory Array Using Distinct Voltages,” “Cross Point Memory Array With Memory Plugs Exhibiting A Characteristic Hysteresis,” “Multi-Output Multiplexor,” and “Multiplexor Outputting A Reference Voltage On Unselected Lines,” all of which were filed on date even herewith and are hereby incorporated herein by reference in their entireties and for all purposes.
Provisional Applications (3)
|
Number |
Date |
Country |
|
60400849 |
Aug 2002 |
US |
|
60422922 |
Oct 2002 |
US |
|
60424083 |
Nov 2002 |
US |