Patent Application
20080012574
The same elements have been designated with the same reference numerals in the different drawings. For clarity, only those elements and steps which are useful to the understanding of the present invention have been shown and will be described. In particular, what exploitation is made by an integrated circuit of the detection of a noise peak on its power supply has not been detailed, the present invention being compatible with any countermeasure system.
The present invention originates from an interpretation of the operation of the different types of detectors of noise peaks on the power supply of an integrated circuit in terms of amplitude and duration of the peak.
The fact of applying an approximately constant offset between average value Vm and detection threshold Vth as provided by the assemblies of
A difference between the assembly of
As to the assembly of
A first peak P1 is of amplitude A1 and duration T1. A second peak P2 is of amplitude A2 and duration T2. Amplitude A2 is such that it reverses the circuit supply voltage (amplitude cutting minimum voltage level Vmin) and duration T2 is shorter, by a ratio of at least three, than duration T1. A third peak P3 of amplitude A3 and of duration T3 represents a third category of noise peaks, duration T3 being of the same order of magnitude as duration T2 and amplitude A3 being of the same order of magnitude as amplitude A1, not reaching level Vmin.
The three peaks P1, P2, and P3 of
A detector capable of detecting only peak P1 and detecting neither peaks P2 and P3 is considered as belonging to a first category, typically shown in
A detector only detecting a peak P2, of sufficient amplitude to invert the integrated circuit supply voltage or at least go below a minimum operating voltage of a comparator in the technology of this circuit, is considered as belonging to a second category corresponding to the detector of
A detector capable of detecting the three peaks P1, P2, and P3 belongs to a third category, gathering the detectors of
The examination of the detection of a noise peak by a detector is, according to the present invention, performed by checking whether the integrated circuit responds to the occurrence of at least one noise peak. This response is determined by comparison of the consumption or of the average current consumed by the circuit before and after sending of the noise peak by a qualification system. If the circuit has detected the peak, the countermeasure that it implements necessarily causes a modification in the average consumed current, be it a reset internal to the detector or any other countermeasure.
The present inventors have further found that the capacity to detect noise peaks of a detector depends, for the detectors of first and second categories using a comparator in the form of differential amplifiers, on the supply voltage. Indeed, the supply voltage conditions the speed performance (transition frequency) of the integrated circuit switches and in particular the slope of the differential stages that it comprises. This supply voltage thus conditions the speed of the detectors made in the form of amplifiers (first and second categories of
A circuit to be qualified is supplied (block 81, Valim=V1) with a first voltage V1.
A first step (block 82, ATR?) comprises checking whether supply voltage V1 is sufficient for the circuit start up. For this purpose, a control signal or a stimulus to which the circuit to be tested is supposed to respond is sent thereto. For example, the case in point is to check whether the circuit provides on its input/output ports an answer to reset (ATR). The case in point may also be to check the connection of a USB peripheral.
If test 82 is positive (output O of block 82), the system measures and stores (block 83, lb) average current lb of the circuit before disturbance.
Then (block 84), the system sends onto the supply of the circuit to be tested a noise peak P of amplitude A and of duration T. In the example, the sending of a negative noise peak on a positive supply voltage is assumed. The opposite is of course possible and will easily be understood from the following description. Amplitude A is selected so as, under voltage V1, not to reach the minimum voltage level which would be detected as an reversal (for example, A=A1=A3). Duration T is selected so as, under voltage V1, to be detectable by first category detectors (T=T1).
The system then measures (block 85, la) and memorizes average current la after the noise peak, to determine whether the circuit has responded to this peak by means of its possible detector.
Then, the system compares (block 86, la=lb?) the average currents before and after the peak. The time constant of integration of the average current value is selected to be greater than the maximum duration of the peaks to be simulated.
If the circuit does not modify its operation (output N of test 86), this means (flag S1 active) either that the integrated circuit has no noise peak detector, or that it has a second category detector. In the opposite case (output O of test 86), this means (flag S2 active) that the circuit has a detector of the first or third category.
This test is performed again for a second supply voltage V2 smaller than the first one (block 88, Valim=V2<V1). This second test is also performed in case of a negative output of test 82.
Steps 82′, 83′, 84′, 85′, and 86′, similar to steps 82 to 86, are then carried out under supply voltage V2. In the case where the circuit does not start, the qualification test stops (flag S3 active) and the results are interpreted.
If the circuit has started under second voltage V2, the comparison of the average currents before and after a second peak P′ (block 86′) improves the detection of the first execution. For example, peak P′ is selected so as to, under voltage V2, be of a duration insufficient to be detected by the detectors of the first and second categories. It for example respect the gauge (A′=A3, T′=T3) of the third category.
In case of a positive detection (output O) of block 86, this means (flag S5 active) that the detector is of the third category. In case of a negative output of block 86 (flag S4 active), this means that it belongs to the first category.
Assuming levels S1 to S5 to be active at state 1, the results may be interpreted as illustrated by table I hereafter. In this example, a peak P (block 84) selected, under voltage V1, to be of amplitude A=A1=A3 and of duration T=T1, and a peak P′ (block 84′) selected to be, under voltage V2, of amplitude A′=A1 =A3 and of duration T=T3, are assumed. The states shown below must of course need to be adapted if some flags have a quiescent level at state 1.
According to a first alternative embodiment, steps 83 to 86, under voltage V1, are carried out a second time with a peak gauge P2 (A=A2, T=T2) to differentiate the lack of a detector from a second category detector.
According to another variation, the method of
In this variation, an additional execution of steps 83 to 86 with a gauge peak P1 enables removing the uncertainty on the existence of a first category detector.
The present invention enables detecting the presence, in an integrated circuit, of a noise peak detector and, with a decreased number of tests, qualifying this detector according to its sensitivity.
Another advantage of the present invention is that it avoids any reverse engineering intervention within the circuit.
Different variations may be provided to refine the detection or qualify this detection under more than two supply voltages. In the extreme, for each supply voltage, noise peaks respecting the different gauges are successively applied.
According to another alternative embodiment, supply voltages V1 and V2 are inverted, that is, it is started by performing a test under a relatively low voltage, then under a relatively high voltage.
The amplitude and the duration of the noise peaks sent by the test system are preferentially selected according to the breakdown voltage of the transistors forming this circuit.
Technologically, this breakdown voltage is set by the gate oxide thickness of the different MOS transistors of the assembly and by their drain/source resistance.
Noting Mu the electric mobility, Vt the threshold voltage of the transistors, and Lmin the minimum length of the transistor connectable on power supply Valim, transition frequency Ft0 is given by the following relation:
Ft0=Mu.(Valim−Vt)/(2π.Lmin2).
Amplitudes A and A′ and durations T and T′ are for example selected so that:
A=Valim;
A′=Valim−Vt;
T=(Ft0+K)/(Ft0.K); and
T′=(Ft0+K′)/(Ft0.K′)
where K and K′ respectively have values 4.108 Hz and 2.107 Hz and are selected according to the parasitic elements of the detection circuits and on the desired consumption. Such values define the limiting values enabling differentiating the detectors.
As a specific example of embodiment, with Mu=3.1010 μm2/V.s, Valim=5 V, Vt=0.65 V, Lmin=1 μm, a frequency Ft0 of approximately 20 GHz and durations T and T′, respectively, of 2.55 ns and 50 ns are obtained.
According to a specific example of embodiment of the present invention applied to integrated circuits likely to operate under supply voltages V1 of 5.5 volts and V2 of 3.3 volts, the peaks sent by the qualification system have respective durations T of 10 nanoseconds and T′ of 40 ns with respective amplitudes A and A′ of approximately 4 V and 2.3 V.
In the quiescent state, in the absence of waves sent by generator 91, the circuit is powered, transistor 90 being on. The presence of a wave generated by generator 91 causes an abrupt opening of transistor 90, and thus a peak on the power supply of circuit 1. Current detector 95 enables exploiting average measurements of this current before and after the occurrence of noise peaks.
For the case where a gauge peak P2 must be applied by the system, the emitter of transistor 90 is then collected to a terminal (not shown) of application of a negative voltage to which is also connected resistor Rb2 by its terminal opposite to that connected to the base of transistor 90. Terminal 41 of circuit 1 is further connected, as well as resistor Re, to the transistor collector rather than to its emitter.
Of course, various alterations, modifications, and improvements will readily occur to those skilled in the art. In particular, although the present invention has been described in relation with an example of detectors of negative peaks on a positive power supply, it easily transposes to detectors of positive peaks on negative power supplies as well as to detectors of positive, respectively, negative peaks on positive, respectively, negative power supplies. Further, the practical implementation of the present invention based on the functional indications given hereabove is within the abilities of those skilled in the art by using available hardware and/or software tools. In particular, other test circuits than that of
Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.
| Number | Date | Country | Kind |
|---|---|---|---|
| FR06/52713 | Jun 2006 | FR | national |
