Patent Application
20140176116
1. Field of the Invention
Embodiments of the present invention relate generally to integrated circuits and, more specifically, to quantifying silicon degradation in an integrated circuit.
2. Description of the Related Art
In integrated circuits (ICs) and related subsystems, microprocessors and other components can typically be operated across a range of voltages and frequencies. Consequently, a microprocessor or other component of an IC that is operated at a higher frequency (and correspondingly higher voltage) in this range has faster computing performance and higher energy consumption than when operated at a lower frequency (and correspondingly lower voltage). A feature key for saving power and reducing heat generation in ICs is the implementation of dynamic voltage and frequency scaling (DVFS), a combination of dynamic voltage scaling and dynamic frequency scaling. Dynamic voltage scaling is a power management technique in which the voltage used in a component is increased or decreased dynamically, depending upon the usage of the component, and dynamic frequency scaling involves adjusting the frequency of a component dynamically, depending on the usage of the component.
Over the lifetime of an IC, various mechanisms result in the degradation of sub-circuits and other components of the IC, including hot-carrier injection (HCI), negative bias temperature instability (NBTI), and positive bias temperature instability (PBTI) or “charge trapping.” The degradation caused by HCI, NBTI, and PBTI generally reduces the intrinsic speed of an affected sub-circuit and component, thereby altering the voltage-frequency curve that describes the minimum voltage required to operate the IC component at a given frequency. As an IC component degrades from use, a higher minimum voltage is required for running at a particular frequency. Consequently, a “voltage margin” is commonly incorporated into the voltage-frequency curves of an IC device to anticipate such degradation and prevent functional failures in the IC device later in the functional life of the device. Unfortunately, the inclusion of voltage margin in the voltage-frequency curve of an IC device results in wasted power consumption and unnecessarily slow performance for much of the lifetime of the IC device.
Accordingly, there is a need in the art for a technique to reduce voltage margins used in IC devices without increasing the likelihood of functional failures in such devices.
One embodiment of the present invention sets forth a subsystem of an integrated circuit configured to monitor the degradation over time of one or more portions of the integrated circuit. The subsystem includes a first instance and a second instance of an oscillating circuit that are each formed as part of an integrated circuit. The first instance of the oscillating circuit is configured to be coupled to a power source during operation of the semiconductor system. The second instance of the oscillating circuit is configured to be decoupled from the power source during operation of the integrated circuit and coupled to the power source during a testing operation.
One advantage of the afore-described embodiment is that accurate measurement of semiconductor degradation over time in an integrated circuit can be made periodically throughout the lifetime of the integrated circuit. This allows for significantly reduced voltage margins, thereby improving computing performance and reducing power consumption of the integrated circuit.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
For clarity, identical reference numbers have been used, where applicable, to designate identical elements that are common between figures. It is contemplated that features of one embodiment may be incorporated in other embodiments without further recitation.
A switch 116 provides connections between I/O bridge 107 and other components such as a network adapter 118 and various add-in cards 120 and 121. Other components (not explicitly shown), including universal serial bus (USB) or other port connections, compact disc (CD) drives, digital versatile disc (DVD) drives, film recording devices, and the like, may also be connected to I/O bridge 107. The various communication paths shown in
In one embodiment, the parallel processing subsystem 112 incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In another embodiment, the parallel processing subsystem 112 incorporates circuitry optimized for general purpose processing, while preserving the underlying computational architecture, described in greater detail herein. In yet another embodiment, the parallel processing subsystem 112 may be integrated with one or more other system elements in a single subsystem, such as joining the memory bridge 105, CPU 102, and I/O bridge 107 to form a system on chip (SoC). In some embodiments, parallel processing system 112 may include multiple processors, such as parallel processor units.
It will be appreciated that the system shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of CPUs 102, and the number of parallel processing subsystems 112, may be modified as desired. For instance, in some embodiments, system memory 104 is connected to CPU 102 directly rather than through a bridge, and other devices communicate with system memory 104 via memory bridge 105 and CPU 102. In other alternative topologies, parallel processing subsystem 112 is connected to I/O bridge 107 or directly to CPU 102, rather than to memory bridge 105. In still other embodiments, I/O bridge 107 and memory bridge 105 might be integrated into a single chip instead of existing as one or more discrete devices. Large embodiments may include two or more CPUs 102 and two or more parallel processing subsystems 112. The particular components shown herein are optional; for instance, any number of add-in cards or peripheral devices might be supported. In some embodiments, switch 116 is eliminated, and network adapter 118 and add-in cards 120, 121 connect directly to I/O bridge 107.
Aging circuit 210 includes an oscillating circuit 205A, such as a ring oscillator, and is coupled to a power source 240 during operation of CPU 102, parallel processing subsystem 112, or other IC. As shown in
Because aging circuit 210 is powered during operation of CPU 102, parallel processing subsystem 112, or other IC of interest, aging circuit 210 undergoes degradation associated with use that is proportional to that experienced by target sub-circuit 203. For example, in one embodiment, target circuit 203 includes one or more LTV transistors, and oscillating circuit 205A is configured for measuring the transistor-level performance of target circuit 203. In such an embodiment, oscillating circuit 205A may include an odd number of inverters 209 and therefore continue to oscillate when coupled to power source 240. In this embodiment, because oscillating circuit 205A is ringing throughout the life of the IC that includes target circuit 203, and is operated at the same voltage as target circuit 203, transistors in oscillating circuit 205A age in a similar fashion to the transistors in target circuit 203. Thus, target circuit 203 and oscillating circuit 205A both slow down over time in a corresponding way when measured at a given voltage and temperature. In such embodiments, oscillating circuit 205A may be configured to oscillate at substantially the same frequency as target circuit 203. Alternatively, oscillating circuit 205A may be configured to oscillate at a different frequency than target circuit 203, and measurements of oscillating circuit 205A are scaled accordingly when determining degradation that has occurred in target circuit 203.
Reference circuit 220 includes an oscillating circuit 205B, and is also coupled to the same power source as aging circuit 210, i.e., power source 240. Oscillating circuit 205B is a second instance of oscillating circuit 205A. Consequently, except for manufacturing variation, oscillating circuit 205B is configured to be substantially identical to oscillating circuit 205A. Unlike aging circuit 210, reference circuit 220 is not coupled to a power source during operation of the IC that includes target circuit 203, and is generally only powered during testing this IC. In the embodiment illustrated in
Because reference circuit 220 is generally not powered during operation of the IC that includes target circuit 203, and testing of this IC typically occurs periodically and over short intervals, reference circuit 220 undergoes essentially no degradation associated with use. Thus, reference circuit 220 can be used as an absolute reference for measuring degradation of aging circuit 210 and, by extension, target circuit 203.
It is noted that various configurations of ring oscillators and other oscillating circuits are known and can be readily devised whose oscillation speed is proportional to different characteristics of sub-circuits in an IC. In this way, a desired behavior of the many transistors and other components that undergo degradation with use over the lifetime of an IC can be quantified. For example, oscillating circuits 205A and 205B can be configured with an oscillation speed that is proportional to wire speed, transistor speed, transistor leak rate, etc. In addition, oscillating circuits 205A and 205B can be configured to quantify the behavior SRAM, NAND gates, NOR gates, and the like. Thus, the embodiment of oscillating circuits 205A and 205B illustrated in
In operation, degradation measurement circuit 200 can be used to periodically quantify changes in performance of target circuit 203. As noted above, during normal operation of an IC that includes degradation measurement circuit 200, aging circuit 210 is coupled to power source 240. Periodically, a test of aging circuit 210 is performed by coupling reference circuit 220 to power source 240 and measuring the resulting frequency of aging circuit 210 and reference circuit 220 with frequency counter 230. In the embodiment illustrated in
The use of aging circuit 210 and reference circuit 220 as described above provides a more accurate reference of the absolute change in performance of a sub-circuit other techniques, such as measuring sub-circuit performance and comparing the measurement to performance of the sub-circuit prior to aging. This is because the initial measurement is taken under conditions that will generally change over time. For instance, voltage can vary due to degradation of a voltage regulator, and/or because a different voltage regulator may be used at different times (e.g. a voltage regulator in a system vs. a voltage regulator on an ATE). Similarly, the variations in temperature cannot be measured with the necessary precision to take into account the associated difference in sub-circuit performance caused by such temperature variation. Thus, comparing an aging and a non-aging circuit that are both effectively at identical temperatures and are coupled to the same power source gives a more accurate reference of absolute change between the circuits.
In some embodiments, aging circuit 210 is configured to be decoupled from power source 240 when an IC that includes degradation measurement circuit 200 operates in low-power mode. In such an embodiment, power consumption associated with running aging circuit 210 is eliminated at a time when available power is at a premium. Because degradation is generally greatly reduced for components of an IC when in low-power mode, the inaccuracy in degradation measurements associated with decoupling aging circuit 210 in such situations is slight.
In other embodiments, aging circuit 210 and reference circuit 220 are co-located on the IC containing degradation measurement circuit 200, or are disposed as close as practicable to each other. In this way, aging circuit 210 and reference circuit 220 can both be assumed to be at substantially identical temperatures. Because the output frequency of aging circuit 210 and reference circuit 220 is affected by temperature, collocation of aging circuit 210 and reference circuit 220 eliminates a significant source of error when measuring output frequencies thereof. Furthermore, in some embodiments, aging circuit 210 and reference circuit 220 have substantially the same orientation, to further insure that sources of error when measuring output frequencies are minimized.
As is well-known in the art, there are various mechanisms that can cause degradation of the components of an IC. Specifically, in one example, transistors subject to operating bias, whether or not the transistors are actually switched, exhibit changes in their operating characteristics over time. Such an effect is know as bias temperature instability (BTI). Typically, BTI causes transistor thresholds to increase, and other electrical parameters, such as drive current and transconductance, are also affected. According to embodiments of the invention, aging circuit 210 is configured to quantify the degradation experienced by target circuit 203 cause by operating bias. In such embodiments, aging circuit 210 is configured to be “usually stopped,” i.e., coupled to power source 240 during normal operation of the IC that includes target circuit 203 but in a static state and not oscillating. Thus, oscillating circuit 205A is subject to operating bias throughout the lifetime of degradation measurement circuit 200, but does not undergoes switching during normal operation. Instead, oscillating circuit 205A generally only oscillates during periodic testing, for example once per week or month, so that frequency counter 230 can measure the output frequency thereof. Such testing typically has very limited duration and results in insignificant degradation of the components of oscillating circuit 205A.
Another mechanism that can cause degradation of transistors in an IC to suffer degradation is due to the switching of said transistors. The high fields associated with increased switching speed are known to induce hot carrier injection (HCI), a phenomenon in which a charge carrier, i.e., an electron or a hole, gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state. The charge carrier can become trapped in the gate dielectric of a MOS transistor, permanently changing the switching characteristics of the transistor. According to embodiments of the invention, aging circuit 210 can be configured to quantify the degradation experienced by target circuit 203 caused by switching of transistors over the lifetime of target circuit 203. In such embodiments, aging circuit 210 is configured to be “usually on,” i.e., coupled to power source 240 during normal operation of target circuit 203 and continuously oscillating. Thus, oscillating circuit 205A is subject to continuous switching operations throughout the lifetime of degradation measurement circuit 200, as well as operating bias. During periodic testing, oscillating circuit 205A continues to oscillate so that an output frequency can be measured by frequency counter 230.
As shown, first aging circuit 310 is configured to enable measurement of components of an IC subject to degradation associated with operating bias and with switching. Second aging circuit 315 is configured to enable measurement of components of an IC subject to degradation associated with operating bias. Thus, first aging circuit 310 is configured to be usually on during normal operation of target circuit 203 and degradation measurement circuit 300, and is generally oscillating continuously. Second aging circuit 315 is configured to be usually stopped during normal operation of target circuit 203 and degradation measurement circuit 300, but does have supply voltage applied from power source 240. During testing, first aging circuit 310, second aging circuit 315, and reference circuit 220 provide outputs to frequency counter 230.
As shown, for a particular desired frequency of operation, such as f, a higher voltage is recommended at end-of-life than at beginning-of-life, due to degradation of the IC or component over time. Without the measurements of degradation provided by a degradation measurement circuit, e.g., degradation measurement circuit 200 and/or 300, a worst-case scenario is generally assumed to guarantee that sufficient voltage margin is used. Specifically, a voltage margin 405 is incorporated into the operation of the IC or component. In other words, to avoid the occurrence of functional failures during the specified lifetime of the IC or component, EOL voltage-frequency curve 402 is typically used when implementing dynamic voltage and frequency scaling (DVFS). Consequently, over most of the useful lifetime of the IC or component, unnecessarily high power consumption and/or reduced performance is experienced. Similarly, a frequency margin may be used in lieu of or in addition to voltage margin 405, such as when voltage cannot be raised further. According to embodiments of the invention, an IC or component may be operated using a modified voltage-frequency curve 404, which is based on the periodic measurement taken using one or more degradation measurement circuits as described herein. Modified voltage-frequency curve 404 can be updated whenever the one or more degradation measurement circuits 200 and/or 300 associated with the IC or component are used to measure degradation of the IC or component. In this way, a minimum recommended voltage is used throughout the lifetime of the IC or component based on the actual condition thereof. This approach reduces energy requirements and/or increases computing performance of the IC or component.
According to other embodiments of the invention, an IC or system, such as CPU 102 or parallel processing subsystem 112 in
Each of processor cores 510, 520, 530, and 540, and each of peripheral logic blocks 551-554 may include one or more measurement circuits 501 formed as a sub-circuit. Measurement circuits 501 are substantially similar in configuration and operation to degradation measurement circuit 200 in
In other embodiments, the multiple measurement circuits 501 in processor cores 510, 520, 530, and 540 may also include redundant measurement circuits. Specifically, two or more of measurement circuits 501 on a particular processor core may be configured to measure the same characteristic. In such embodiments, the redundant measurement circuits can provide more accurate output, either by averaging, elimination of outlying measurements, etc.
As shown, a method 600 begins at step 610, where a processor or other suitably configured device measures an output frequency of a first instance of an oscillating circuit, such as aging circuit 210 in
In step 620, the processor or other suitably configured device measures an output frequency of a second instance of the oscillating circuit, such as reference circuit 220 in
In step 630, the processor or other suitably configured device compares the output frequency of the first instance to the output frequency of the second instance to determine behavior of a sub-circuit of the semiconductor system. Because the oscillating circuit is configured to be proportional to a particular characteristic of one or more sub-circuits or other components in the semiconductor system, such a comparison of output frequencies can provide a quantitative measurement of degradation of the sub-circuits or other components. Particular characteristics that may be monitored include a leakage rate of one or more types of transistors in the semiconductor system, a speed of one or more types of transistors in the semiconductor system, a critical path delay of the semiconductor system, a static random access memory speed of the semiconductor, and a wire delay of the semiconductor system.
In step 640, the processor or other suitably configured device adjusts a voltage-frequency table associated with operating the sub-circuit of interest in the semiconductor system, where the adjustment is based on the behavior of the sub-circuit of the semiconductor system determined in step 630. Such an adjustment allows the sub-circuit of interest to be operated using a modified voltage-frequency curve, such as modified voltage-frequency curve 404 in
In sum, embodiments of the invention set forth systems and methods for monitoring the degradation over time of one or more portions of an integrated circuit. A first instance and a second instance of an oscillating circuit are each formed as part of the integrated circuit being monitored, where the first instance of the oscillating circuit is configured to be coupled to a power source during normal operation of the integrated circuit and the second instance is configured to be decoupled from the power source. Over the lifetime of the integrated circuit being monitored, the first instance undergoes degradation from use corresponding to degradation of the integrated circuit while the second instance of the oscillating circuit remains unpowered, therefore experiencing essentially no use-related degradation. During a testing operation, the second instance can be used as a reference circuit that accurately quantifies use-related degradation of the first instance of the oscillating circuit and, by extension, one or more portions of the integrated circuit.
One advantage of the present invention is that accurate measurement of semiconductor degradation over time in an integrated circuit can be made periodically throughout the lifetime of the integrated circuit. This allows for significantly reduced voltage margins, thereby improving computing performance and reducing power consumption of the integrated circuit.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
