Patent Application
20050083766
Off-chip driver (OCD) circuits are employed by semiconductor devices, including dynamic random access memory (DRAM) devices, to provide off-chip interfacing to external buses or external devices. The OCD circuits are generally required to provide an output signal that meets specified operating parameters of the external device. For example, OCD circuits are generally required to provide an output signal having a signal strength that is within a specified current range and a slew rate that is within a specified range of voltage rates.
The signal strength and slew rate are affected by many factors such as voltage variation of an OCD supply voltage (VDDQ), process variations, variations in operating temperature, and even data patterns. Regarding signal strength, the most significant factor is variations in the magnitude of VDDQ. If VDDQ is too high or too low, the output signal strength may respectively exceed or fall below the specified operating range. The largest factor affecting slew rate is the AC transient operation of the OCD circuit, which is in-turn dependent VDDQ. If VDDQ is too high or too low, the slew rate may respectively exceed or fall below a specified slew rate range.
Generally, an OCD circuit is designed during the final stages of development of a DRAM device. However, due to the various factors that can impact the signal strength and slew rate, it can be difficult to design an OCD circuit that meets specified operating parameters and often leads to costly delays in the fabrication and mass-production of the DRAM device.
One embodiment of the present invention provides a random access memory device including a memory array, a level detector, and an off-chip driver circuit. The level detector monitors a source voltage and provides a level signal representative of a voltage range of the source voltage. The off-chip driver circuit is associated with the memory array and provides an output signal having at least one operating parameter, and adjusts the at least one operating parameter by adjusting a magnitude of at least one impedance based on the level signal.
In the following Detailed Description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
OCD circuit 40 receives an output enable (OE) signal from memory controller 31 via a path 43 and a data signal representative of data stored in memory array 32 via a path 44, and is coupled to a supply voltage (VDDQ) 46 via a path 48. Level detector 38 is coupled to VDDQ 46 at 48 and provides a level signal representative of a voltage range of VDDQ 46 to OCD circuit 40 via a path 50. OCD circuit 40, in response to the OE signal at 43 and the data signal from memory array 32 at 44, provides an output signal representative of the stored data at DQ 42, wherein the output signal has at least one operating parameter. OCD circuit 40 adjusts the operating parameter based on level signal received from level detector 38 via path 50.
By adjusting the operating parameter of the output signal based on the level signal, OCD circuit 40 is able to maintain the operating parameter within a specified range required by an external device 52 receiving the output signal at DQ 42 via a path 54. In one embodiment, the operating parameter comprises an output current, or signal strength of the output signal. In one embodiment, the operating parameter comprises a rate of change of an output voltage over time, or slew rate, of the output signal.
R172 has a first terminal coupled to VDDQ 46, and a second terminal coupled to an inverting terminal 82 of comparator 70. R274 has a first terminal coupled to inverting terminal 82 and a second terminal coupled to a reference node (VSSQ) 84. In one embodiment, VSSQ 84 is a negative source voltage. In one embodiment, VSSQ 84 is a ground node. A non-inverting terminal 86 of comparator 70 is coupled to a substantially constant reference voltage (Vref). R172 and R274 function as a voltage divider with the voltage across R274 providing the minimum voltage level (Vmin) of the voltage range at inverting terminal 82. When Vmin at inverting terminal 82 drops below Vref 88 at non-inverting terminal 86, comparator 70 provides a first level signal (Omin) 90 having a “high” level (i.e., “1”) at an output 92. When Vmin at inverting terminal 82 is greater than or equal to Vref 88, Omin 90 has a “low” level (i.e., “0”).
R378 has a first terminal coupled to VDDQ 46, and a second terminal coupled to an inverting terminal 94 of comparator 76. R480 has a first terminal coupled to inverting terminal 94 and a second terminal coupled to VSSQ 84. A non-inverting terminal 96 of comparator 70 is coupled to Vref 88. R378 and R480 function as a voltage divider with the voltage across R480 providing the maximum voltage level (Vmax) of the voltage range at inverting terminal 94. When Vmax at inverting terminal 96 rises above Vref at non-inverting terminal 96, comparator 76 provides at an output 98 a second level signal (Omax) 100 having a “high” level (i.e., “1”). When Vmax at inverting terminal 94 is less than or equal to Vref 88, Omax 100 has a “low” level (i.e., “0”).
As an illustrative example, assume that R172 comprises 48% and R274 comprises 52% of the sum of R172 and R274. Also assume that R378 is equal to R274, that R480 is equal to R172, and that Vref 88 has a substantially constant value of 1.25 volts. Using these values, Omin 90 has a “high” level when VDDQ drops below approximately 2.4 volts and Omax 100 has a “high” level when VDDQ rises above approximately 2.6 volts. Omin 90 and Omax 100 each have a “low” level when VDDQ is at or between 2.4 and 2.6 volts.
Logic circuit 120 further includes an AND-gate 128, an OR-gate 130, and an inverter 132. AND-gate 128 receives data signal 48 at a first input and OE 44 at a second input, and provides a pull-up enable signal (PUin) 134 at an output. OR-gate 130 receives data signal 46 at a first input and OE 44 via inverter 132 at a second gate, and provides a pull-down enable signal (PDin) 136 at an output. PUin 134 has a “high” level when OE 44 has a “high” level and data signal 44 has a “high” level, and a “low” level when OE 44 has a “high” level and data signal 44 has a “low” level. PDin 136 has a “high” level
Pull-up pre-driver circuit 122 receives PUin 134 from logic circuit 120 and Omin 90 and Omax 100 from level detector 38, and provides a first pull-up signal (PU1) 138, a second pull-up signal (PU2) 140, and a third pull-up signal (PU3) 142. Pull-down pre-driver circuit 124 receives PDin 136 from logic circuit 120 and Omin 90 and Omax 100 from level detector 38, and provides first pull-down signal (PD1) 144, second pull-down signal (PD2) 146, and third pull-down signal (PD3) 148.
Output driver circuit 126 includes PMOS switches P1150, P2152, P3154, and NMOS switches N1156, N2158, and N3160. The gates of P1150, P2152, and P3154 respectively receive PU1138, PU2140, and PU3142 from pull-up pre-driver circuit 122. The sources and drains of P1150, P2152, and P3154 are respectively coupled to VDDQ 46 and DQ 42. The gates of N1156, N2158, and N3160 respectively receive PD1144, PD2146, and PD3148. The drains and sources of N1156, N2158, and N3160 are respectively coupled to DQ 42 and VSSQ 84.
When both OE 44 and data signal 46 are “high”, pull-down circuit 124 turns-off NMOS switches N1156, N2158, and N3160 to isolate DQ 42 from VSSQ 84, and pull-up circuit 122 controls PMOS switches P1150, P2152, and P3154 based on the levels of Omin 90 and Omax 100. When both Omin 90 and Omax 100 are “low”, meaning VDDQ 46 is within a desired voltage range, pull-up circuit 122 turns-on P1150 and P2152 to connect DQ 42 to VDDQ 46 and thereby provide an output signal having an output current at DQ 42. When Omin is “high”, meaning VDDQ 38 is below the desired voltage range, pull-up circuit 122 also turns-on P3154 to reduce the impedance between DQ 42 and VDDQ 46, thereby increasing the output current, and thus the output signal strength, at DQ 42. When Omax is “high”, meaning VDDQ 46 is above the desired voltage range, pull-up circuit 122 turns-off P2152 leaving only P1150 turned-on. This increases the impedance between DQ 42 and VDDQ 46, thereby decreasing the output current, and thus the output signal strength, at DQ 42.
When OE 44 is “high” and data signal 46 is “low”, pull-up circuit 124 turns-off PMOS switches P1150, P2152, and P3154 to isolate DQ 42 from VDDQ 46, and pull-down circuit 124 controls NMOS switches N1156, N2158, and N3160 based on the states of Omin 90 and Omax 100. When both Omin 90 and Omax 100 are “low”, meaning VDDQ 46 is within the desired voltage range, pull-down circuit turns-on NMOS switches N1156 and N2158 to connect DQ 42 to VSSQ 84 and thereby provide an output signal having an “output” current at DQ 42. When Omin is “high”, meaning that VDDQ 38 is below the desired voltage range, pull-down circuit 124 also turn-on NMOS switch 160. This decreases the impedance between DQ 42 and VSSQ 84, thereby increasing the “output” current by increasing the current sinking ability to VSSQ 84. When Omax is “high”, meaning that VDDQ 38 is above the desired voltage range, pull-down circuit 124 turns-off NMOS switches 158 and 160, leaving only NMOS switch 156 turned-on. This increases the impedance between DQ 42 and VSSQ 84, thereby decreasing the “output” current by decreasing the current sinking ability to VSSQ 84.
When OE 44 is “low”, meaning the output of OCD circuit 40 is disabled, pull-up circuit 122 turns-off PMOS switches P1150, P2152, and P3154, and pull-down circuit 124 turns-off NMOS switches N1156, N2158, and N3160 to thereby isolate DQ 42 from both VDDQ 46 and VSSQ 84.
When PUin 134 has a “low” level, PU1138, PU2140, and PU3142 each have a “high” level, causing PMOS switches P1150, P2152, and P3154 to be turned-off. When PUin 134 has a “high” level, the levels of PU1138, PU2140, and PU3142 are based on the levels of Omin 90 and Omax 100. When Omin 90 and Omax 100 are both “low”, PU1138 and PU2140 are “low” and PU3142 are “high”, resulting in PMOS switches P1150 and P2152 being turned-on and P3154 being turned-off. When Omin 90 is “high” and Omax 100 is “low”, PU1138, PU2140, and PU3142 each have a “low” level, causing PMOS switches P1150, P2152, and P3154 to be turned-on. When Omin 90 is “low” and Omax 100 is “high”, PU1138 is “low” and PU2140 and PU3142 are “high”, causing PMOS switch P1150 is turned-on and PMOS switches P2152 and P3154 are turned-off.
When PDin 136 has a “high” level, PD1144, PD2146, and PD3148 each have a “low” level, causing NMOS switches N1156, N2158, and N3160 to be turned-off. When PDin 136 has a “low” level, the levels of PD1144, PD2146, and PD3148 are based on the levels of Omin 90 and Omax 100. When Omin 90 and Omax 100 are both “low”, PD1144 and PD2146 are “high” and PD3148 is “low” , causing NMOS switches N1156 and N2158 to be turned-on and switch N3160 to be turned-off. When Omin 90 is “high” and Omax 100 is “low”, PD1144, PD2146, and PD3148 each have a “high” level, causing NMOS switches N1156, N2158, and N3160 to be turned-on. When Omin 90 is “low” and Omax 100 is “high”, PD1144 has a “high” level and PD2146 and PD3148 each have a “low” level, causing NMOS switch N1156 to be turned-on and NMOS switches N2158 and N3160 to be turned-off.
Pull-up pre-driver circuit 222 receives PUin 134 from logic circuit 120 and Omin 90 and Omax 100 from level detector 38, and provides a pull-up signal PU1228. Pull-down pre-driver circuit 224 receives PDin 136 from logic circuit 120 and Omin 90 and Omax 100 from level dectector 38, and provides a pull-down signal PD1230.
Output driver circuit 226 includes a PMOS switch P1232 and an NMOS switch N1234. P1232 receives PU1228 at a gate, has a source coupled to VDDQ 46, and has a drain coupled to DQ 42. N1234 receives PD1230 at a gate, has a drain coupled to DQ 42, and a source coupled to VSSQ 84.
When both OE 44 and data signal 46 are “high”, pull-down circuit 224 turns-off N1234 to isolate DQ 42 from VSSQ 84, and pull-up circuit 222 controls the current at the gate of P1232 based on the levels of Omin 90 and Omax 100. When Omin 90 is “high”, meaning VDDQ is below a desired voltage range, pull-up pre-driver circuit 122 increases the current at the gate of P1232 to increase the slew-rate. When Omax 100 is “high”, meaning VDDQ is above the desired voltage range, pull-up pre-driver circuit 222 decreases the current at the gate of P1232 to decrease the slew-rate. When both Omin 90 and Omax 100 are “low”, pull-up pre-driver circuit 222 does not adjust the current at the gate of P1232.
When OE 44 is “high” and data signal 46 is “low”, pull-up circuit 222 turns-off P1232 to isolate DQ 42 from VDDQ 46, and pull-down circuit 224 controls the current at the gate of N1234 based on the levels of Omin 90 and Omax 100. When Omin 90 is “high”, meaning VDDQ is below the desired voltage range, pull-down pre-driver circuit 224 increases the current at the gate of N1234 to increase the slew rate. When Omax 100 is “high”, meaning that VDDQ is above the desired voltage range, pull-down circuit 224 decreases the current at the gate of N1234 to decrease the slew rate. When both Omin 90 and Omax 100 are “low”, pull-down pre-driver circuit 224 does not adjust the current at the gate of N1234.
When OE 44 is “low”, pull-up pre-driver circuit 222 turns-off P1232 and pull-down pre-driver circuit 224 turns-off N1234 to isolate DQ 42 from VDDQ 46 and VSSQ 84.
When PUin 134 is “low” PU1 is high, causing P1232 to be turned-off. Additionally, N2244 and N3248 are turned-off, causing the gate of P1232 to be isolated from VSSQ 84.
When PUin 134 is “high”, switch P1232 is turned-on and NMOS switches N2244, N4246, N3248, and N5250 are turned-on and -off based on the levels of Omin 90 and Omax 100. When Omin 90 and Omax 100 are “low”, meaning that VDDQ 46 is within the specified voltage range, switches N1244, N2246, and N3248 are turned-on and N5250 is turned-off, causing the gate of P1232 to be coupled to VSSQ 84 through N2244 and N4246.
When Omin 90 is “high” and Omax 100 is “low”, meaning that VDDQ is below the specified voltage range, switch N5250 is also turned-on. As a result, the impedance between the gate of P1232 and VSSQ 84 is reduced, thereby increasing the rate at which P1232 is turned-on and increasing the output signal slew-rate at DQ 42. When Omin 90 is “low” and Omax 100 is “high”, meaning that VDDQ is above the specified voltage range, switches N4246 and N5250 are turned-off. As a result, the gate of P1232 is isolated from VSSQ 84, thereby decreasing the rate at which P1232 is turned-on and decreasing the output signal slew rate at DQ 42.
When PDin 230 is “high” PD1 is “low”, causing N1234 to be turned-off. Additionally, switches P4266 and P5270 are turned-off, causing the gate of N1234 to be isolated from VDDQ 46.
When PDin 230 is “low”, switch N1234 is turned-on and PMOS switches P2264, P3268, P4266, and P5270 are turned-on and -off based on the levels of Omin 90 and Omax 100. When Omin 90 and Omax 100 are “low”, meaning that VDDQ 46 is within the specified voltage range, switches P3268, P4266, and P5270 are turned-on and P2264 is turned-off, causing the gate of N1234 to be pulled to VDDQ 46 through P3268 and P4270 P1 to be turn-on.
When Omin 90 is “high” and Omax 100 is “low”, meaning that VDDQ is below the specified voltage range, switch P2264 is also turned-on. As a result, the impedance between the gate of N1234 and VDDQ 46 is reduced, thereby increasing the rate at which N1234 is turned-on and increasing the output signal slew-rate at DQ 42. When Omin 90 is “low” and Omax 100 is “high”, meaning that VDDQ is above the specified voltage range, switches P2264 and P3268 are turned-off. As a result, the gate of N1234 is isolated from VDDQ 84, thereby decreasing the rate at which N1234 is turned-on and decreasing the output signal slew rate at DQ 42.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
