Patent Application
20150258769
1. Field of the Invention
This invention applies to epitaxially grown solar cells and specifically to inverted solar cell structures. Inverted metamorphic III-V multi-junction solar cells achieve the highest efficiencies (>30% in space and >40% terrestrial under concentrator). These cells are grown epitaxially on Ge or GaAs wafers that are up to 700 μm thick. The solar photons are absorbed in the epitaxial layer, which is about 10 μm thick. The substrate is only for mechanical support and considered wasted from a materials point of view. Triple-junction solar cells for space cost>$250/W. This high cost is split among the cost of the substrate (40%), epitaxial growth (30%) and front side processing including metallization (30%). Epitaxial lift-off (ELO) is used to transfer the epi-layer to a flexible substrate and reuse the Ge or GaAs wafer to grow another epi-layer. There is a need to make high efficiency solar cells thin, lightweight and flexible to achieve high specific power (>200 W/Kg); and foldable so that they can be stowed in a small volume to increase payload space. It is desired to transfer the epi-layer to polyimide substrate and to reuse the Ge or GaAs wafer multiple times. A new cost-effective dry lift-off process which transfers the active cell layer wafer-scale to a less expensive flexible polyimide substrate without ion implantation or chemical etching is presented. This yields thin high efficiency solar cells which have the same performance on the host substrate as on the growth substrate and which are easily scalable to large size arrays. This process applies to all semiconductor substrates including Si, Ge, GaAs and InP and allows re-using of the base semiconductor wafer to grow new cells which results in savings in materials, grinding and etching expenses. This technology reduces the cost of the cell by 30% and allows very rapid growth of the terrestrial market for high efficiency III-V solar cells.
A dry epitaxial lift-off (DELO) process is presented by driving a crack at the epi/wafer interface and transferring wafer scale to a polyimide substrate which is used as the stressor layer and permanent carrier of the fragile solar cell, thus eliminating the need for detaching. The polyimide substrate has a thickness between 25 and 250 μm. Preferably, a thickness between 50 and 100 μm provides sufficient driving force and yields a specific power ratio>1000 W/Kg. The crack is driven purely by the thermal stresses due to the mismatch in CTE between GaAs and polyimide without the necessity for any external mechanical force or tool to aid crack propagation. This allows the use of automated roll-to-roll processes which reduce the cost even further. In order to reduce the cost of the cell a single junction GaAs solar cell with efficiency>20% at AM1.5 [1] can be used which simplifies the solar cell structure considerably and reduces the cost of epitaxial growth significantly compared to the triple junction. This process yields single atomic plane horizontal cleavage which reduces the need for post lift-off polishing, which allows multiple reuses of the substrate. This combined with cheaper metallization techniques such as aerosol jet printing, which is a maskless additive manufacturing technology, allows reducing the cost down to $50/W, which makes it attractive for terrestrial applications.
2. Discussion of Related Art
Inverted metamorphic (IMM) solar cells are grown epitaxially inverted (high bandgap junction first, low bandgap junction last) on Ge or GaAs wafers in multiple layers, as shown in
The (110) is the preferred cleavage plane in GaAs. However, solar cell manufacturers are reluctant to grow on (110) wafers because most of the industry is built on (100) wafers, albeit with large off-cut angles up to 15° toward the (111)A plane.
The ultimate goal of all lift-off techniques is to re-use the base wafer after lift-off.
It is desired to cleave atomically flat surfaces at or very near the epi/wafer interface in order to minimize post lift-off polishing and avoid wasting substrate material. III-V materials have the advantage that devices are fabricated in epitaxially-grown layers. Thus, the epi-layer can be peeled off the substrate and transferred to a flexible carrier and the substrate can be reused to grow another epi-layer. If the quality of the surface is good and the substrate is recovered at original thickness then the substrate can be reused multiple, perhaps more than 10 times. The fragile crystalline solar cell must be supported at all times. A suitable flexible carrier is polyimide Kapton® sheet which is manufactured by DuPont and qualified for space applications. Kapton is available in sheets as thin as 25 μm which are easy to handle and come pre-coated with a uniform layer of acrylic adhesive. It operates continuously from cryogenic to >200° C. which is suitable for space and terrestrial applications. A Kapton sheet with adhesive layer is bonded to the epi-side of GaAs wafer using a hot roll laminator and then cured in an oven at 150-190° C. for about an hour. After lift-off the thin epi-layer is carried by the Kapton sheet which serves as permanent carrier of the solar cell. The entire thickness of the thin solar cell is less than 200 μm, which meets the specific power requirement.
A sheet of polyimide as thin as 50 μm bonded to a GaAs wafer of any size lifts a layer of GaAs about 10-20 μm thick off the substrate when immersed in liquid nitrogen within a minute. A crack nucleates with an audible sound at a temperature about −140° C. as the wafer is lowered in the Dewar even before it touches the liquid. The crack propagates beneath the surface at a depth which is prescribed by the thickness of the polyimide/GaAs wafer ratio. The crack propagates across the wafer in a split second. Two wafers ensue: the base wafer in one piece, and the epi-layer on the polyimide. There are no cracks in the epi-layer on the polyimide. The lift-off was captured on video and can be seen at the following link: http://www.youtube.com/watch?v=BR1LDdZabg. The video takes only 48 seconds. Lift-off happens at second 40.
Kapton® tape which is commercially available and comes pre-coated with a thin adhesive layer is perfect for this application and is even qualified for space. This is very convenient because it is not easy to apply an adhesive layer uniformly over an entire 4″ wafer. The adhesive layer must be uniform in order to carry a fragile epi-layer 1-10 μm thick without fracturing it. Kapton is available in layers as thin as 25 μm in 25 μm increments. Multiple layers can be laminated sequentially to obtain any desired thickness. Cooling in LN2 is advantageous because GaAs becomes even more brittle at −196° C. which lowers the energy to propagate the crack. The organic adhesive material has sufficient shear strength and holds its grip at cryogenic temperature and is able to transmit the force necessary to rupture the semiconductor wafer, even Gallium Nitride (GaN) and Silicon Carbide (SiC) which have a fracture toughness and elastic modulus larger than GaAs. The entire lift-off happens within a couple of minutes. It was not known previously that a commercial off-the-shelf Kapton tape could be bonded to a semiconductor wafer and causes it to cleave a thin layer at a depth between 10 and 20 μm simply by dunking in LN2.
The polyimide serves not only as the permanent carrier of the thin crystalline solar cell but also as stressor layer which creates the thermal stresses that lead to cleavage. The temperature is lowered by introducing the composite structure slowly in liquid nitrogen at −196° C. Within a minute, an audible crack initiates and the film snaps right off A polyimide thickness between 50 and 100 μm is able to lift-off a GaAs thickness between 10 and 20 μm and achieves a specific power ratio of 1000 W/Kg for space and terrestrial applications (see calculation of specific power in the Appendix). At this thickness the polyimide packs just enough elastic strain energy to initiate and propagate the crack through the wafer at the desired depth. In fact most of the strain energy is stored in the polyimide itself Kapton has a CTE about 16×10−6/° C. and GaAs 6×10−6/° C. The composite structure is subjected to a temperature drop of about 300° C. (between the curing temperature and LN2). Thus, the driving thermal strain ΔαΔT=3×10−3. This thermal strain produces a tensile stress in the GaAs between 20 and 60 MPa which is sufficient to initiate the crack and overcome the resistance to its propagation. The stress intensity factor KI which represents the stress concentration factor at the tip of the crack is related to the stress σ and the depth of the scratch a as KI=σ√{square root over (πa)} When the stress intensity factor exceeds the fracture toughness of the material KIc the crack starts to propagate. Thus, a scratch depth of about 20-40 μm is needed to initiate the crack, which can be readily achieved either by scratching manually with a diamond tip or with a nano-indenter. Crack nucleation is due solely to the build-up of thermal stresses without applying external mechanical force. The crack propagates across the wafer in about 0.1 milli-second. The wafer cleaves spontaneously at a plane parallel to the bond interface. For GaAs the lift-off temperature is about −140° C. whereas for Si the wafer must be cooled down to −196° C. The lift-off happens in a split-second and was captured on video. The front side of the solar cell can be processed on the Kapton after lift-off. The concept applies to all semiconductor materials, Si, Ge, GaAs, InP, GaN and SiC and to all epitaxially grown solar cells for space as well as terrestrial applications. The concept is illustrated in
The sequence of frames in
The following video clips show the rolling and unrolling of GaAs epitaxial layers on Kapton as it is thermally cycled between a hot plate at +100° C. and −196° C. These movies take less than a minute each: http://www.youtube.com/watch?v=WED8cj2YfIw 1:33 min rolling and unrolling http://www.youtube.com/watch?v=U5rxiwkenmI 1:00 min rolling and unrolling
A lifted-off GaAs layer on Kapton can be held flat on a standard vacuum chuck. The following video shows the lifted-off layer spinning at 3000 RPM which allows fabrication of the front side of the solar cell. http://wvvw.youtube.com/watch?v=VC6v7_RAOok The video takes only 9 seconds.
The polyimide is very advantageous because it is able to induce lift-off for a temperature drop ΔT of only 300° C. compared to metal which requires raising to >800° C. Furthermore, it is completely inert and does not contaminate the semiconductor layer. This process is low temperature between +200° C. and −196° C. The combination of polyimide/adhesive is tough and can withstand these temperatures. The acrylic adhesive holds in liquid nitrogen and is able to transmit the force and break-off a layer of semiconductor wafer without losing its grip. The adhesive layer is applied uniformly to Kapton. It has a smooth surface and supports the epi-layer over the entire 4″ wafer.
a and
A Kapton film 50-100 μm thick carrying a GaAs layer 10-15 μm thick curls to a radius of about 15 mm in LN2 as shown in
The residual stress causes curvature at room temperature which depends on the relative thickness of GaAs/polyimide, as shown in
The two parameters that influence crack propagation are the thickness of polyimide and the depth of the initial scratch. If the polyimide is too thin (<50 μm) then there is not enough elastic strain energy to overcome the resistance to crack propagation, i.e. the surface energy. If the polyimide is too thick (>300 μm) then several cracks start simultaneously. The wafer shatters in many pieces to increase the surface of the crack. The cracks will start even without scratching due to defects on the surface of the wafer. This leads to uncontrollable crack propagation. However, a scratch with the right depth is needed to obtain a controlled crack. If the scratch is too shallow then the crack will not propagate because the stress intensity factor is below the fracture toughness. If the scratch is too deep then the crack may continue along its vertical path until it hits the adhesive and may not turn sideways. Thus, controlling the crack is a delicate balance between scratching and the thickness of polyimide. A polyimide thickness between 50 and 100 μm lifts-off a layer 10-20 μm from a GaAs wafer 500-700 μm thick which are typically used to grow III-V IMM solar cells. The base wafer separates nicely in one piece and there are no cracks on the polyimide. Luckily this thickness range yields a rugged yet flexible solar sheet which meets the specific power requirement of 1000 W/Kg for space and terrestrial.
A rectangular strip of Si wafer was laminated with Kapton, but the Kapton was purposefully terminated before the edge of the strip, as shown in
Substrates of different shapes were cleaved with polyimide.
The GaAs wafer is subjected to tremendous stresses at lift-off which can cause the backside of the wafer to shatter rather than separate smoothly in one piece. When the polyimide is too thick (>300 μm) then several cracks start simultaneously even without scratching. This leads to uncontrollable crack propagation. The polyimide packs significant elastic strain energy and the wafer shatters in many small rectangular pieces to increase the surface of the crack. This happened mainly with GaAs (100) wafers that were scratched near and parallel to the flat edge. A crack may have originated from the scratch, but it was not the only one. The scratch did not prevent other spontaneous auto-initiated cracks from starting. The GaAs wafers started cracking even before they reached −196° C. when they were exposed to nitrogen gas. Cracks developed at right angles (parallel and perpendicular to the scratch) and the piece cleaved in many small rectangular pieces, as shown in
The success of the epitaxial lift-off by crack propagation hinges on a delicate balance between the initial scratching and the loading by the polyimide which depends on the polyimide-to-GaAs thickness ratio and the crystallographic orientation of the wafer. GaAs (110) cleaves smoother and more uniformly than (100). The extent of the lateral crack propagation also depends on the thickness ratio. Thicker polyimide causes the crack to propagate farther but lifts-off a thicker layer and may break the wafer. It is desired to minimize the thickness of polyimide to increase the specific power ratio for space applications. The right combination of stresses is necessary to guide the crack near the interface. However, thermal stresses cause significant bow. It is desired to minimize the effect of stresses on the performance of the solar cell.
Precise control over crack propagation is necessary to lift-off layers with uniform thickness and smooth surface. Atomically smooth cleaved surfaces were obtained by controlling the crack propagation. The polyimide applies pure bending moment on the GaAs wafer which is the optimal mode of opening a crack in tension (Mode I). Shearing stresses (Mode II) cause deviation in the path and uncontrollable crack propagation [16]. If these requirements are not met then the crack can bifurcate and branch out and cause secondary cracks to propagate at different angles along different paths. To maximize yield in production a fundamental understanding of fracture mechanics at the nano-scale is essential. For industrial applications this process must be controlled. The focus of the research is to better understand the stress mechanisms that lead to rupture and how to control the path of the crack. The challenges are controlling the crack propagation depth near the epi/wafer interface and preventing the substrate from shattering.
The accompanying drawings are not intended to be drawn to scale. In the drawings:
a Schematic of wafer with epi-layer bonded to Kapton® polymeric permanent carrier;
b Schematic of wafer separated and solar cell carried by Kapton® after lift-off;
a GaAs (110) wafer lifted on Kapton (right), base wafer (left);
b top GaAs (110) wafer lifted on Kapton (left), base wafer (left) broken to six pieces, bottom base wafer saved in one piece;
a Triangular wafer piece unscratched;
b Triangular wafer piece scratched along common edge;
a Unit cell of GaAs;
b Unit cell of GaAs;
a Vertical crack stops at compressive InGaAs layer;
b Crack guided around complex shape;
a Solar cell for space 6.6 cm×4 cm bonded to 4″ polyimide wafer (half circle) on one side and Kapton on the other side;
b Base GaAs wafer on the polyimide wafer and the epi-layer on the Kapton after lift-off;
4″ GaAs wafer diced yields two cells for space applications. Several cells are integrated on common blanket polyimide sheet. Photo courtesy of Sharp Corporation;
a Contacting both sides of IMM cell from the top of the wafer;
b Interconnecting of several IMM cells in series;
a Deformations of 8-layer solar cell structure at −200° C. for Spray-on Polyimide Thickness of 25 μm, at different CTE's, flat at CTE=16.5 ppm/° C.;
b Deformations of 8-layer solar cell structure at −200° C. for Spray-on Polyimide Thickness of 50 μm, at different CTE's, flat at CTE=20 ppm/° C.;
a GaAs/polyimide composite structure at the temperature of zero stress;
b Thermal strain in GaAs and polyimide;
c Bending of GaAs/polyimide composite structure due to thermal stress;
a 1/R and bending stresses vs h for GaAs 370 μm thick and ΔT=300° C. before lift-off;
b 1/R and bending stresses vs h for Si 200 μm thick and ΔT=300° C. before lift-off;
a 1/R and bending stresses vs h′ for GaAs 20 μm thick and ΔT=300° C. after lift-off;
b GaAs 20 μm thick on Kapton 50 μm in liquid nitrogen having a radius of about 4 cm;
a Elastic strain energy of GaAs/polyimide before crack propagation;
b Elastic strain energy of GaAs/polyimide after crack propagation;
a U/Lb vs thickness for GaAs, polyimide h2=150 μm, showing range of residual energy in lifted-off layer corresponding to surface energy;
b U/Lb vs thickness for Si, polyimide h2=150 μm, showing range of residual energy in lifted-off layer corresponding to surface energy;
a SiC/Kapton laminate bent in LN2;
b GaN/Kapton laminate bent in LN2;
This invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including”, “comprising”, or “having”, “containing”, “involving”, “triple-junction” or “multi-junction” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
It is desired to cleave a single atomic plane to reduce the amount of polishing and thickness variation after each lift-off. A touch polish would only be necessary followed by cleaning of the surface. The (110) is the preferred cleavage plane in GaAs because it has the lowest fracture toughness. GaAs presents anisotropy with KI varying between 0.31 and 0.46 MPam1/2 along different <110> directions. The origin of the anisotropy lies in the difference between dislocation mobilities along the different directions [10,11]. The mobility of <110> dislocations on As-terminated planes is much higher than on Ga-terminated {111} planes (Warren et al. 1984). A (100) surface contains 2 <110> vectors perpendicular to each other. Thus, the effective value of KIc depends on whether the scratch is parallel or perpendicular to the flat.
Smoother cleaved surfaces were obtained on (110) than (100) planes.
Horizontal crack propagation in non-crystalline materials has been investigated theoretically and experimentally since the late 80's [2,3,4]. However, horizontal cleavage or spalling of crystalline semiconductor substrates, especially those carrying solar cells, has only been investigated in the last few years [5,6,7]. When a composite structure is subjected to thermal stresses upon cooling, a vertical crack opens under tensile stresses in pure mode I because there is no mechanism to open a horizontal crack. However, as the crack propagates downward it encounters significant shear stresses which cause deviation of its path. Horizontal crack propagation is due to mixed-mode I (opening) and II (shear) stress at the crack tip. The theoretical investigations attempt to calculate the stress intensity factors (KI and KII) at the crack tip due to an over-layer with residual tensile stress, and suggest that the horizontal crack propagates at a depth where KII=0. KI is related to the stress a and the depth of the scratch a, as mentioned above. The theory of fracture mechanics assumes that a crack already exists, but does not pay particular attention to where it nucleated or how it started. When a crack reaches a certain length under a certain stress, such that KI=KIc which is a material property called the fracture toughness, the crack starts to propagate on its own. According to Thouless [2] no matter where the crack starts, it ends up propagating at the same depth. For this reason it is called “steady-state” propagation. The calculation of KI and KII is not straightforward. Alternatively, the depth of cleavage can be predicted from the principle of conservation of energy. According to Griffith's criterion, once the crack starts to propagate the energy release rate G, i.e. the change in the elastic strain energy of the system per unit crack advance is constant, pinned at the surface energy 2γs, which is a material property.
The crack opens vertically in pure mode I at the upper surface where the stress and KI are maximal, as shown in
Kapton polyimide tape is used as the stressor layer and permanent carrier. The fragile solar cell is supported at all times. The use of Kapton is more advantageous than metallic substrates. The front side of the solar cell is processed on the Kapton after lift-off at temperatures that do not exceed 200° C. The process can be automated on a roll-to-roll basis because the driving force behind the crack is due solely to the thermal stresses without the help of any external force that must be applied manually to each individual wafer. Several, up to hundreds of GaAs 4″ wafers can be placed face down on a roll of Kapton up to tens of meters long and processed simultaneously. Scribing on the backside can also be automated because it does not involve scratching the edge of the wafer or using special tools. A scribing machine can be programmed with the exact load to yield precisely the desired scratch depth (20-40 μm) required to propagate the crack. The Kapton sheet holding the wafers can be folded at the seams and heated in an oven at 150-190° C. to cure the adhesive and then bathed in LN2. The base wafers just pop-off the Kapton collectively and are recovered while the epi-layers remain on the Kapton sheet. The assembly is subsequently electroplated with copper and adjacent cells are connected in series or parallel. Both sides of the epi-layer solar cell can be contacted electrically from the top side of the wafer without going through the Kapton, as shown in
A single crack has been launched successfully competing with spontaneous crack nucleation. Uniform bonding and cleavage across 4″ wafer was demonstrated showing that a polyimide film can carry a thin epitaxial layer free of cracks; and the base wafer was saved in one piece and can be reused to grow another epi-layer. The depth of cleavage can be changed by varying the thickness of the polyimide.
The technology is very simple. It only involves laminating using a desk laminator, scratching the backside, curing in an oven and cooling in liquid nitrogen and voila! The wafer separates in two pieces and the epi-layer is lifted-off onto the polyimide substrate.
The use of Kapton as the stressor layer is novel. It is very convenient to induce lift-off with a substrate that also serves as the final carrier of the solar cell because there is no need to dissolve or detach the substrate. By controlling the depth of cleavage precisely in conjunction with single atomic plane cleavage it is possible to lift-off exactly the thickness of GaAs that was grown epitaxially, so that the substrate remains at its original thickness after every lift-off. This allows up to 10 or more reuses of the substrate.
It is remarkable that single atomic plane cleavage was obtained from a hand scratch. This was not obtained with any of the other dry ELO techniques. It is desired to widen the area of single atomic plane cleavage and improve the quality of the cleaved surface and to minimize thickness variation. This requires more control over the crack path to determine exactly where it turns and how it transitions from a vertical crack to a horizontal crack. This can be accomplished either by scratching more precisely with a nano-indenter or by embedding a layer of lower fracture toughness at the desired depth to help guide the crack. This is necessary to facilitate processing the cleaved epitaxial layers into functional solar cells. The goal is to minimize the necessity to repolish the substrate and increase the number of substrate reuses.
Scratching with Nano-Indenter
The goal of scratching is to create a single dominant crack, which nucleates at higher temperature (−140° C.) and preempts the other cracks due to auto-nucleation (at −196° C.) from happening. The scratch must be deeper and sharper than any defect in the material. The critical stress intensity level is reached at the scratch first. A single crack was launched successfully without controlling the temperature very precisely by lowering the wafer slowly in the LN2 Dewar. However, it is expected that controlling the crack parameters, such as scratch depth and temperature will yield more control over the crack path.
Single atomic plane cleavage was obtained over a limited area (>1 cm2) in spite of scratching by hand. A more precise scratch is obtained with a nano-indenter. In fact the nano-indenter can produce atomically smooth vertical surfaces [15,16,17] if the scratch is oriented along the <110> direction. Scratching with a nano-indenter produces a sub-surface damage known as a median crack under the plastic deformation which is seen on the surface, with a depth that varies as the load to the power2/3 [16]. A median crack size between 20 and 40 μm is desired. This requires a scratching load on GaAs between 70 and 200 mN using a diamond tip [16 see FIG. 8 on page 119]. A typical nano-indenter utilizes a Berkowich tip with a radius of 2.7 μm.
A median crack with a precisely controlled depth is required to obtain vertical single atomic plane cleavage. If the median crack is too small, catastrophic failure and uncontrolled crack propagation ensues. When the median crack reaches a critical depth, the fracture is controlled and the quality of the cleaved surface is greatly improved. This cannot be obtained by scratching with hand. The scratching load must be controlled very precisely within a narrow range in order to yield a median crack with the desired depth and avoid chipping [16]. If the load is below this range then only plastic deformation ensues. If it exceeds this range then chipping of the substrate occurs. The tip radius is also very important as it determines the shear stresses that cause dislocations and influences the depth of the median crack. The nano-indenter provides just enough energy to create the precursor median crack. The polyimide will initiate and propagate the precursor crack due to strain energy. The initiation is very difficult to control as the energy input to the system must be precisely controlled knowing with great accuracy the precursor crack. A thick polyimide initiated several cracks simultaneously from many nucleation sites and the cleavage was not controllable. This could circumvent the median crack. Therefore, it is important to know how the polyimide applies the load on the GaAs, in order to avoid the effort spent controlling the vertical scratch very precisely being wasted by the polyimide starting cracks at different locations. We were able to influence the cleavage and reduce the number of cracks by choosing the right thickness of polyimide. The thinner the polyimide, the thinner is the lifted-off thickness. The thickness of polyimide (50-100 μm) yields a depth of cleavage which coincides with the thickness of the epi-layer and satisfies the specific power ratio requirement.
There is no doubt that the crack started from the scratch and propagated vertically downward, stopped and turned horizontally, as can be seen from
The velocity of crack propagation also influences the quality of the cleaved surface. Cracks in brittle materials typically propagate at speeds ˜1-2 Km/sec which are up to 35% of the Rayleigh wave speed. In order to obtain single atomic plane cleavage it is necessary to slow down the speed of the crack. Any scribing machine can be used as long as it provides the desired load range on GaAs between 50 and 200 mN, where the load can be monitored accurately during scratching within a couple of milli-Newtons, and the tip radius and geometry can be precisely characterized. This allows the use of automated scribing machines that are used routinely in semiconductor wafer dicing, which lowers the cost of the scratching operation significantly.
The crack starts propagating from the scratch on the backside of the wafer, as illustrated schematically in
The lower-CTE substrate is made of Kapton which is bonded to the epi-side and serves as the permanent carrier of the thin epi-layer after lift-off. The wafer is bonded to a high-CTE polyimide substrate on the opposite side away from the epi. The polyimide wafer has a CTE of 54 ppm/° C. and thickness of about 250 μm, which is optimized to deliver the maximum bending stresses for a typical semiconductor wafer about 175-200 μm used for PV applications. The thickness of the polyimide substrate can be adjusted arbitrarily and continuously to deliver the maximum punch if thicker semiconductor wafers are used because the polyimide substrate is sliced from ingot. The high-CTE polyimide induces the lift-off. The wafers are bonded using adhesive layers. The bond to Kapton is permanent, whereas the bond to the high-CTE polyimide substrate is temporary and is dissolved after each lift-off so that the high-CTE polyimide substrate can be reused to lift-off another epi-layer. It is intended that the wafers separate at the epi/wafer interface so that the epi-layer remains permanently attached to the Kapton, as shown schematically in
The process of lift-off starts by laminating the Ge or GaAs wafer to Kapton and polyimide wafer and then heating to a temperature between 150 and 190° C. for about an hour to activate and cure the adhesives. The lamination using a hot roller takes only 30 seconds and can be repeated a few times to strengthen the bond. After bonding, the wafers are ready for lift-off. The temperature is lowered by introducing the bonded wafers in a Dewar of liquid nitrogen at −196° C. Lift-off happens naturally as the wafers reach a certain temperature without applying any external force or pressure. The wafer cleaves spontaneously at a plane parallel to the bond interface when the temperature is reached. An audible crack is heard and the film snaps right off in a fraction of a second. The entire process takes only a couple of minutes. This process is called dry epitaxial lift-off or DELO to differentiate it from other techniques that require ion implantation, high-temperature annealing or wet etching. DELO also applies to non-epitaxially grown solar cells and to any circuit layer in general. The polyimide substrate can cleave a layer of a certain thickness from a semiconductor wafer regardless of whether it contains an epi-layer or an active electronic circuit or not. Kapton can cleave a layer on its own; however, the crack may propagate through the majority of the thickness of the semiconductor wafer. When a polyimide wafer with a higher CTE is bonded temporarily on the backside opposite the Kapton, the crack is confined near the Kapton, thus limiting the depth which the crack traverses through the wafer.
The polyimide wafer has a high CTE of 54 ppm/° C. which lowers the temperature drop necessary for lift-off. The polyimide is tough and can withstand temperatures from 300° C. down to −196° C. The adhesive is applied uniformly. The surface of the polyimide wafer does not have to be polished. It can be ground or lapped and still supports the epi-layer over the entire 4″ diameter. The front side of the solar cell can be processed on the Kapton after lift-off. The high-CTE polyimide substrate is described in U.S. Pat. Nos. 6,563,998; 6,807,328; 7,512,297; and 8,107,777. A polished 4″ diameter polyimide wafer 250-500 μm thick is shown in
From biaxial stress and beam theory the maximum bending stress that a polyimide substrate applies on the GaAs wafer at the onset of crack initiation is about 66-86 MPa depending on the thicknesses of GaAs and polyimide substrate, as can be seen in
Under the right initial conditions a region with compressive stress can stop a crack and even guide it. In GaAs the preferred cleavage plane is <110>. So if a crack encounters a barrier along the <110> direction because it cannot penetrate a compressive zone then it will simply turn 90° and continue its path along the interface. According to Griffith's criterion which forms the basis for fracture mechanics, the initial elastic strain energy is equal to the energies of the two surfaces created after the crack has propagated plus the residual strain energy. This is used to predict the depth of the cleavage plane as shown in the Appendix.
It is well known that one can induce a vertical crack to propagate through the thickness of the wafer by scratching the surface and cleaving manually. This is routinely used to cleave mirror-like facets of laser diodes. If a silicon wafer unscratched is bonded to a polyimide wafer on the back side and introduced gently in a container of liquid nitrogen and left alone to reach thermal equilibrium at −196° C. then it will curl and start cracking audibly within a couple of minutes. A GaAs or Ge wafer would start cracking at −140° C. because it is more fragile than Si. If the polyimide is too thick, i.e. if the strain energy is too high, then the base wafer will shatter into many small pieces and a contiguous layer of semiconductor will remain stuck to the polyimide. If liquid nitrogen is poured on it then it will shatter instantaneously due to the non-uniform thermal gradients. This is auto-initiation. However, if the thickness of the polyimide is just right and the backside of the wafer is scratched with the right depth and tip radius then the base wafer will separate in one piece. We compete with auto-initiation by scratching the wafer at a prescribed location so that the crack starts propagating under the scratch at a higher temperature before all the other auto-initiated cracks have the chance to start, thus, preempting all the other cracks. The polyimide substrate opens the crack due to tensile stress by bending, which is the preferred mode of opening. It is preferable to avoid crack propagation through the thickness of the wafer and to confine the crack near the surface where it started. Thus, the polyimide wafer must be used only to initiate the crack on the opposite side and a second mechanism should be used to stop it before it travels through the wafer. A compressively strained pseudomorphic layer, such as InGaAs, grown under the epi-layer can be used effectively to stop the crack within a few microns from where it started, as shown in
Ideally the wafer is scratched near the edge parallel to the flat to minimize wafer area loss, as shown in
After transfer, the anti-reflective coating (ARC) and wire grid electrode are deposited on the front side of the solar cell on the Kapton. The base semiconductor wafer is recycled by polishing the surface to remove any remains of the release layer, and is ready for the next epitaxial growth thereby completing the manufacturing cycle.
The two main design parameters of DELO are the thicknesses of the polyimide and semiconductor wafer. The stresses depend on the elastic modulus of the semiconductor material and on the ratios of the elastic moduli and thicknesses of the wafers, as can be seen from equations (6-9) in the Appendix. The radius of curvature depends on the thickness of the polyimide substrate and on the ratios of the elastic moduli and thicknesses of the wafers, as can be seen from equation (5).
GaAs (110) wafers yield smoother, thinner and more uniform cleavage with less surface variation than (100) wafers. However, solar cell manufacturers are reluctant to grow on (110) wafers because most of the III-V industry is built on (100) wafers, albeit with some deviation up to a few degrees.
{100} planes and {110} planes are orthogonal to each other. Thus a {110} plane is obtained by rotating a {100} plane by 90° about a <110> axis. Therefore, tilting the (100) plane by 15° toward the (111)A plane brings it closer to the {110} plane, which makes it easier to cleave than a perfectly aligned (100) wafer.
Embedded Layer with Lower Fracture Toughness
As it was observed that a (110) wafer cleaved much smoother and thinner than a (100) wafer, because it has lower fracture toughness, this leads to the concept of embedding a nano-layer of lower fracture toughness, such as GaAs (110), at the desired depth in a (100) wafer. It is known that the (110) orientation in GaAs is the preferred cleavage plane because it has lower fracture toughness. The concept is illustrated in
a and
A subset of {100} planes and {110} planes make an angle of 45° with respect to each other. For example, the (101) plane passing through Arsenic atoms A and C in
Besides shifting the plane by one quarter of a unit cell the atoms must be dragged by an additional amount of {1−1/√{square root over (2)}}≈0.3 to coincide the lattices, as shown in
A (100) GaAs surface is naturally biased to grow a (100) epi-layer. However, if the As atoms are placed at locations A and B in
However, the problem is that the location of the As atoms cannot be controlled precisely during epitaxial growth. It is very difficult to grow such a layer using current MBE or MOCVD equipment. Even techniques such as Atomic Layer Epitaxy where one atomic layer is grown at a time, for example only Ga atoms first then As atoms next, cannot afford the level of control required to write single or groups of atoms on an epitaxial surface. Epitaxial growth is very sensitive to the group V/group III ratio. A certain ratio must be maintained to obtain optimal growth conditions. GaAs surfaces are generally described as either Ga-rich or As-rich. As-rich surfaces are easier to grow on because the sticking coefficient of As atoms on As-rich surfaces is always nearly 100%. However, the delicate balance comes in when the surface is Ga-rich.
It is worth noting that this concept is different from the porous silicon “weak” layer approach spear headed by IMEC and others because there is no vertical force to separate the epi-layer. The embedded layer is weaker than the (100) GaAs substrate in the sense that it has a slightly lower fracture toughness but it is still a solid epitaxially grown layer which forms the basis for the thick solar cell grown on top of it.
The cost of fabricating the front side of space solar cells accounts for 30% of the cost of the cell. Thus, the cost of metallization must be reduced in order to meet the target cost requirement of $50/W. Alternative cheaper techniques can be used to write the metal lines and bus bar because a solar cell for terrestrial applications does not have to last as long as 15 years as in space. Ag is the main metal used for III-V solar cells. A very thin Cr layer is used to enhance the adhesion of Ag to GaAs and the Ag is encapsulated on both sides with a thin layer of Au which acts as barrier and prevents diffusion of the Ag into the GaAs. The metals are patterned using a lift-off process. The wafer is covered with a patterned photoresist and the metal is deposited usually by evaporation. Subsequently, the residual photoresist is developed leaving the metal lines on the surface. No transparent conductive oxide is needed because Ag has good lateral conductivity. The metal grid lines are typically 11 μm wide and 5 μm high. Screen printing is an inexpensive technology which is used for interconnecting silicon solar cells but does not have the required resolution either vertically or laterally.
Aerosol jet printing, produced by Optomec in Albuquerque N. Mex., is a cost-effective maskless non-contact direct-write metallization technique which has been used for high efficiency solar cells [18]. It uses additive technology and inks containing metallic nano-particles to build up metal lines with widths below 10 μm layer by layer. It is applied at low temperature and is particularly suited for non-planar surfaces and flexible substrates which present challenges regarding stretching and potential cracking of the metal lines. The flexible substrate is held flat on a vacuum chuck while writing. It is an emerging alternative to traditional photolithography and has much higher resolution than inkjet. A pulsed flash lamp is used to fuse the metallic nanoparticles and cure the inks similar to rapid thermal annealing. A Novacentrix flash curing unit is used in conjunction with aerosol jet printing for roll-to-roll processing.
The front side of the solar cell is processed at a temperature that does not exceed 200° C. Good efficiency and fill factor were obtained from solar cells processed on flexible substrates without loss in performance compared to the original substrates [see FIG. 7 in 19].
Electron imaging tools such as SEM, TEM, X-ray diffractometry and cathodo-luminescence (CL) and dissecting tools such as focused ion-beam milling (FIB) can be used to study the composition of layers. SEM can be used to examine the FIB cross-sections of median cracks. TEM can be used to reveal microscopic defects in the layers.
The GaAs wafer can be scratched with a nano-indenter, such as the one made by CSM in Peseux, Switzerland, or by Hysitron in Minneapolis, Minn., or by Nanovea in Irvine, Calif. The applied load can be correlated to the median crack size while avoiding the creation of radial and lateral cracks, which are responsible for chipping. A knoop type indenter, such as Vickers, rather than a conical tip can be used as it yields better control over the crack in brittle materials. Different tip radii can be used. The tip radius can be measured and the size of the defect can be calibrated vs radius. Scratches can be made along different crystallographic directions. The goal is to calibrate the depth of the median crack vs load and to observe the effect of the crystallographic orientation. FIB can be used to dissect parallel and perpendicular to the scratches.
A more precise control over the temperature may result in better control over the propagation of the crack. The wafer is instrumented with a thermocouple which measures the temperature as it is lowered in the LN2 jar.
When an unmetallized GaAs wafer is bonded to Kapton, the adhesive holds its grip in LN2 and the crack propagates in the GaAs wafer. However, actual solar cells are capped with a blanket metal layer on top of the epi-layer, which forms the backside contact after lift-off. The adhesive layer is in contact with the metal layer. The adhesion to metal is improved to prevent delamination at the metal/epi interface.
A process for achieving single atomic plane cleavage wafer scale and a cost-effective metallization scheme for processing the front side of a solar cell is presented. The effects of thermal stresses and crack propagation on the performance of the solar cell are minimized. Roll-to-roll processing, i.e. simultaneous cleavage of several cells mounted on one large sheet of Kapton, and reclaim of the substrates. Several cells are interconnected using copper plating to produce flexible panels with output power that exceeds 20 W. This lift-off technology has applications for space and terrestrial solar cells and is qualified for space.
A GaAs wafer with IMM3J epi-layer capped with a metal layer is bonded face down to Kapton substrate and trimmed. After lift-off a typical 4″ wafer is diced to yield two trapezoidal solar cells for space applications having dimensions of approximately 4 cm×6.6 cm (area 26.6 cm2). Several cells are integrated on a common blanket polyimide sheet and interconnected, as shown schematically in
The thin encapsulated solar cell structure is shown schematically in
Both sides of the epi-layer can be contacted from the top of the wafer, as shown schematically in
A solar cell was encapsulated with Imiclear (previously Corin® XLS) layer available from Hybrid Plastics, Inc in Hattiesburg, Miss. ImiClear is a spray-on fluorinated polyimide nano-composite, which was developed to replace the cover glass for space applications. It has the combination of transparency and UV resistance and ruggedness that make it suitable for space applications. It can be sprayed-on at room temperature to a thickness between 25 and 50 μm and does not perturb the balance of the structure. It is applied at room temperature and therefore does not exert any thermal stress on the thin solar cell. This provides a process for fabricating a thin flexible solar cell, interconnecting the front and backsides, integrating several cells on a common blanket polyimide sheet, and encapsulating, which applies to both inverted and non-inverted cells.
It is necessary to flatten the structure of a multi-layer solar cell over a wide temperature range to encompass temperature swings that are encountered on orbit. ANSYS simulation was used to balance the 8-layer solar cell structure of
Controlling the thickness of the spray-on polyimide cover layer within a fraction of a mil is crucial as it affects the transparency and degree of protection of the cell. A change in thickness of only half of a mil (12.5 μm) causes a shift in the UV cut-off wavelength of 15 nm, which can be critical for the performance of the cell. The thickness of spray-on polyimide is controlled precisely by concentration and duration of the spray. Furthermore, the value of the CTE of the blanket polyimide layer required to stress-balance the structure depends on the thickness of the ImiClear cover layer. The 8-layer solar cell structure can be balanced using Novastrat® variable-CTE polyimide, which is available commercially from Nexolve, Inc which is a division of Mantech SRS in Huntsville, Ala.
A typical triple junction solar cell for space applications produces about 2.2 V and generates a current of 0.45 A at the Maximum Power Point (MPPT), which corresponds to a power output of about 1 W. Thus, a blanket made of one hundred thousand cells having an area of 300 m2 produces a total power of 100 KW. At least 100 cells are connected in series to produce a voltage >200 V, i.e. 1000 cells are connected in parallel.
The lifted-off solar cells are integrated on a common blanket polyimide sheet and interconnected in series and parallel using copper electroplating. The process starts by bonding the epi-wafer to Kapton® polyimide substrate in a clean room and then lifting-off the epi-layer, as described above. After lift-off the thin IMM structures are processed into fully functional solar cells and a new IMM structure is grown on the original GaAs wafer. Anti-reflection coating (ARC) is deposited and metal lines are patterned on the front side of the IMM cell on Kapton to create metal landing pads. A small volume (10 μm×10 μm×10 μm) is etched at the point of interconnect on the edge of the epi-layer as shown schematically in
The initial bonding of the epi-layer to Kapton by lamination and the electroplating after assembly are done in a clean room. A standard sheet of polyimide (8½″×11″) accommodates 2 rows of 6 cells (6.6 cm×4 cm each), i.e. 6 series and 2 parallel connections. Automated equipment can be used to process in a roll to roll format using 1,000 foot×12″ rolls of polyimide.
The process starts by coating all surfaces with photoresist, exposing through a mask, and developing leaving all surfaces covered except those that will be coated with dielectric. The samples are then coated with a thin layer of dielectric using Atomic Layer Deposition (ALD), which is particularly effective at coating side walls and sharp edges. All the surfaces are coated with dielectric, including the photoresist. After the photoresist is dissolved the remaining dielectric is shown in Step 2. Subsequently, a second coat of photoresist is applied and patterned, leaving only some areas exposed for electroless Cu plating. Submerging the samples in electroless Cu coats the entire assembly with a thin layer of Cu. Dissolving the second photoresist and the overlying Cu, a thin Cu layer remains over the dielectric in the areas shown in Step 3. This step creates a continuous electrical path from one cell to the next.
The assembly is then coated with a third layer of photoresist, exposed through a mask and developed; leaving exposed the surfaces that will be electroplated. The samples are submerged in an electroplating bath and Cu is plated to the desired thickness in the areas shown in Step 4. The remaining photoresist is finally removed. Electroplating allows much tighter spacing in the placement of the cells compared to other interconnect methods and a much smaller area of the epi-layer needs to be etched away. The IMM cell would not survive immersion in a plating bath unless it is protected by photoresist.
Step 1 (right column) illustrates the concept of connecting two neighboring cells in parallel, which is slightly different from the series connection. There is no need for dielectric coating at the beginning because the two connected metals are at the same level. Electroless Cu is deposited directly after patterning to connect the back side metals, as shown in Step 2, which is followed by electroplating copper by applying a potential to the interconnected back side metal layers in step 3. This is followed by patterning the areas to be covered by a dielectric layer and dielectric deposition using ALD in step 4. The parallel connection requires a second electroless Cu deposition, as shown in Step 5. Finally, the cells are patterned and electroplated one more time, as shown in Step 6. These steps require photoresist deposition, patterning and removal three times as in the series connection. The completed and interconnected cells will be encapsulated using spray-on polyimide.
Wide band gap materials, such as GaN and SiC, are advantageous for high power electronics because they can operate at high switching speeds, voltages and temperatures [25]. GaN devices fabricated on native substrates achieve better performance due to lower defect densities. Vertical GaN LEDs fabricated on GaN substrates achieve higher brightness and can handle higher current densities and yield chips with smaller footprint compared to conventional GaN LEDs fabricated on other substrates because the chip can be contacted from both sides. Another advantage of growing on GaN substrate is the flexible choice of crystallographic plane, which yields improved LED performance [26]. The lack of good quality bulk GaN substrates at a reasonable price is hampering the development of vertical devices. The largest diameter GaN substrate is 2″ and a premium GaN wafer costs over $3,000. The largest commercially available m-plane GaN substrate is only 10 mm×5 mm. A premium 4″ 4H—SiC wafer currently costs about $1000, while a premium 6″ 4H—SiC wafer sells for over $2,500. Devices are made in epitaxial layers. To grow an epi-layer, a smooth epi-ready surface free of subsurface damage is required. However, these materials are extremely hard and difficult to machine (Mohs hardness of 9). Conventional lapping and polishing of a GaN substrate takes between 15 and 20 hours using fine grit diamond particles [27], depending on the amount of material removed, and leaves the surface with scratches that are visible under the microscope and bowed. The typical average surface roughness is on the order of 1 nm and the grinding marks are about 5-10 nm deep. This is about 10 times rougher than softer materials, like sapphire and GaAs. For this reason, chemical-mechanical polishing (CMP) is needed to smooth the surface further for epitaxial growth. However, CMP is not very effective on these materials because the Ga-face is chemically very stable [28]. It can take up to 150 hours of CMP time [29] to get rid of all the grinding marks and remove all the subsurface damage. Lapping/polishing/CMP of a 2″ wafer currently costs $500 or equivalently about 20% of the cost of the wafer. Thus, it is necessary to reduce the cost of surface preparation of epi-ready GaN and SiC substrates.
The wafers are often thinned from the backside after device fabrication by either lapping or grinding from an original thickness of 400 or 500 μm down to 100 μm to separate the laser bars [28] or to improve heat dissipation for power applications [30]. However, a wafer breaking rate of about 30% has been reported [28]. Thus, 80% to 90% of the material is wasted. These crystals are too expensive to be ground away to dust. Furthermore, thinning produces a strong bow and warpage [31]. Reduction of wafer bow is necessary to improve the yield and facilitate facet cleavage. Wafers with pre-fabricated devices are covered with UV curable tape on the front side prior to grinding to protect the devices and prevent contamination with grinding fluids and debris.
A rapid thinning technique by lifting-off a 20-70 μm thick layer from the surface is presented, which can be applied to the front side of the wafer, and independently to the backside regardless of the starting surface condition, i.e. as sliced from boule. A crack propagates across a 4″ wafer within a fraction of a second and leaves the surface shiny with an average roughness<1 nm. The surface can be CMP'ed further down to 0.1 nm to make it epi-ready. The savings in lapping and polishing add up to 60%, when this technique is incorporated in the crystal manufacturing process. There are additional savings in CMP time because this technique is expected to yield less subsurface damage as it does not use abrasives. This technology also has application for backside thinning where the savings are even larger because the cleaved surface does not need further polishing post lift-off. Furthermore, the present rapid thinning technique does not produce any bow or warpage and does not require taping of the front side during backside thinning.
The growth of LEDs on bulk GaN substrates is critical to the development of Solid State Lighting. GaN has outstanding properties for switching at high frequencies, while SiC is best known for its high temperature abilities. They are the most prominent candidates to replace Si for power applications. At the present time, SiC is considered to offer the best trade-off between properties and commercial maturity. Premium quality 150 mm 4H—SiC wafers are commercially available. Nevertheless, it is generally agreed upon that both materials have tremendous potential [25].
Currently, state-of-the-art GaN substrates have defect densities on the order of 106 cm−2. This can be reduced by at least three orders of magnitude if the GaN layers are grown on GaN substrates. Epitaxy on the native substrate material eliminates all problems related to hetero-epitaxy, such as defects and bow due to lattice and coefficient of thermal expansion (CTE) mismatch. In fact the CTE mismatch was exploited to separate a 100 μm-500 μm thick GaN layer from it growth sapphire substrate by propagating horizontal cracks parallel to the interface [27,32,33]. The threading dislocations also bent horizontally in the direction of the cracks.
Diamond scribing and cleavage of GaN substrates are routinely used for the fabrication of edge-emitting laser diode facets [28]. It is very important to produce vertical flat surfaces that act as mirrors for this application. The stress depends on the dimensions of the wafer and is inversely proportional to the thickness squared. For this reason GaN wafers must be thinned to about 100 μm or less before cleavage [10]. This method has not been widely adopted for GaN laser diodes grown on sapphire substrates, however, because sapphire has many planes that have approximately equal cleavage strength. These planes lie within a small angular distance. Therefore, any perturbation, such as slight misalignment of the applied pressure redirects the fracture from one plane to another resulting in a jagged facet [34]. It is very difficult to cleave a 200 μm thick GaN substrate, whereas a 400 μm thick SiC wafer cleaves readily, and has vertical cleavage planes. Wafer thinning to about 100 μm has become a standard procedure before dicing. All the techniques currently used require thinning of the wafer prior to cleaving.
Completed device wafers are routinely thinned before separating the individual chips. It is necessary to thin the wafer for vertical devices because the current travels through the thickness of the wafer. The substrate contributes about 70% of the overall diode resistance. The thermal behavior of the chip is also improved, which leads to a cooler junction. Thinning the wafer from the standard 350 μm to below 150 μm leads to significant improvements of the electrical as well as thermal resistances of SiC diodes operating at 650 V [30]. However, the damage to the backside due to grinding combined with the reduced thickness lead to significant increase in wafer bow. For example, the starting bow on a typical SiC 2″ wafer before grinding is <20 um, whereas after grinding it jumps to 1.5-1.8 mm, which is a major drawback for backside thinning [31].
Dislocation densities and subsurface damage appear as dark lines in Cathodo-Luminescence (CL). The quality of a cleaved laser diode facet correlates with low crystal defect density [35]. Lapping and polishing produce a sub-surface damaged layer which is deeper than the surface scratches, which are typically about 5-10 nm deep. It took 150 hours of CMP time to remove all the dark lines observed in the CL image of GaN substrate [29]. Overall, 2.5 μm of material was removed to obtain the scratch-free surface and get rid of all the sub-surface damage [29].
A state-of-the-art commercial epi-ready 2″ GaN or 4″ 4H—SiC substrate exhibits grinding marks which are a few nanometers deep, as measured by AFM, as shown in
A new method of thinning a semiconductor wafer by driving a horizontal crack parallel to the surface at a certain depth into the substrate, which is also known as spalling, is presented. A polyimide tape is laminated to one face of a semiconductor wafer (either smooth or rough) and lowered slowly in liquid nitrogen. Within 30 seconds an audible crack sound is heard and a layer is separated from the wafer instantly, which remains stuck to the polyimide. It takes an hour to cure the adhesive, but the cleavage takes a fraction of a second. The cleavage transfers a layer about 50 μm thick to the polyimide substrate which is used as the stressor layer. Kapton® Polyimide sheet is used, which is manufactured by DuPont. The crack is driven purely by the thermal stresses due to the CTE difference between GaN or SiC (4-5.5×10−6/° C.) and polyimide (16×10−6/° C.) across a temperature drop of 300° C. without the necessity for any external mechanical force or tool to aid crack propagation. The crack can start either on the surface or the side of the wafer, but propagates at a depth which depends on the thickness ratio and the elastic modulus ratio of the polyimide/GaN. It is independent of the dimensions of the wafers. A 2″ wafer will cleave at the same depth as a 4″ wafer, as long as the thickness ratio of polyimide to GaN is the same. Unlike manual cleavage where the stress depends on the dimensions of the wafer and the skills of the operator, cleavage by polyimide is a lot more uniform. A stress of about 20 MPa is needed to initiate a crack in GaAs. Stresses on the order of up to 1 GPa may be needed to cleave GaN. The polyimide is capable of exerting the necessary stress by choosing the right thickness of polyimide. Kapton comes in sheets of 25 μm increments. So it is easy to choose the desired thickness.
About 700 μm of polyimide cleaves about 50 μm off a 400 μm SiC wafer. The thickness of the lifted-off layer can be controlled from 10 to 100 μm by controlling the thickness of polyimide. The cleaved thickness can be calculated by equating the elastic strain energies of the system before and after crack propagation, according to the Griffith criterion. The initial elastic strain energy at full thickness is equal to the residual strain energy in the thin SiC/Kapton plus the energies of the two newly created surfaces. The surface energy is a known material property.
Smooth cleavage was obtained for both polar (c) and non-polar (m) planes, and 4″ wafers have been cleaved. We have laminated Kapton to a cleaved surface and cleaved the second time. The hexagonal atomic structure of GaN/SiC cleaves even better than the cubic FCC zinc blende structure of GaAs.
Currently, about 80-90% of the GaN and SiC crystals are thrown away or ground to dust in order to satisfy the thinning requirement for cleavage, as discussed above. This is a huge waste because these materials are very expensive to produce. By contrast, the polyimide is able to cleave 50 μm off a 400 μm SiC wafer without prior thinning. Furthermore, the lifted-off material is not lost. It is still intact single crystal sitting on the Kapton and can be reclaimed.
Layers have been peeled off GaN and 4H—SiC substrates. The starting surface of the wafer can be as-cut from boule. This technique has been used to lift III-V epitaxial layers off GaAs substrates to fabricate flexible high efficiency solar cells, and reused the substrate multiple times [36]. The wafer is recovered in one piece and can be reused to grow epitaxial layers several times. Similarly, epitaxial layers of GaN can be lifted off any substrate. The layer peel-off process is done wafer scale, and requires minimal investment in equipment. The process can be scaled up II to process hundreds of wafers simultaneously with the use of automated roll-to-roll processes.
The thermal stresses cause bending of the composite structure. The organic adhesive has enough shear strength to transmit the force to bend the wafer and holds its grip in LN2.
The goal is to do CMP directly on the surface as-cleaved. It is desired to avoid lapping and polishing if possible because that would destroy the smoothness of the surface and re-introduce subsurface damage. The grinding marks will return after lapping. If the CMP is successful, then the lapping and polishing and some CMP time will have been saved, because the surface is expected to have less sub-surface damage than a lapped and polished surface. These savings amount to 60% of the polishing costs. The goal is to reduce the time and cost of lapping and polishing and possibly CMP of GaN and SiC substrates in the process of making the surface epi-ready.
It is desired to thin the wafer using only the polyimide without lapping or grinding, and to remove only the amount of material necessary for the application. Multiple layers can be lifted off the same surface with the Kapton. For the front side it is only needed to lift-off about 10-20 μm once. For the backside we can lift-off several times to reach the desired final thickness and there would be no need for lapping or polishing afterward because major roughness is not an issue for the back side. Therefore, this process saves the grinding time and does not produce any warpage. Rapid thinning reduces the cost of manufacturing GaN and SiC substrates. This technology also applies to large size wafers.
The main goal will be to reduce the surface variation to about 20 μm, which is equivalent to the TTV on premium 4H-4″ SiC wafers. We want to obtain the smoothest surface starting from the roughest surface while minimizing abrasive machining. The height variation is due to the convergence of multiple crack fronts. Cracks start simultaneously from several points on the sample as soon as it is lowered in the LN2 Dewar. The key to obtain a smooth cleavage is to launch a single crack. A crack propagates across a 4″ diameter wafer in less than 0.1 milli-second at a speed of Km/sec which is about 35% of the Rayleigh wave speed. In order to control the crack it is necessary to slow it down [16]. A fast camera that has a time resolution of 0.1 μ-sec can be used to grab at least 1000 frames to image crack nucleation and propagation, as this would give us insight on how to control the crack.
It is very important to discover whether crack propagation yields any subsurface damage. A crack has tendency to branch out and travel in different directions. However, it is not known whether a crack would produce lateral damage along its path. The extent of post lift-off CMP needed depends on such damage. Contiguous layers have been cleaved off 4″ wafers and recovered the base wafer in one piece.
Another issue which is equally important is the effect of defects and dislocations on the cleavage. It is believed that in order to obtain good cleavage, a low dislocation density is required [35] because the propagation of cracks is altered at dislocations. GaN has about two orders of magnitude higher dislocation density compared to other semiconductors, such as Si or GaAs.
The subsurface damage can be inspected using the optical microscope, AFM, SEM, TEM, FIB, Cathode Luminescence imaging (CL) and reflection high energy electron diffraction (RHEED). Dislocations act mainly as non-radiative recombination centers, hence, appear as dark spots and lines in CL images. Therefore, the objectives will be to reduce the height variations during lift-off and to measure subsurface damage using CL in order to reduce CMP time. Another objective will be to improve the uniformity of bonding between Kapton and GaN by applying uniform pressure using a hot press.
A sheet of polyimide about 50 μm thick is bonded to a semiconductor wafer, either GaAs with orientation (110) 370 μm thick or Si with orientation (111) 200 μm thick, using a layer of organic adhesive about 25 μm thick in between. The thickness of polyimide can be increased by laminating several layers. The structure is modeled as a two-layer because the organic adhesive has physical and thermal properties similar to polyimide. Layer 1 refers to the semiconductor material, either Si, GaAs, SiC or GaN and layer 2 is the lumped polyimide/adhesive.
There are two components of stresses in each material: axial stresses which are uniform across the cross-section, and bending stresses which vary linearly across the cross-section. These are denoted by σa1, σa2, σb1 and σb2, respectively, where σb1 and σb2 are the maximum bending stresses at the boundaries. These stresses give rise to the forces F1 and F2, and the moments M1 and M2, acting on each element, as shown in
So the problem consists of 4 unknowns and can be stated either in terms of the stresses σa1, σa2, σb1 and σb2, or equivalently in terms of the forces and moments F1, F2, M1 and M2.
Therefore, 4 linear equations are needed to solve for the 4 unknowns. These are the balance of axial forces ΣFx=0, which yields F1=F2=F; the total moment must also vanish because there are no external forces acting on the bi-layer, ΣM=0; the geometric compatibility which relates the bending strains in both materials εb1 and εb2, to their relative thicknesses h1 and h2 due to planar deformation, which can be inferred from
σa1h1=σa2h2 (1)
M
1
+M
2
=F(h1+h2)/2 (2)
εa1/h1=εa2/h2=1/R (3)
εa1+εb1+εa2+εb2=(α2−α1)ΔT (4)
The solution of these 4 equations yields all the pertinent parameters including the stresses, strains, radius of curvature, forces and moments acting on the structure. We define two parameters E and h, which are the ratios of E1/E2 and h1/h2, respectively. The curvature 1/R is given by equation (5).
This is the same as equation (3) in [19]. The axial and bending stresses are given by
Usually, the bending stresses in the GaAs or Si, σa1, are dominant followed by the axial stresses in the polyimide σb2. The bending stresses are related to the radius of curvature R as
σb1=E1h1/2R and σb2=E2h2/2R (10)
Thus, the bending stresses are directly proportional to the curvature 1/R.
a plots the curvature after lift-off for GaAs thickness h1=20 μm and ΔT=300° C. vs h′=h2/h1 which is the ratio of the thickness of polyimide to the thickness of GaAs. It is seen that the curvature peaks (1/R=22.5 m−1, R=4.4 cm) at a ratio h′=3.75, i.e. h2=75 μm. This is verified experimentally as shown in
The layers shrink in both in-plane directions relative to each other. This gives rise to a bi-axial state of stress σx=σy=(σa1−σb1), as shown in
GaAs and Si are crystalline materials and therefore, have different properties along different crystallographic orientations. In particular, the elastic modulus varies up to 65% depending on the orientation. For example Young's modulus for
GaAs <100> E=86 GPa
GaAs <110> E=122 GPa
GaAs <111> E=142 GPa
whereas for Si
Si <100> E=130 GPa
Si <110> E=169 GPa
Si <111> E=188 GPa
These values act along the direction of the respective vectors, rather than in the plane. Furthermore, the (110) plane is known to be the preferred cleavage plane in GaAs, whereas (111) is the preferred cleavage plane in silicon.
Since the GaAs wafer is thicker than (KIc/σY)2=1.3×10−8 m, where KIc is the fracture toughness=0.31-0.43 MPa(m)1/2 and σY is the yield stress=2.7 GPa, it is in plane strain. This means that there is no strain perpendicular to the surface of the wafer εz=0, but there must be vertical stress σz in order to cancel the effects of the in-plane stresses. Under these circumstances for bi-axial stress σx=σy=(σb1−σa1), the effective modulus Eeff=E/(1−ν−2ν2) where ν is Poisson's ratio. For uni-axial stress, Eeff=E/(1−ν2). For GaAs ν=0.31, while for Si ν=0.278. Thus, the effective modulus for GaAs (110) Eeff=250 GPa, while for Si (111) Eeff=300 GPa. For Kapton Eeff=5.8 GPa. Thus, the material becomes significantly stiffer for plane strain under bi-axial stress.
Since the effective moduli mentioned above act along the respective vector directions and the stresses act in the plane, it is important to know what crystallographic vectors exist in a particular wafer surface. It helps to examine the face centered cubic lattice structure of GaAs shown in
A (100) face contains both <100> and <110> vectors. The vectors make an angle of 45° with each other. The <110> vector is perpendicular to the flat.
A (110) face contains all three <100>, <110> and <111> types of vectors. The <100> and <110> vectors are orthogonal to each other, while the <111> vector makes an angle of 54.3° with the <100> vector. The <100> vector is perpendicular to the flat.
A (111) surface contains only a <110> vector.
Thus, all three principal semiconductor surfaces contain a <110> vector. This is illustrated in the diagrams of
The temperature drop AT is taken to be 300° C. and the difference in CTE between the polyimide and semiconductor is assumed to be 10×10−6/° C. for both GaAs and Si. To be more accurate the CTE of Si is 3×10−6/° C. while that of GaAs is 6×10−61° C. Thus, the driving thermal strain ΔαΔT=3×10−3.
GaAs (110) E1eff=250 GPa, h1=370 μm, polyimide E2eff=5.8 GPa, h2=150 μm E=E1eff/E2eff=42.88, h=h1/h2=2.467
Equations (5-9) yield:
1/(2R)=0.3 m−1→R=1.66 m (10)
Si (111) E1eff=300 GPa, h1=200 μm, polyimide E2eff=5.8 GPa, h2=150 μm E=E1eff/E2eff=51.3, h=h1/h2=1.333
Equations (5-9) yield:
1/(2R)=1 m−1→R=50 cm (11)
As can be seen from the two examples above, the bending stress σb1 is larger than the axial stress σa1 for both GaAs and Si, i.e. the outer half of the wafer is under tension. Thus, the stresses are not exactly as depicted in
According to the theory of fracture mechanics, the stress at the crack tip is described by the stress intensity factor, KI=σ√{square root over (πa)} where σ is the tensile stress responsible for opening of the crack (σb1−σa1) and a is the crack depth. The theory of fracture mechanics assumes that a crack already exists in the material. This corresponds to a static crack due to either a hand scratch or the median crack depth obtained after nano-indentation. When KI reaches a certain value known as the fracture toughness of the material KIc, which is a material property, under plane strain conditions, the crack starts to propagate. For GaAs (110) KIc=0.31 MPa(m)1/2 [15] and for Si (111) KIc=0.62 MPa(m)1/2 [6]. From these values of KIc and (σb1−σa1) above, the depth of the scratch that is necessary to propagate the crack can be calculated.
The crack opens vertically in pure mode I at the upper surface where the stress and KI are maximal, as shown in
A crack will propagate as long as KI and KII are outside the envelope given by (KI2+KII2)=KIc2, as shown in
Horizontal crack propagation is due to mixed mode stress at the crack tip. However, KIv and KIIv for the vertical crack are different from those for the horizontal crack KIh and KIIh. Nevertheless, they are related by the same driving force, which is the energy release rate G
G=(KIv2+KIIv2)/Eeff=(KIh2+KIIh2)/Eeff G=(KI2+KII2)/Ē (12)
Thus, as KIv approaches zero, the crack swerves by 90° and keeps going.
The total elastic strain energy Uo at the onset of crack propagation (a=0), which is proportional to the width b (into the page) times the length L, can be evaluated from the forces, moments and strains calculated above, as shown in
The lifted-off thickness d depends on the stress intensity factors KI and KII at the tip of the crack, which are function of the point of application of the force on the edge of the lifted-off layer (M1d/Fd) [2,3,4]. However, the Griffith criterion for crack advance circumvents the necessity to consider the actual physical mechanism of material separation at the crack tip in detail and eliminates the need to determine KI and KII exactly. The two approaches are equivalent, as can be seen from equation (12) above, and can be used interchangeably. After separation, the backside of the wafer of thickness (h1−d) is stress free and therefore has zero strain energy, whereas the lifted-off GaAs layer having thickness d, width b and length L, has residual strain energy Ud, as shown in
The initial energy Uo is the total energy build up needed to initiate the crack. Once the crack starts to propagate then the rate of decrease in energy, i.e. the energy expended per unit crack advance, G which is defined as dU/b·da, is pinned at G=2γs. Therefore,
U
o
−U
d=2Lbγs (13)
The energy Uo can be expressed in terms of the curvature 1/R and the stresses and strains, forces and moments given by equations (1-9) above and shown in
U
o=1/2{Fε1+Fε2+M1/R+M2/R}L (14)
U
d=1/2{Fdε1d+Fdε2d+M1d/Rd+M2d/Rd}L (15)
Equation (13), in conjunction with equations (14) and (15), can in principle be solved for the lifted-off thickness, d. However, this involves solving an equation to the 8th power (d8). Alternatively, the equation can be solved iteratively by trial and error by plugging in values of d until equation (13) is satisfied.
From the literature [15], the reported value of γs for GaAs (110) varies between 0.69 and 0.86 J/m2, while that of Si (111) varies between 1.022 and 1.14 J/m2 [6]. Thus, it is desired to find the thickness of GaAs which yields
(Uo−Ud)/Lb=2γs=1.38−1.72 J/m2 for GaAs, and (16)
(Uo−Ud)/Lb=2γs=2.044−2.28 J/m2 for Si (17)
Referring back to Example 1 above, GaAs (110) full thickness h1=370 μm, polyimide h2=150 μm.
U
o=(0.0328+3.467+0.193+0.0003)bL=3.693 bL (18)
U
o=1/2{Fε1+Fε2+M1/R+M2/R}L (14)
Equation (14) is placed directly under equation (18) in order to compare the magnitudes of the corresponding terms. The largest contributor to the elastic strain energy at full thickness by far is the axial stress in the polyimide (1/2Fε2). The Kapton is being stretched by 28.7×10−4, followed by bending in the GaAs, then compression in the GaAs, followed by a distant fourth, bending in the Kapton. The amount of energy that goes in bending the GaAs is 18× smaller than that goes in stretching the Kapton. The majority of the energy (93%) at full thickness is stored in the Kapton.
GaAs (110) thickness d=15 μm, polyimide h2=150 μm. Since a layer about 15 μm thick was cleaved in GaAs (110), this value is plugged in equation (15) to see whether it satisfies equation (16). Again, equation (15) is placed directly under equation (19) in order to compare the magnitudes of the corresponding terms. The radius of curvature Rd=4 cm.
U
15=(0.0412+0.1781+0.025+0.585)bL=0.8293bL (19)
U
d=1/2{Fdε1d+Fdε2d+M1d/Rd+M2d/Rd}L (15)
By contrast, the largest contributor to the elastic strain energy after lift-off is the bending in the polyimide (1/2M2d/Rd), which exceeds the stretching energy (1/2Fdε2d). The majority of the energy (92%) after lift-off is still stored in the Kapton. By subtracting equation (19) from (18) and comparing to (16) we obtain:
(Uo−U15)/Lb=2.864 J/m2 which is outside the range 1.38-1.72 J/m2 given by equation (16)
Therefore, a GaAs lifted-off thickness of 15 μm does not satisfy the energy release rate equation. Neither does a thickness of 25 μm. However, a thickness of 80 μm comes close.
GaAs (110) thickness d=80 μm, polyimide h2=150 μm. The radius of curvature R80=8.1 cm in liquid nitrogen.
U
80=(0.0435+1+0.815+0.125)bL=1.9835bL (20)
U
d=1/2{Fdε1d+Fdε2d+M1d/Rd+M2d/Rd}L (15)
The majority of the energy (56.7%) after lift-off is still stored in the Kapton, but the GaAs carries a significant portion of the strain. By subtracting equation (20) from (18) and comparing to (16):
(Uo−U80)/Lb=1.71 J/m2 which is within the range 1.38-1.72 J/m2. Thus, GaAs cleaves at a depth of 80 μm. This depth is within the compressive zone near the polyimide.
GaAs (110) E1eff=250 GPa, h1=370 μm, polyimide E2eff=5.8 GPa, h2=75 μm E=E1eff/E2eff=42.88, h=h1/h2=4.933.
1/(2R)=0.135 m−1→R=3.7 m in liquid nitrogen
Uo=(0.009+1.868+0.038+0.000007)bL=1.915bL (21)
U
o=1/2{Fε1+Fε2+M1/R+M2/R}L (14)
This is barely above 2γs=1.38-1.72 J/m2 for GaAs from equation (16) above. For this reason one layer of Kapton 75 μm thick is barely able to drive the crack across the GaAs wafer and needed to be scratched every step of the way to reach the edge. When another layer was laminated for a total thickness of 150 μm, the crack propagated readily. The majority of the elastic energy (97.5%) is stored in the Kapton.
Referring back to Example 2 above, Si (110) full thickness h1=200 μm, polyimide h2=150 μm. R=50 cm
U
o=(0.0433+2.987+0.397+0.0033)bL=3.43bL (22)
U
o=1/2{Fε1+Fε2+M1/R+M2/R}L (14)
The total energy in the 200 μm Si wafer is almost equal to that in the 370 μm thick GaAs wafer. This is due to the fact that Si is stiffer than GaAs. The largest contributor to the elastic strain energy at full thickness by far is still the axial stress in the polyimide (1/2Fε2). The Kapton is being stretched by 26.2×10−4, followed by bending in the GaAs, then compression in the GaAs, followed by a distant fourth, bending in the Kapton. The majority of the energy (87.2%) at full thickness is stored in the Kapton.
Si (110) h1=50 μm, polyimide h2=150 μm. R=5.25 cm
U
o=(0.027+0.45+0.56+0.294)bL=1.331bL (23)
U
d=1/2{Fdε1d+Fdε2d+M1d/Rd+M2d/Rd}L (15)
By subtracting equation (22) from (21) and comparing to (17):
(Uo−U50)/Lb=2.1 J/m2 which is within the range 2.044-2.28 J/m2. Thus, Si cleaves at a depth of 40-50 μm. This depth is within the compressive zone near the polyimide.
To summarize, the residual energy Ud/Lb must fall in the following ranges:
U
d
/Lb=U
o
/Lb−2γs=1.973-2.313 J/m2 for GaAs, and (24)
U
d
/Lb=U
o
/Lb−2γs=1.15-1.386 J/m2 for Si (25)
Thus, cleavage depths of 80-90 μm for GaAs and 40-50 μm for Si satisfy the energy release rate criterion, whereas lifted-off thicknesses of 15-25 μm for GaAs (110) and 25-40 μm for Si (111) were obtained experimentally. The discrepancy is due to inaccuracy in determining the effective modulus of elasticity.
Si (111) E1eff=300 GPa, h1=200 μm, polyimide E2eff=5.8 GPa, h2=75 μm E=EIeff/E2eff−51.3, h=h1/h2=2.667
U
o=(0.0126+1.827+0.074+0.000075)bL=1.914bL (26)
U
o=1/2{Fε1+Fε2+M1/R+M2/R}L (14)
This is below 2γs=2.044-2.28 J/m2 for Si from equation (17) above. For this reason one layer of Kapton 75 μm thick was not able to drive a crack across a Si wafer 200 μm thick even after scratching. A second layer of Kapton was laminated and the crack propagated readily. The total elastic energy stored in the Si wafer 200 μm thick is very close to that of GaAs wafer 370 μm thick, equation (21) in example 6 above, for a polyimide thickness of 75 μm. The majority of the elastic energy (95.4%) is stored in the Kapton, and it is stretched by a similar amount.
The results for GaAs and Si are summarized in
The specific power is calculated for an ImiClear thickness of 50 μm, a GaAs epi-layer thickness of 10 μm, Kapton thickness of 50 μm, and blanket polyimide sheet thickness of 50 μm as follows:
Thus, the specific power ratio=1000 W/kg under AM0.
Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only.
| Number | Date | Country | |
|---|---|---|---|
| 61935986 | Feb 2014 | US |
