Claims
- 1. A method of forming essentially uniform width deep trenches in a substrate by reactive ion etching, comprising of the steps of:
- forming an etch mask on the substrate that includes a first layer of material overlying the substrate that will react with or absorb the same ions which reactive ion etch the substrate, and forming a second layer of material on said first layer of material which will mask the ions used for reactive ion etching, and patterning said second layer to reveal portions of the first layer of materials and define the location and width of the trenches,
- reactive ion etching completely through the patterned exposed first layer of material and reactive ion etching the substrate therebelow to form the trenches in the substrate,
- whereby the exposed first layer of material beneath the second layer mask material absorbs or is etched by non-vertically travelling ions allowing only essentially vertically travelling ions to etch said substrate to an essentially uniform width.
- 2. The method as defined in claim 1 wherein the substrate is silicon.
- 3. The method as defined in claim 2 wherein the first layer of mask material is polysilicon.
- 4. The method as defined in claim 3 wherein the second layer of mask material is silicon dioxide.
- 5. The method as defined in claim 1 further characterized by said substrate including at least one layer of dielectric material on the surface thereof underlying said first layer of mask material.
- 6. The method as defined in claim 2 wherein the etch conditions for etching the trench in the substrate are selected such that essentially no passivation of the trench side walls in the substrate occurs during etching.
- 7. The method as defined in claim 2 wherein the aspect ratio of the trench is about 20:1 and the thickness of the first layer of material is about 30% of the depth of the trench.
- 8. The method as defined in claim 6, wherein a passivating layer is applied to the trench side walls.
- 9. The method as defined in claim 8, wherein said passivating layer includes silicon dioxide.
Parent Case Info
This is a continuation of copending application Ser. No. 07/504,197 filed on Apr. 3, 1990, abandoned.
US Referenced Citations (8)
Foreign Referenced Citations (2)
Number |
Date |
Country |
0272143 |
Jun 1988 |
EPX |
60-83331 |
Sep 1985 |
JPX |
Non-Patent Literature Citations (3)
Entry |
B. M. Kemlage, et al. "Fabrication of Oxide Isolation Using an Oxynitride/Polysilicon Mask", IBM Tech. Disclosure Bulletin, vol. 24, No. 9 (Feb. 1982). |
"Narrow Width Effects of Shallow Trench-Isolated CMOS with n+- Polysilicon Gate"--IEEE Transaction on Electron Devices, vol. 36, No. 6. |
"Trench Framed Recessed Oxide Isolation" IBM Technical Disclosure Bulletin, vol. 24, No. 118 (Apr., 1982). |
Continuations (1)
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Number |
Date |
Country |
Parent |
504197 |
Apr 1990 |
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