Patent Application
20250118376
The present disclosure relates to non-volatile memory.
Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery).
A memory structure in the memory system typically contains many memory cells and various control lines. The memory structure may be three-dimensional. One type of three-dimensional structure has non-volatile memory cells arranged as vertical NAND strings. The memory structure may be arranged into units that are commonly referred to as blocks. For example, a block in a NAND memory system contains many NAND strings. A NAND string contains memory cell transistors connected in series, a drain side select gate at one end, and a source side select gate at the other end. Each NAND string is associated with a bit line. The block typically has many word lines that provide voltages to the control gates of the memory cell transistors. In some architectures, each word line connects to the control gate of one memory cell on each respective NAND string in the block. The blocks may be divided into smaller units. Herein, the term “tier” will be used to refer to a portion of a block that has been divided such that different sets of word lines are in different tiers. Therefore, each tier contains only a subset of the memory cells of each NAND string in the block. A block may be divided into two, three, or more tiers. A “tier” of a block may also be referred to herein as a sub-block.
For memory such as NAND, a large set of memory cells are erased prior to programming. Herein, a set of memory cells that are erased as a unit are referred to as an “erase group”. In some techniques an erase group coincides with a block. In some cases an erase group is a portion of a block such as one tier. Thus, in some techniques each tier may be erased independent of the other tiers in the block.
After erasing, the memory cells within the erase group are programmed one unit at a time. In some techniques, the memory cells are programmed one word line at a time. The non-volatile memory cells may be programmed to store data. Typically, the memory cells are programmed to a number of data states. Using two data states to store a single bit per cell is referred to herein as SLC programming. Using a greater number of data states allows for more bits to be stored per memory cell. Using additional data states to store two or more bits per cell is referred to herein as MLC programming. For example, four data states may be used to store two bits per memory cell, eight data states may be used in order to store three bits per memory cell. 16 data states may be used to store four bits per memory cell, etc. Some memory cells may be programmed to a data state by storing charge in the memory cell. For example, the threshold voltage (Vt) of a NAND memory cell can be set to a target Vt by programming charge into a charge storage region such as a charge trapping layer. The amount of charge stored in the charge trapping layer establishes the Vt of the memory cell.
Once the memory cells in the memory device have been programmed, data may be read from the memory cells by sensing the programmed states of the memory cells. In one technique, the memory cells are sensed at one or more “read reference voltages” A read reference voltage is used to distinguish between two of the states. However, sensed states can sometimes vary from the written states due to one or more factors. Error detection and correction decoding can be used to detect and correct data errors resulting from sensed states that do not match written states. However, there is a limit as to how many bits in the un-decoded data read from the memory cells can be in error in order for the ECC algorithm to successfully correct all errors. Therefore, memory systems typically do not rely only on ECC algorithms. Another option is to move the read reference voltages and re-read the memory cells. In some cases, moving the read reference voltages can result in fewer bits in errors in the data prior to decoding to thereby improve the effectiveness ECC algorithm. One possible technique is to execute an ECC algorithm on data read with different candidate read reference voltages and then select the best read reference voltages based on an evaluation of the decoding process.
However, challenges remain in determining suitable read parameters for reading a group of memory cells such that there will be a low number of bits in error in the un-decoded data. For example, although read reference voltages can be moved with the read being re-tried this will consume additional time, current, and/power. Moreover, moving the read reference voltages and evaluating the decoding results may take many attempts to locate the best read reference voltages.
Like-numbered elements refer to common components in the different figures.
Technology is disclosed herein for reading memory cells in three-dimensional memory having multiple tiers. The memory system erases the tiers within each block independently. Then, memory cells in the tiers are programmed by units such as word lines. However, it is possible that when reading a selected tier that the other tiers in the block (“non-selected tiers”) are either programmed or erased. The programmed/erased states of the other tiers can impact the reading of the memory cells in the selected tiers. For example, the programmed/erased states of the other tiers may impact the Vt of memory cells in the selected tier. In an embodiment, the memory system will determine one or more read parameters for the selected tier based on the programmed/erased states of the other tiers in the block. In one embodiment, the memory system will select read reference levels for the selected tier based on the programmed/erased states of the other tiers. In an embodiment, the one or more read parameters are used to determine the set of reference voltages for a bit error rate estimation scan (BES). Briefly, the BES may include sensing memory cells using the aforementioned set of reference voltages, and then determining an error metric for codewords derived from the sensing. The error metric may be, for example, a syndrome weight (SW) or a bit error rate (BER). Accurate reference voltages should have a low SW (or low BER). Thus, the final reference voltages for use in the selected tier may be those having a low SW (or low BER). Therefore, the reference voltages may be dynamically updated such that the selected tier can be read accurately and quickly. Time, power and/current are not wasted re-trying the read with many different read levels. Note that the savings are not limited to reading the cells, but also executing an ECC algorithm on the data re-read from the memory cells.
In an embodiment, each block has an upper tier, a middle tier, and a lower tier, with each tier containing a different section of each NAND string in the block. The lower tier and the middle tier may be separated by a first interface layer having a first set of fabrication joints. The middle tier and the upper tier may be separated by a second interface layer having a second set of fabrication joints. In an embodiment, the NAND strings are formed in memory holes, with each fabrication joint providing an electrical connection between a NAND channel in one tier with a NAND channel in another tier. Therefore, the NAND strings may extend from the lower tier to the upper tier. In an embodiment, the programmed/erased states of the non-selected tiers are used to determine one or more read parameters for the tier selected for read.
The components of storage system 100 depicted in
Memory controller 120 comprises a host interface 152 that is connected to and in communication with host 102. In one embodiment, host interface 152 implements an NVM Express (NVMe) over PCI Express (PCIe). Other interfaces can also be used, such as SCSI, SATA, etc. Host interface 152 is also connected to a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit. NOC's can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communications and brings notable improvements over conventional bus and crossbar interconnections. NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs. The wires and the links of the N(XC are shared by many signals. A high level of parallelism is achieved because all links in the NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems keep growing, a NOC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments. N(C 154 can be replaced by a bus. Connected to and in communication with NOC 154 is processor 156. ECC engine 158, memory interface 160, and local memory controller 164. Local memory controller 164 is used to operate and communicate with local high speed memory 140 (e.g., DRAM, SRAM, MRAM).
ECC engine 158 performs error correction services. For example, ECC engine 158 performs data encoding and decoding. In one embodiment, ECC engine 158 is an electrical circuit programmed by software. For example, ECC engine 158 can be a processor that can be programmed. In other embodiments, ECC engine 158 is a custom and dedicated hardware circuit without any software. In another embodiment, the function of ECC engine 158 is implemented by processor 156.
Processor 156 performs the various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom and dedicated hardware circuit without any software. Processor 156 also implements a translation module, as a software/firmware process or as a dedicated hardware circuit. In many systems, the non-volatile memory is addressed internally to the storage system using physical addresses associated with the one or more memory die. However, the host system will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store the data as it wishes among the locations of the one or more memory die. To implement this system, memory controller 120 (e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory die. One example implementation is to maintain tables (i.e. the L2P tables mentioned above) that identify the current translation between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word “tables” they need not literally be tables. Rather, the logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of a storage system is so large that the local memory 140 cannot hold all of the L2P tables. In such a case, the entire set of L2P tables are stored in a storage 130 and a subset of the L2P tables are cached (L2P cache) in the local high speed memory 140.
Memory interface 160 communicates with non-volatile storage 130. In one embodiment, memory interface provides a Toggle Mode interface. Other interfaces can also be used. In some example implementations, memory interface 160 (or another portion of controller 120) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory die.
In one embodiment, non-volatile storage 130 comprises one or more memory dies.
System control logic 260 receives data and commands from memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (which comprises one or more electrical circuits) includes state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 is programmable by software. In other embodiments, the state machine 262 does not use software and is completely implemented in hardware (e.g., electrical circuits). In another embodiment, the state machine 262 is replaced by a micro-controller or microprocessor, either on or off the memory chip. System control logic 260 can also include a power control module 264 that controls the power and voltages supplied to the rows and columns of the memory structure 202 during memory operations. System control logic 260 includes storage 266 (e.g., RAM, registers, latches, etc.), which may be used to store parameters for operating the memory structure 202.
In an embodiment, the memory die 200 stores tier based read parameters 263.
Commands and data are transferred between memory controller 120 and memory die 200 via memory controller interface 268 (also referred to as a “communication interface”). Memory controller interface 268 is an electrical interface for communicating with memory controller 120. Examples of memory controller interface 268 include a Toggle Mode Interface and an Open NAND Flash Interface (ONFI). Other I/O interfaces can also be used.
In some embodiments, all the elements of memory die 200, including the system control logic 260, can be formed as part of a single die. In other embodiments, some or all of the system control logic 260 can be formed on a different die than the die that contains the memory structure 202.
In one embodiment, memory structure 202 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping layers.
In another embodiment, memory structure 202 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR-type flash memory) can also be used.
The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure 202 include ReRAM memories (resistive random access memories), magnetoresistive memory (e.g., MRAM. Spin Transfer Torque MRAM, Spin Orbit Torque MRAM). FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structure 202 include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.
One example of a ReRAM cross-point memory includes reversible resistance-switching elements arranged in cross-point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.
Another example is magnetoresistive random access memory (MRAM) that stores data by magnetic storage elements. The elements are formed from two ferromagnetic layers, each of which can hold a magnetization, separated by a thin insulating layer. One of the two layers is a permanent magnet set to a particular polarity; the other layer's magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created. MRAM based memory embodiments will be discussed in more detail below.
Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. In other PCM embodiments, the memory cells are programmed by current pulses Note that the use of“pulse” in this document does not require a square pulse but includes a (continuous or non-continuous) vibration or burst of current, voltage, light, or other wave. These memory elements within the individual selectable memory cells, or bits, may include a further series element that is a selector, such as an ovonic threshold switch or metal insulator substrate.
A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, memory construction or material composition, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.
The elements of
Another area in which the memory structure 202 and the peripheral circuitry are often at odds is in the processing involved in forming these regions, since these regions often involve differing processing technologies and the trade-off in having differing technologies on a single die. For example, when the memory structure 202 is NAND flash, this is an NMOS structure, while the peripheral circuitry is often CMOS based. For example, elements such sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic 260 often employ PMOS devices. Processing operations for manufacturing a CMOS die will differ in many aspects from the processing operations optimized for an NMOS flash NAND memory or other memory cell technologies. Three-dimensional NAND structures (see, for example.
To improve upon these limitations, embodiments described below can separate the elements of
System control logic 260, row control circuitry 220, and column control circuitry 210 may be formed by a common process (e.g., CMOS process), so that adding elements and functionalities, such as ECC, more typically found on a memory controller 120 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 120 may also be used to fabricate system control logic 260, row control circuitry 220, and column control circuitry 210). Thus, while moving such circuits from a die such as memory structure die 201 may reduce the number of steps needed to fabricate such a die, adding such circuits to a die such as control die 211 may not require many additional process steps. The control die 211 could also be referred to as a CMOS die, due to the use of CMOS technology to implement some or all of control circuitry 260, 210, 220.
For purposes of this document, the phrases “a control circuit” or “one or more control circuits” can include any one of or any combination of memory controller 120, state machine 262, power control 264, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, read/write circuits 225, sense amps, a microcontroller, a microprocessor, and/or other similar functioned circuits. A control circuit can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor. FPGA. ASIC, integrated circuit, or other type of circuit.
For purposes of this document, the term “apparatus” can include, but is not limited to, one or more of, storage system 100, storage 130, memory die 200, integrated memory assembly 207, and/or control die 211.
In some embodiments, there is more than one control die 211 and more than one memory structure die 201 in an integrated memory assembly 207. In some embodiments, the integrated memory assembly 207 includes a stack of multiple control dies 211 and multiple memory structure dies 201.
Each control die 211 is affixed (e.g., bonded) to at least one of the memory structure die 201. Some of the bond pads 282/284 are depicted. There may be many more bond pads. A space between two die 201, 211 that are bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. This solid layer 280 protects the electrical connections between the die 201, 211, and further secures the die together. Various materials may be used as solid layer 280.
The integrated memory assembly 207 may for example be stacked with a stepped offset, leaving the bond pads at each level uncovered and accessible from above. Wire bonds 270 connected to the bond pads connect the control die 211 to the substrate 271. A number of such wire bonds may be formed across the width of each control die 211 (i.e., into the page of
A memory die through silicon via (TSV) 276 may be used to route signals through a memory structure die 201. A control die through silicon via (TSV) 278 may be used to route signals through a control die 211. The TSVs 276, 278 may be formed before, during or after formation of the integrated circuits in the semiconductor dies 201, 211. The TSVs may be formed by etching holes through the wafers. The holes may then be lined with a barrier against metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.
Solder balls 272 may optionally be affixed to contact pads 274 on a lower surface of substrate 271. The solder balls 272 may be used to couple the integrated memory assembly 207 electrically and mechanically to a host device such as a printed circuit board. Solder balls 272 may be omitted where the integrated memory assembly 207 is to be used as an LGA package. The solder balls 272 may form a part of the interface between integrated memory assembly 207 and memory controller 120.
Some of the bond pads 282, 284 are depicted. There may be many more bond pads. A space between two dies 201, 211 that are bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. In contrast to the example in
Solder balls 272 may optionally be affixed to contact pads 274 on a lower surface of substrate 271. The solder balls 272 may be used to couple the integrated memory assembly 207 electrically and mechanically to a host device such as a printed circuit board. Solder balls 272 may be omitted where the integrated memory assembly 207 is to be used as an LGA package.
As has been briefly discussed above, the control die 211 and the memory structure die 201 may be bonded together. Bond pads on each die 201, 211 may be used to bond the two die together. In some embodiments, the bond pads are bonded directly to each other, without solder or other added material, in a so-called Cu-to-Cu bonding process. In a Cu-to-Cu bonding process, the bond pads are controlled to be highly planar and formed in a highly controlled environment largely devoid of ambient particulates that might otherwise settle on a bond pad and prevent a close bond. Under such properly controlled conditions, the bond pads are aligned and pressed against each other to form a mutual bond based on surface tension. Such bonds may be formed at room temperature, though heat may also be applied. In embodiments using Cu-to-Cu bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 5 μm to 5 μm. While this process is referred to herein as Cu-to-Cu bonding, this term may also apply even where the bond pads are formed of materials other than Cu.
When the area of bond pads is small, it may be difficult to bond the semiconductor dies together. The size of, and pitch between, bond pads may be further reduced by providing a film layer on the surfaces of the semiconductor die including the bond pads. The film layer is provided around the bond pads. When the die are brought together, the bond pads may bond to each other, and the film layers on the respective die may bond to each other. Such a bonding technique may be referred to as hybrid bonding. In embodiments using hybrid bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 1 μm to 5 μm. Bonding techniques may be used providing bond pads with even smaller sizes and pitches.
Some embodiments may include a film on surface of the dies 201, 211. Where no such film is initially provided, a space between the die may be under filled with an epoxy or other resin or polymer. The under-fill material may be applied as a liquid which then hardens into a solid layer. This under-fill step protects the electrical connections between the dies 201, 211, and further secures the die together. Various materials may be used as under-fill material.
Each sense amplifier 325 operates to provide voltages to one of the bit lines (see BL0, BL1, BL2, BL3) during program, verify, erase, and read operations. Sense amplifiers are also used to sense the condition (e.g., data state) of a memory cell in a NAND string connected to the bit line that connects to the respective sense amplifier.
Each sense amplifier 325 may have a sense node. During sensing, a sense node is charged up to an initial voltage, Vsense_init, such as 3V. The sense node is then connected to the bit line for a sensing time, and an amount of decay of the sense node is used to determine whether a memory cell is in a conductive or non-conductive state. The amount of decay of the sense node also indicates whether a current Icell in the memory cell exceeds a reference current. Iref. A larger decay corresponds to a larger current. If Icell<=Iref, the memory cell is in a non-conductive state and if Icell>Iref, the memory cell is in a conductive state. In an embodiment, the sense node has a capacitor that is pre-charged and then discharged for the sensing time.
In particular, the comparison circuit 320 determines the amount of decay by comparing the sense node voltage to a trip voltage after the sensing time. If the sense node voltage decays below the trip voltage, Vtrip, the memory cell is in a conductive state and its Vth is at or below the verify voltage. If the sense node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vth is above the verify voltage. A sense node latch 322 is set to 0 or 1, for example, by the comparison circuit 320 based on whether the memory cell is in a conductive or non-conductive state, respectively. The bit in the sense node latch 322 can also be used in a lockout scan to decide whether to set a bit line voltage to an inhibit or a program enable level in a next program loop. The bit in the sense node latch 322 can also be used in a lockout mode to decide whether to set a bit line voltage to a sense voltage or a lockout voltage in a read operation.
The data latches 340 are coupled to the sense amplifier 325 by a local data bus 346. The data latches 340 include three latches (ADL, BDL, CDL) for each sense amplifier 325 in this example. More or fewer than three latches may be included in the data latches 340. In one embodiment, for programming each data latch 340 is used to store one bit to be stored into a memory cell and for reading each data latch 340 is used to store one bit read from a memory cell. In a three bit per memory cell embodiment, ADL stores a bit for a lower page of data, BDL stores a bit for a middle page of data, CDL stores a bit for an upper page of data. Each read/write circuit 225 is connected to an XDL latch 348 by way of an XDL bus 352. In this example, transistor 336 connects local data bus 346 to XDL bus 352. An I/O interface 332 is connected to the XDL latches 348. The XDL latch 348 associated with a particular read/write circuit 225 serves as an interface latch for storing/latching data from the memory controller.
Managing circuit 330 performs computations, such as to determine the data stored in the sensed memory cell and store the determined data in the set of data latches. Each set of data latches 340 is used to store data bits determined by managing circuit 330 during a read operation, and to store data bits imported from the data bus 334 during a program operation which represent write data meant to be programmed into the memory. I/O interface 332 provides an interface between XDL latches 348 and the data bus 334.
During reading, the operation of the system is under the control of state machine 262 that controls the supply of different control gate voltages to the addressed memory cell. As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense circuit may trip at one of these voltages and a corresponding output will be provided from the sense amplifier to managing circuit 330. At that point, managing circuit 330 determines the resultant memory state by consideration of the tripping event(s) of the sense circuit and the information about the applied control gate voltage from the state machine. It then computes a binary encoding for the memory state and stores the resultant data bits into data latches 340.
During program or verify operations for memory cells, the data to be programmed (write data) is stored in the set of data latches 340 from the data bus 334 by way of XDL latches 348. The program operation, under the control of the state machine 262, applies a series of programming voltage pulses to the control gates of the addressed memory cells. Each voltage pulse may be stepped up in magnitude from a previous program pulse by a step size in a process referred to as incremental step pulse programming. In one embodiment, each program voltage is followed by a verify operation to determine if the memory cells have been programmed to the desired memory state. In some cases, managing circuit 330 monitors the read back memory state relative to the desired memory state. When the two agree, managing circuit 330 sets the bit line in a program inhibit mode such as by updating its latches. This inhibits the memory cell coupled to the bit line from further programming even if additional program pulses are applied to its control gate.
The block depicted in
Although
A three-tier other multi-tier stack can be used to form a relatively tall stack while maintaining a relatively narrow memory hole width (or diameter). After the layers of the lower tier 425 are formed, memory hole portions are formed in the lower tier 425. After the layers of the middle tier are formed, memory hole portions are formed in the middle tier. After the layers of the upper tier are formed, memory hole portions are formed in the upper tier. The memory holes of the upper tier are aligned with the memory holes of the middle tier and the upper tier and middle tier are joined together. In an embodiment a fabrication joint 435 connects a memory hole of the upper tier with a memory hole in the middle tier. The memory holes of the lower tier are aligned with the memory holes of the middle tier and the lower tier and middle tier are joined together. In an embodiment a fabrication joint 435 connects a memory hole of the middle tier with a memory hole in the lower tier. Therefore, the respective fabrication joints 435 may provide a conductive connection between the NAND channels in one tier with the NAND channels in another tier. Thus, the NAND strings will extend continuously through the three tiers. Hence. NAND strings may extend from one end of the stack to the other.
The resulting memory hole is narrower than would be the case if the memory hole was etched from the top to the bottom of the stack rather than in each tier individually. The interface layers (IF1, IF2) are created where each pair of tiers are connected. Due to the presence of the interface layers, the adjacent word line layers may suffer from edge effects such as difficulty in programming or erasing. These adjacent word line layers can therefore be set as dummy word lines (IFDL1, IFDU1, IFDL2, IFDU2). In an embodiment, the memory system operates the dummy word lines (IFDL1, IFDU1, IFDL2, IFDU2) as dummy word lines in both the full-block mode and the sub-block mode.
The structure of
In the sub-block mode, the upper tier 421, middle tier 423, and the lower tier 425 may be erased independently of each other. Hence, data may be maintained in the other tiers 421, 423 after the lower tier 425 is erased. Likewise, data may be maintained in the other tiers 421, 425 after the middle tier 423 is erased. Likewise, data may be maintained in the other tiers 423, 425 after the upper tier 421 is erased.
Vertical columns 432 and 434 are depicted protruding through the drain side select layer, source side select layer, IF layers, dummy word line layers, reconfigurable word line layers and data word line layers. In one embodiment, each vertical column comprises a vertical NAND string. Below the vertical columns and the layers listed below is substrate 457, an insulating film 454 on the substrate, and source line SL. The NAND string of vertical column 432 has a source end at a bottom of the stack and a drain end at a top of the stack. As in agreement with
For ease of reference, drain side select layer, source side select layer, dummy word line layers, data word line layers, and reconfigurable word line layers collectively are referred to as the conductive layers. In one embodiment, the conductive layers are made from a combination of TiN and Tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as Tungsten or metal silicide. In some embodiments, different conductive layers can be formed from different materials. Between conductive layers are dielectric layers. In one embodiment, the dielectric layers are made from SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layers.
The non-volatile memory cells are formed along vertical columns which extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. The word line layers WL0-W267 connect to memory cells (also called data memory cells). Dummy word line layers DD and DDS connect to dummy memory cells. A dummy memory cell does not store and is not eligible to store host data (data provided from the host, such as data from a user of the host), while a data memory cell is eligible to store host data. In some embodiments, data memory cells and dummy memory cells may have a same structure. Drain side select layer SGD is used to electrically connect and disconnect (or cut off) the channels of respective NAND strings from bit lines. Source side select layer SGS are used to electrically connect and disconnect (or cut off) the channels of respective NAND strings from the source line SL.
When a data memory cell transistor is programmed, electrons are stored in a portion of the charge-trapping layer which is associated with the data memory cell transistor. These electrons are drawn into the charge-trapping layer from the channel, and through the tunneling layer. The Vth of a data memory cell transistor is increased in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel.
Each of the memory holes can be filled with a plurality of annular layers (also referred to as memory film layers) comprising a blocking oxide layer, a charge trapping layer, a tunneling layer and a channel layer. A core region of each of the memory holes is filled with a body material, and the plurality of annular layers are between the core region and the WLLs in each of the memory holes. In some cases, the tunneling layer 464 can comprise multiple layers such as in an oxide-nitride-oxide configuration.
A source side selection line SGS connects/disconnects the NAND strings to/from the common source line. In some embodiments, there is a source side selection line for each finger (similar to the five SGD-s0, SGD-s1. SGD-s2, SGD-s3 and SGD-s4. The block can also be thought of as divided into five fingers: Finger 0, Finger 1, Finger 2. Finger 3, Finger 4. Finger 0 corresponds to those vertical NAND strings controlled by SGD-s0, Finger 1 corresponds to those vertical NAND strings controlled by SGD-s1, Finger 2 corresponds to those vertical NAND strings controlled by SGD-s2, Finger 3 corresponds to those vertical NAND strings controlled by SGD-s3, and Finger 4 corresponds to those vertical NAND strings controlled by SGD-s4. Note that the term “finger” in this context refers to regions that each contain entire NAND strings (but a subset of NAND strings in the block). In some embodiments, there is a sub-block mode in which each sub-block contains only a portion of each NAND string (see the tiers 421, 423, 425).
Although the example memories of
The storage systems discussed above can be erased, programmed and read. At the end of a successful programming process, the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate.
Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”). The data stored in MLC memory cells is referred to as MLC data; therefore, MLC data comprises multiple bits per memory cell. Data stored as multiple bits of data per memory cell is MLC data. In the example embodiment of
There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used.
Over time, the locations of the threshold voltage distributions may change. A factor in this change may be programming and/or erasing memory cells in another tier in the block. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. In one embodiment, adjusting the reference levels may be used to compensate for the change in the locations of the Vt distributions. One technique for adjusting the reference levels is to change the magnitude of the read reference voltages. For example, the magnitude of one or more of the hard bit reference voltages (Vr1 Vr15) may be dynamically updated. In some embodiments, the memory cells are read at a set of reference voltages that includes a hard bit reference voltage and offsets to the hard bit reference voltage in a process of dynamically updating the hard bit reference voltage.
Typically, the program voltage applied to the control gates (via a selected data word line) during a program operation is applied as a series of program pulses (e.g., voltage pulses). Between programming pulses a set of verify pulses (e.g., voltage pulses) may be used to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step 602 of
In step 608, a program voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If a memory cell on a NAND string should be programmed, then the corresponding bit line is biased at a program enable voltage. In step 608, the program pulse is concurrently applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently (unless they are inhibited from programming). That is, they are programmed at the same time or during overlapping times (both of which are considered concurrent). In this manner all of the memory cells connected to the selected word line will concurrently have their threshold voltage change, unless they are inhibited from programming.
In step 610, program verify is performed and memory cells that have reached their target states are locked out from further programming by the control die. Step 610 includes performing verification of programming by sensing at one or more verify reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage. In step 610, a memory cell may be locked out after the memory cell has been verified (by a test of the Vt) that the memory cell has reached its target state. For example, a memory cell may be locked out if it reaches a verify reference voltage.
If, in step 612, it is determined that all of the memory cells have reached their target threshold voltages (pass), the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step 614. Otherwise if, in step 612, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 616.
In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distribution are counted. That is, the number of memory cells that have, so far, failed to reach their target state are counted. This counting can be done by state machine 262, memory controller 120, or another circuit. In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state.
In step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, than the programming process can stop and a status of “PASS” is reported in step 614. In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step 618 is below the number of bits that can be corrected by error correction codes (ECC) during a read process to allow for future/additional errors. When programming fewer than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), than the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria.
If the number of failed memory cells is not less than the predetermined limit, than the programming process continues at step 620 and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 6, 12, 16, 19, 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step 624. If the program counter PC is less than the program limit value PL, then the process continues at step 626 during which time the Program Counter PC is incremented by 1 and the programming voltage signal Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size ΔVpgm (e.g., a step size of 0.1-1.0 volts). After step 626, the process loops back to step 604 and another program pulse is applied to the selected word line so that another iteration (steps 604-626) of the programming process of
In one embodiment memory cells are erased prior to programming, and erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. For example, changing the threshold voltage of memory cells from state P to state E of
In embodiments, a partial block erase is performed to erase tiers (or sub-blocks) independently). A partial block erase operation may be performed by biasing word lines within a selected tier to be erased with an erase enable voltage (e.g., 0V, 05V) while biasing other word lines in the other tiers that are not to be erased with an erase inhibit voltage high voltage (e.g., 15V) and providing an erase voltage to NAND channels in the block.
One technique to erase memory cells is to bias a p-well substrate to a high voltage to charge up a NAND channel. An erase enable voltage is applied to control gates of memory cells to be erased while the NAND channel is at a high voltage to erase the memory cells. In one embodiment, a p-well erase is performed. In some cases, the NAND strings within a block may share a common well (e.g., a p-well). In a p-well erase, holes may be provided from the p-well in the substrate below the NAND strings. In one embodiment, memory cells may be erased by raising the p-well to an erase voltage (e.g., 20 volts) for a sufficient period of time and grounding the word lines connected to memory cells to be erased. These erase bias conditions may cause electrons to be transferred from the charge-trapping layer or film 463 through the tunneling oxide 464, thereby lowering the threshold voltage of the memory cells within the selected block.
Another approach to erasing memory cells is to generate gate induced drain leakage (GIDL) current to charge up the NAND string channel. An erase enable voltage is applied to control gates of the memory cells, while maintaining the string channel potential to erase the memory cells. The GIDL current is generated by causing a drain-to-gate voltage at a select transistor, in one embodiment. The GIDL current may result when the select transistor drain voltage is significantly higher than the select transistor control gate voltage. GIDL current is a result of carrier generation, i.e., electron-hole pair generation due to band-to-band tunneling and/or trap-assisted generation. In one embodiment, GIDL current may result in one type of carriers, e.g., holes, predominantly moving into NAND channel 465, thereby raising the potential of the channel 465. The other type of carriers, e.g., electrons, are extracted from the channel 465, in the direction of a bit line or in the direction of a source line, by an electric field. During erase, the holes may tunnel from the channel to a charge storage region 463 of memory cells and recombine with electrons there, to lower the threshold voltage of the memory cells.
The programmed/erased states of other sub-blocks can impact the Vt of a sub-block selected for read.
An embodiment of a memory system determines and applies one or more read parameters within a tier that depends on the programmed/erased states of other tiers in the block. The read parameter may compensate for Vt shifts.
In the examples in the tables in
Step 1004 includes determining one or more read parameters based on the programmed/erased states of the non-selected tiers. As one example, table 900 in
Step 1006 includes reading the selected tier based on the read parameter(s). In one embodiment, the aforementioned reference signal is used to read the selected memory cells in the selected tier. In one embodiment, a read reference voltage is applied to a selected word line in the selected tier during the read. In one embodiment, the results of reading the memory cells are used to dynamically adjust the present read reference levels. In one embodiment, the results of reading the memory cells are used in a BES that dynamically adjusts the present read reference levels.
Steps 1106-1110 are performed for one or more different read levels. In one embodiment, steps 1106-1110 are performed to read a page of data, which may involve one, two, three, four or more reads, depending on the coding scheme and number of bits per cell. For example, with reference to
Step 1106 includes adding the offset to the base Vcgr for this state. Here, the offset may be positive or negative. Note that this offset may be one of the read parameters or may be determined from one of the read parameters in step 1004 of
The read parameters are not limited to being those used to sense at “hard bit voltages.” In one embodiment, the read parameters are used to sense at a set of reference voltages in order to dynamically update the hard bit reference voltages.
Step 1204 includes generating one or more pages of data from the sensing in step 1202. In the example based on
Step 1206 includes executing an ECC algorithm on each separate page of data. This step may result in a bit error rate, an estimation of a bit error rate, a syndrome weight, or some other decoding metric for each page.
Step 1208 includes updating the base reference voltages based on results of executing the ECC algorithm on each respective page. In one embodiment, the reference levels that produced the “best” decoding metric are selected. For example, the reference levels that results in the lowest actual bit error rate, lowest estimated bit error rate, or lowest syndrome weight are selected for the new base reference levels. In one embodiment, interpolation may be used to select values between two of the sets that each had similar decoding results.
Step 1304 includes counting the number of cells having a Vt above the reference voltage. This count need not be a count of every cell in that counting may stop if a certain number is reached. If the memory cells have been programmed then a substantial number of cells should have a Vt above the reference voltage. In this case, then in step 1306 the system records that the tier is programmed. If the memory cells have not been programmed (i.e., still erased) then not more than an insignificant number of cells should have a Vt above the reference voltage in which case in step 1308 the system records that the tier is erased. Step 1310 is a determination of whether there is another non-selected tier to evaluate. Process 1300 is able to quickly and accurately determine the programmed/erased states of the other tiers.
In view of the foregoing, a first embodiment includes an apparatus comprising one or more control circuits configured to communicate with a three-dimensional array of non-volatile memory cells. The non-volatile memory cells are arranged in blocks. The blocks are divided into multiple tiers with each tier comprising a set of word lines. The one or more control circuits configured to erase the multiple tiers in respective blocks separately. The one or more control circuits configured program memory cells in respective tiers after the respective tiers have been erased. The one or more control circuits configured determine one or more read parameters based on a programmed/erased state of at least one non-selected tier in a selected block having a tier selected for read. The one or more control circuits configured to read selected memory cells in the selected tier using the one or more read parameters.
In a further embodiment, each block comprises NAND strings and word lines. And the word lines in a block are connected to control gates of memory cells on the NAND strings.
In a further embodiment, the one or more read parameters comprise a magnitude of a reference signal. And the one or more control circuits are further configured to use the reference signal to read the selected memory cells in the selected tier.
In a further embodiment, the or more read parameters comprise a magnitude of a read reference voltage. And the one or more control circuits are further configured to apply the read reference voltage to a selected word line in the selected tier during the read of the selected memory cells in the selected tier. The selected word line is connected to the selected memory cells.
In a further embodiment, the one or more read parameters comprise a set of reference voltages that includes a base reference voltage to distinguish between two data states and offsets to the base reference voltage. And the one or more control circuits are further configured to apply the set of reference voltages to a selected word line in the selected tier during the read of the selected memory cells in the selected tier. The selected word line connected to the selected memory cells.
In a further embodiment, the one or more control circuits configured to update the base reference voltage for the selected tier based on results of reading the selected memory cells in the selected tier using the set of reference voltages.
in a further embodiment, each block comprises at least three tiers. And the one or more control circuits are further configured to determine the one or more read parameters based on a pattern of fully erased or fully programmed tiers in the selected block.
In a further embodiment, each block comprises at least three tiers. And the one or more control circuits are further configured to read at a single reference voltage in the non-selected tiers to determine whether the at least one non-selected tier is programmed or erased.
In a further embodiment, each block comprises at least three tiers. And the one or more control circuits are further configured to read a single word line in each non-selected tier to determine whether the non-selected tiers are programmed or erased.
In a further embodiment, each block comprises at least three tiers. And the one or more control circuits are further configured to read the selected memory cells in the selected tier using the one or more read parameters when the selected tier is fully programmed and the non-selected tiers are either fully programmed or fully erased.
One embodiment includes a method for operating non-volatile storage. The method comprises erasing sub-blocks of memory cells independently within blocks comprising memory cells on NAND strings, wherein each block is divided into at least three sub-blocks with each sub-block comprising a different portion of each NAND string in the block. The method comprises programming respective sub-blocks of memory cells after the respective sub-blocks have been erased. The method comprises determining one or more read reference levels for a selected sub-block in a selected block based on whether the other sub-blocks in the selected block are programmed or erased. The method comprises applying the one or more read reference levels to control gates of selected memory cells in the selected sub-block to read the selected memory cells.
One embodiment includes a non-volatile storage system. The system comprises a three-dimensional array of non-volatile memory cells. The non-volatile memory cells are arranged in blocks. The blocks are divided into multiple tiers. The system comprises erase means for erasing multiple tiers in each block separately. The system comprises program means for programming each word line in each tier after the tier has been erased. The system comprises read parameter means for determining one or more read parameters that depend on whether non-selected tiers in a selected block are erased or programmed. The system comprises read means for applying the one or more read parameters to selected memory cells in a selected tier of the selected block to read the selected memory cells.
In a further embodiment of the volatile storage system, the blocks comprises NAND strings. In a further embodiment of the volatile storage system each tier comprises a portion of each NAND string in the block. In a further embodiment of the volatile storage system each respective block comprises fabrication joints that provide a conductive connection between NAND channels in one tier of the respective block with NAND channels in another tier of the respective block.
In an embodiment, the erase means for erasing multiple tiers in each block separately comprises one or more of memory controller 120, system control logic 260, state machine 262, column control circuitry 210, row control circuitry 220, a processor, an FPGA, an ASIC, and/or an integrated circuit. In an embodiment, the erase means performs the process of
In an embodiment, the program means for programming each word line in each tier after the tier has been erased comprises one or more of memory controller 120, system control logic 260, state machine 262, column control circuitry 210, row control circuitry 220, a processor, an FPGA, an ASIC, and/or an integrated circuit. In an embodiment, the program means performs the process of
In an embodiment, the read parameter means for determining one or more read parameters that depend on whether non-selected tiers in a selected block are erased or programmed comprises one or more of memory controller 120, system control logic 260, state machine 262, column control circuitry 210, row control circuitry 220, a processor, an FPGA, an ASIC, and/or an integrated circuit. In an embodiment, the read parameter means performs the process of
in an embodiment, the read means for applying the one or more read parameters to selected memory cells in a selected tier of the selected block to read the selected memory cells comprises one or more of memory controller 120, system control logic 260, state machine 262, column control circuitry 210, row control circuitry 220, a processor, an FPGA, an ASIC, and/or an integrated circuit. In an embodiment, the read means performs the process of
For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.
For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via one or more intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.
For purposes of this document, the term “based on” may be read as “based at least in part on.”
For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects.
For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects.
The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.
