Patent Application
20140359202
1. Technical Field
This disclosure relates to data storage systems. More particularly, the disclosure relates to systems and methods for calculating reading voltage levels in solid-state data storage devices.
2. Description of the Related Art
Certain solid-state memory devices, such as flash drives, store information in an array of memory cells constructed with floating gate transistors. In single-level cell (SLC) flash devices, each cell stores a single bit of information. In multi-level cell (MLC) devices, each cell stores two or more bits of information. When a read operation is performed, the electrical charge levels of the cells are compared to one or more voltage reference values (also called “reading voltage level” or “voltage threshold”) to determine the state of individual cells. In SLC devices, a cell can be read using a single voltage reference value. In MLC devices, a cell is read using multiple voltage references values. Certain solid-state devices allow for a memory controller to set reading voltage levels.
Various factors can contribute to data read errors in solid-state memory devices. These factors include charge loss or leakage over time, and device wear caused by usage. When the number of bit errors on a read operation exceeds the ECC (error correction code) correction capability of the storage subsystem, the read operation fails. Reading voltage levels can contribute to a device's ability to decode data.
Various embodiments are depicted in the accompanying drawings for illustrative purposes, and should in no way be interpreted as limiting the scope of the inventions. In addition, various features of different disclosed embodiments can be combined to form additional embodiments, which are part of this disclosure. Throughout the drawings, reference numbers may be reused to indicate correspondence between reference elements.
While certain embodiments are described, these embodiments are presented by way of example only, and are not intended to limit the scope of protection. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the scope of protection.
Data storage cells in solid-state memory, such as multi-level-per-cell (MLC) flash memory, may have distinct threshold voltage distribution (Vt) levels, corresponding to different memory states. For example, in an MLC implementation, different memory states in solid-state memory may correspond to a distribution of voltage levels ranging between reading voltage (VR) levels; when the charge of a memory cell falls within a particular range, one or more reads of the page may reveal the corresponding memory state of the cell. The term “read” is used herein with respect to voltage reads of solid-state memory according to its broad and ordinary meaning, and may refer to read operations on a page, including a plurality of cells (e.g., thousands of cells), or may be used with respect to a voltage charge level of a single memory cell.
Reading voltage levels can advantageously be set to values in the margins between memory states. According to their charge level, memory cells store different binary data representing user data. For example, based on its charge level, each cell generally falls into one of the memory states, represented by associated data bits.
Over time, and as a result of various physical conditions and wear from repeated program/erase (P/E) cycles, the margins between the various distribution levels may be reduced, so that voltage distributions overlap to some extent. Such reduction in read margin may be due to a number of factors, such as loss of charge due to flash cell oxide degradation, over-programming caused by erratic program steps, programming of adjacent erased cells due to heavy reads or writes in the locality of the cell (or write disturbs), and/or other factors, all of which may contribute to read failure in a solid-state storage device.
In addition to data corruption, read failure can result from the use of fixed reading voltage levels that are not adapted to the voltage distribution shifts of the memory cells inside the device. Although devices may be programmed with fixed manufacturer-determined reading voltage levels, certain embodiments may provide for overriding of such default manufacturer read levels. Certain embodiments disclosed herein provide systems and methods for reading memory cells at adjusted/optimized reading voltage levels, which may provide for improved data recovery. In particular, three techniques for determining adjusted/optimal read voltage levels are described below, which may be applicable to either generic or pre-calibrated solid-state memories.
“Page,” or “E-page,” as used herein may refer to the unit of data correction of embodiments disclosed herein. For example, error correction/calibration operations may be performed on a page-by-page basis. A page of data may be any suitable size. For example, a page may comprise 1 k, 2 k, 4 k, or more bytes of data. Furthermore, the term “location,” or “memory location” is used herein according to its broad and ordinary meaning and may refer to any suitable partition of memory cells within one or more data storage devices. A memory location may comprise a contiguous array of memory cells or addresses (e.g., a page).
As used in this application, “non-volatile solid-state memory” may refer to solid-state memory such as NAND flash. However, the systems and methods of this disclosure may also be useful in more conventional hard drives and hybrid drives including both solid-state and hard drive components. Solid-state memory may comprise a wide variety of technologies, such as flash integrated circuits, Phase Change Memory (PC-RAM or PRAM), Programmable Metallization Cell RAM (PMC-RAM or PMCm), Ovonic Unified Memory (OUM), Resistance RAM (RRAM), NAND memory, NOR memory, EEPROM, Ferroelectric Memory (FeRAM), MRAM, or other discrete NVM (non-volatile solid-state memory) chips. The non-volatile solid-state memory arrays or storage devices may be physically divided into planes, blocks, pages, and sectors, as is known in the art. Other forms of storage (e.g., battery backed-up volatile DRAM or SRAM devices, magnetic disk drives, etc.) may additionally or alternatively be used.
The error management module 140 includes an error correction module 144 for encoding and decoding data transferred to/from the non-volatile memory array(s) 150. Furthermore, the error management module 140 includes an optimal VR calculation module 142 for calculating adjusted/optimal reading voltage levels in order to provide optimal data to the error correction module 144 according to one or more embodiments disclosed herein to increase the error correction module's ability to decode data stored in the memory array(s).
In certain embodiments, the controller 130 is configured to receive memory access commands from a storage interface (e.g., a device driver) 112 residing on a host system 110. The controller 130 is configured to execute commands in response to such host-issued memory commands in the non-volatile solid-state memory arrays 150. Storage access commands communicated by the storage interface 112 can include write and read commands issued by the host system 110. The commands can specify a block address in the solid-state storage device 120, and the controller 130 can execute the received commands in the non-volatile solid-state memory array 150. Data may be accessed/transferred based on such commands. In an embodiment, the solid-state storage device 120 may be a hybrid disk drive that additionally includes magnetic memory storage (not shown). In such case, one or more controllers 130 may control the magnetic memory storage and the non-volatile solid-state memory array(s) 150.
The solid-state storage device 120 can store data received from the host system 110 so that the solid-state storage device 120 can act as memory storage for the host system 110. To facilitate this function, the controller 130 can implement a logical interface. The logical interface can present to the host system 110 storage system memory as a set of logical addresses (e.g., contiguous address) where data can be stored. Internally, the controller 130 can map logical addresses to various physical memory addresses in the non-volatile solid-state memory array 150 and/or other memory module(s).
The horizontal axis depicted in
The gap between the levels (i.e., margin between programmed states), in which the read voltage references may advantageously be positioned in certain embodiments, is referred to as “read margin.” Over time, and as a result of various physical conditions and wear, for example from being subjected to repeated P/E cycles, the read margins between the various distribution levels may be reduced, resulting in both data retention problems and higher read errors beyond certain limits. Such reduction in read margin may be due to a number of factors, such as loss of charge due to flash cell oxide degradation, over-programming caused by erratic program steps, programming of adjacent erased cells due to heavy reads or writes in the locality of the cell (or write disturbs), and/or other factors. As read margins are diminished, or disappear, fixed read voltage levels such as R1, R2, and R3, may prove less reliable. Therefore, adjustment of one or more reading voltage levels can improve decoding reliability in certain embodiments.
While the diagram of
The vertical lines labeled ‘R2’ and ‘R3’ along the X-axis represent preset manufacturer's settings for two of the three reading voltages in a two-bit programming scheme. The third reading voltage, R1, may be set relatively closely to 0 V, and is generally ignored in the present discussion for convenience. These preset levels may be set such that initially, they may be disposed to the left of the optimal reading level, wherein over time the optimal reading level moves to the left, passing the preset level. As stated, the arrows indicate how the state cross points may shift with data retention (DR) time (time between initial writing and a current read operation) in an embodiment. To minimize the errors from readout, such reading voltages may be set at or near state cross points. Since the cross points may shift, in certain embodiments, the reading voltages may also shift in order to improve decoding. As illustrated in the graph of
As illustrated in
Even if the readout of a solid-state storage device fails by reading at the manufacturer-provided VR's, the associated data may not necessarily be lost. Many times the data is easily recoverable by shifting the VR's away from the manufacturer's settings to a more optimal voltage level (e.g. the state cross-points shown in
In an embodiment, target pages may be associated with one or more reference page(s) having similar characteristics. For example, a passing page in a block may be designated as the reference page for all pages in the same block, since the pages within the same block are assumed to have experienced the same number of P/E cycles. In another example, any passing page within the same block as the target page could be considered a reference page to the target page. In yet another example, any passing page within in a designated range of blocks neighboring the block in which the target page is located may be considered a reference page. On the other hand, in certain embodiments, such as when passing pages are not available, direct finding of optimal VR's on failing pages may also be performed. Certain methods involving direct calculation from failed pages may be more involved than methods requiring use of passing reference pages.
In solid-state storage devices, the P/E cycle number for a given block may be known. Preliminarily calibrating the memory according to its P/E condition may provide data retention information according to P/E cycling, thereby simplifying optimal VR calculation. Three methods for calculating adjusted VR's in solid-state storage devices are disclosed below, including both calibration-based and non-calibration techniques. Furthermore, the methods described below implement VR calculation based on both passing and failing pages. The process 400 may be performed at least in part by the controller 130, the optimal VR calculation module 142, and/or the error correction module 144 described above with respect to
Data Retention Index Method
Since data retention time and the other factors can be difficult to obtain, information incorporating all the DR effects can be helpful in estimating optimal VR shift. Once the relationship between VR shift and data retention is known, in block 610 the process 600A generates an index relating flipped-bit counts to optimal voltage shift. Such index data may provide an indication of how and/or to what extent the programming distributions have shifted without the requirement of detailed knowledge of the data storage history, including temperature, time stamp, and the like. Therefore, such index data may be used to adjust reading voltages to minimize the bit error rate in reading. In certain embodiments, the process 600A stores, in block 620, the generated index data in the solid-state storage device, wherein the solid-state storage device may access the index data during normal operation. For example, the index data may be stored in a reserved portion (e.g., reserve table) of the solid-state storage device.
Considering optimal VR shift in response to changing data retention characteristics, error bit count may vary if a solid-state storage device is continually read using manufacturer default VR's as data retention characteristics change. Table A provides an example of error bit count information vs. data retention condition, where fluctuating data retention condition is based on elapsed time, when reading at the default VR for R2 for a block of an embodiment of a solid-state storage device:
The third column of Table A includes data representing the logarithmic value of the lower page 1->0 flip bit counts.
Data retention calibration may provide certain information associated with VR shift. For example, Table B provides R2 and R3 shift data charted over stimulated changing data retention conditions (increasing age of the solid-state storage device stimulated through baking the memory at a certain temperature for the various periods of time as shown in Table B). The voltage shift values illustrated in Table B are determined with respect to default values (or manufacturer settings) of R2=1.82 V and R3=3.36 V.
RBER Polynomial Fitting Method
Certain embodiments disclosed herein provide methods for calculating VR shift using polynomial fitting techniques. In an embodiment, VR shift may be calculated using polynomial fitting for passing reference pages or blocks. Knowledge of P/E cycle condition may not be required.
Shown in Table C are optimal VR's found using polynomial fitting and raw bit error count improvement data over a range of P/E cycle counts for a block of memory in an embodiment. As shown, adjusting VR using parabolic fitting may provide bit error reduction by a factor of three or more for P/E numbers larger than 1 k in certain embodiments. In Table C below, the rows labeled R1(V), R2(V), and R3(V) indicate the VR's used in the optimal reads at the individual P/E levels.
Cumulative Distribution Polynomial Fitting Method
The two methods of optimal VR calculation discussed above work for passing blocks or pages, where the ECC decoding successfully decodes data from the blocks or pages. Sometimes the internal voltage levels of failing pages or blocks may vary substantially from those of passing pages or blocks, such that applying adjusted reading voltage levels obtained from the passing pages is insufficient for adequately recovering the data in such failing pages/blocks. Therefore, being able to find optimal VR's directly from a failing target page may be desirable in certain situations, for example, when adjusted VR's calculated from one of the above methods do not sufficiently reduce the number of error bits so that the error correction can recover data from a target page. Certain embodiments disclosed herein provide for optimal VR calculation from failing pages using cumulative bit count distribution information.
y(x)=−2496.5x4+39418x3−223407x2+547103x−476805 (1)
In certain embodiments, the point at which the fitted polynomial (which may correspond to the cumulative distribution curve shown in
The point of the function having the flattest slope over the range of data points may be determined by solving the equation y″(x)=0 for the variable ‘x,’ representing the to be determined optimal VR. For example, solving y″(x)=0 may yield an optimal VR value of approximately 3.13 V. By comparison to the corresponding state cross point shown in
The read levels, states, and coding schemes associated with voltage level distributions described herein, as well as variables and designations used to represent the same, are used for convenience only. As used in this application, “non-volatile solid-state memory” typically refers to solid-state memory such as, but not limited to, NAND flash. However, the systems and methods of this disclosure may also be useful in more conventional hard drives and hybrid hard drives including both solid-state and hard drive components. The solid-state storage devices (e.g., dies) may be physically divided into planes, blocks, pages, and sectors, as is known in the art. Other forms of storage (e.g., battery backed-up volatile DRAM or SRAM devices, magnetic disk drives, etc.) may additionally or alternatively be used.
Those skilled in the art will appreciate that in some embodiments, other types of data storage devices and/or data retention monitoring can be implemented. In addition, the actual steps taken in the processes shown in
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of protection. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the protection. For example, the various components illustrated in the figures may be implemented as software and/or firmware on a processor, ASIC/FPGA, or dedicated hardware. Also, the features and attributes of the specific embodiments disclosed above may be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure. Although the present disclosure provides certain preferred embodiments and applications, other embodiments that are apparent to those of ordinary skill in the art, including embodiments which do not provide all of the features and advantages set forth herein, are also within the scope of this disclosure. Accordingly, the scope of the present disclosure is intended to be defined only by reference to the appended claims.
This application claims priority to provisional U.S. Patent Application Ser. No. 61/829,955 (Atty. Docket No. T6268.P), filed on May 31, 2013, which is hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61829955 | May 2013 | US |
