This invention relates to systems and methods for fabricating features in memory devices.
Photolithography and other patterning techniques are used to fabricate features of particular sizes and shapes. These features can include parts of electrical devices for instance, such as wires, channels, electrical contacts, and the like. For many reasons, the device industry desires to fabricate smaller features. Smaller features can enable devices to be smaller overall, cheaper, faster, and more robust.
To fabricate patterns having smaller and smaller features, various patterning techniques and systems have been created or improved. Advanced photolithography systems, for example, have recently been designed to fabricate patterns having features as small as one hundred nanometers. These systems are extremely expensive, however. Currently these system can cost tens of millions of dollars. Other less-advanced photolithography systems are also available some of which are typically capable of fabricating patterns having features only as small as 250 nanometers. While these systems typically cannot pattern one-hundred-nanometer features, they often cost millions less than the advanced photolithography systems.
Further, whatever the patterning technique or system used, each typically has a limit on how small it can fabricate features. As smaller and smaller features are desired, even advanced patterning techniques and systems may not be capable of fabricating features of a desired size.
There is, therefore, a need for systems and methods capable of reducing feature sizes.
The same numbers are used throughout the disclosure and figures to reference like components and features.
Overview
This document discloses systems and methods (“tools”) for reducing feature sizes. One of these tools enables a feature patterned with a relatively inexpensive system to be reduced in size to that which would otherwise be patterned with a much more expensive system. This tool enables fabrication of features at a lower cost than is otherwise typically available. Another tool reduces feature sizes below those that are typically patternable even with advanced systems. By so doing, features of very small sizes are enabled. In addition, in at least some embodiments, memory devices can be fabricated using these tools.
Patterned Features
Referring initially to
Each feature 102 can be defined physically by a structure 106, shown in a clipped plane view along A-A′. This structure forms the outer bounds of the feature. In the embodiment shown in
With some exemplary features and accompanying structures set forth, the discussion now turns, for purposes of illustration, to exemplary memory devices having a feature that can be size-reduced using the tools described herein.
Fabricating an Exemplary Memory Device
In the embodiment about to be described, memory devices are fabricated, in part, with the tools to reduce the size of one or more of their features. These memory devices are set forth as examples, and are not intended to limit the applicability of the tools.
Referring to
The features 102, in this example, are circular in shape. As with many devices, a feature's size in one or more dimensions affects the performance of the device. In the ongoing embodiment, each of the features comprises an area exposing one of the bottom electrodes. Once this area is reduced in size, the reduced area will determine how much memory material is formed in electrical communication with the bottom electrodes. Because of this, the area exposing the bottom electrodes affects the power consumption and reliability of the memory device. The smaller the area, generally the better the memory device performs.
Prior to reducing the size of features 102, the features have lengths L and widths W shown in the top plan view. The widths are also shown in a clipped-plane view along the line A-A′. In this example, each of the features has the same width and length (because the shape of each feature is circular), though with many other shapes this is not the case.
In the ongoing embodiment, the width and the length of each of the features is about 250 nanometers. These dimensions of the features are those typically capable of being formed with less advanced photolithography and using techniques that will be appreciated by the skilled artisan. Other sizes, such as widths and lengths of about 100 nanometers can also be formed, such as with more-advanced photolithography.
Reducing Feature Size
Exemplary processes by which one or more feature sizes can be reduced are set forth below. These processes can comprise alignment-independent techniques, such as thin-film deposition and anisotropic etching.
Referring to
In the ongoing memory device example, the removable layer is formed of a dielectric material, such as silicon oxide or silicon nitride.
Generally, as part of this formation of the removable layer 302, the layer thickness TL conforms to the underlying structure 106 and so has a varying height based on dimensions of the underlying structure and its boundaries 108 that surround the feature 102. These varying heights of the removable layer occupy regions of each feature.
As shown in an expanded view in
Dimensions of these spacer precursor regions 304 and the reduced feature precursor region 306 are dependent on the layer thickness TL. The dimension (e.g., the width) of the spacer precursor regions 304 is about equivalent to the layer thickness TL.
In one embodiment (not illustrated), the layer thickness is formed at about forty-five percent of the size (e.g., width) of the feature 102 that is desired to be reduced. In this case, the spacer precursor regions 304 occupy about ninety percent of the feature's size in the width dimension, and the reduced feature precursor region 306 about ten percent.
In another embodiment, the layer thickness is formed at about forty percent of the size of the feature 102 that is desired to be reduced. In this case, the spacer precursor regions 304 occupy about eighty percent of the feature's size in that dimension, and the reduced feature precursor region 306 about twenty percent.
In the illustrated embodiment, the reduced feature precursor region's 306 reduced width WR is based on the width W (here the original width) of the feature 102 and the widths of the spacer precursor regions 304. The reduced width WR of the reduced feature precursor region 306 is about equal to the width W minus twice the layer thickness TL.
Also in the illustrated embodiment, the feature's 102 width W is about 250 nanometers. The layer thickness TL is formed to a thickness of about ninety nanometers (or thirty-six percent of the width W). Thus, the reduced width WR of the reduced feature precursor region 306 is about seventy nanometers (250−(2*90)=70).
Referring to
Based on the exemplary embodiments described above, a size of the feature 102 can be reduced by ninety, eighty, and seventy-two (100−(2*36)=28) percent. This reduction in size of the feature is represented in the illustrated embodiment by the reduced feature 402. Size reductions more than ninety or less than seventy-two percent can also be performed. They can be performed by forming the removable layer 302 to a layer thicknesses TL of greater than forty-five or less than thirty-six percent of the size to be reduced.
In the illustrated embodiment of the memory device, substantially all of removable layer 302 over the reduced feature precursor region 306 is removed. Enough of the removable layer 302 directly over the spacer precursor regions 304 is not removed to leave spacers 404. In this case, the size of the reduced feature precursor region 306 is substantially similar to the size of the reduced feature 402. Relatedly, the reduced width WR of
In another embodiment, some of the removable layer 302 remains in the reduced feature precursor region 306. In this case, the reduced feature 402 may have a dimension that is smaller than the reduced feature precursor region 306 (not shown).
In still another embodiment, all of the removable layer 302 in the reduced feature precursor region 306 is removed and some of the spacer precursor region 304 near the region 306 has all of the removable layer 302 removed. In this case, the spacers 404 are not as large as the spacer precursor regions 304 and the reduced feature 402 has a dimension larger than the reduced feature precursor region 306 (not shown).
Fabricating The Memory Device With The Reduced Feature
Referring to
In the illustrated embodiment, the active amount of the media 502 is reduced through these tools by about 92% ((70/2)ˆ2/(250/2) ˆ2=0.078). The memory media can comprise a phase change material, such as Indium Telluride (InTe) or Indium Selenide (InSe), a ferroelectric material, such as PZT (PbZrxTi1-xO3), SBT (SrBi2Ta2O9), Bi4Ti3O12, or other suitable memory materials.
Each of these memory devices can be formed individually or as a larger system. For a larger system of memory devices, such as a cross-bar memory device, the feature size reduction enabled by the tools can be performed for all of the devices in the system at one once. By so doing, these tools can permit consistent production and reduce cost.
Following formation of the memory media, the top electrodes 506 are formed over the active media 504 with suitable techniques. These top electrodes form an array of conductive structures capable of electrical communication with the active media. A passivation layer can also be formed over the top electrodes and the memory media, if desired (not shown). The result is a cross-bar memory device 508 having improved operating characteristics permitted by reduction of a feature size.
Although the invention is described in language specific to structural features and methodological steps, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or steps described. Rather, the specific features and steps disclosed represent exemplary forms of implementing the claimed invention.