Claims
- 1. A redundant decision circuit, comprising:a switching element connected between a low potential power supply and a node; a switching driver connected to the switching element for driving the switching element; a fuse; a load circuit connected in series with the fuse between a high potential power supply and the node; and a hold circuit, connected to the node, for latching a potential at the node and generating a redundant decision signal.
- 2. The circuit of claim 1, wherein the load circuit generates a voltage drop in accordance with a current flowing in the fuse.
- 3. The circuit of claim 1, wherein the switching element is an N-channel MOS transistor and the load circuit is an N-channel MOS transistor the gate of which is connected to the high potential power supply.
- 4. The circuit of claim 1, wherein the switching element is an N-channel MOS transistor and the load circuit is two series connected N-channel MOS transistors the gates of which are connected to the high potential power supply.
- 5. The circuit of claim 1, wherein the switching element is an N-channel MOS transistor and the load circuit is a resistor.
- 6. The circuit of claim 1, wherein the switching element is an N-channel MOS transistor and the load circuit is a diode.
- 7. A semiconductor memory device, comprising:a memory cell array including a normal cell array and a redundant cell array; a redundant decision circuit for generating a redundant decision signal; and a decoder, connected to the redundant decision circuit, for performing a redundant operation to select a normal cell of the normal cell array or a redundant cell of the redundant cell array in accordance with the redundant decision signal, the redundant decision circuit including, a switching element connected between a low potential power supply and a node, a switching driver connected to the switching element for driving the switching element, a fuse, a load circuit connected in series with the fuse between a high potential power supply and the node, and a hold circuit, connected to the node, for latching a potential at the node and generating the redundant decision signal.
- 8. A method for deciding redundancy, comprising the steps of:connecting a switching element to a low potential power supply; connecting a fuse and a load circuit in series between the switching element and a high potential power supply; driving the switching element to generate a potential at a node between the switching element and the fuse, the potential at the node decreasing by a voltage drop generated by the load circuit; and holding the potential at the node to generate a redundant decision signal.
Priority Claims (1)
Number |
Date |
Country |
Kind |
10-305492 |
Oct 1998 |
JP |
|
Parent Case Info
This is a divisional application of U.S. patent application Ser. No. 09/310,192, filed May 12, 1999, U.S. Pat. No. 6,128,234.
US Referenced Citations (12)