These and other advantages of the invention will be apparent to those of ordinary skill in the art by reference to the following detailed description and the accompanying drawings.
The invention is a new method to identify and insert test points at the register transfer level RTL to reduce the volume of scan-based transition test patterns. Test points are inserted in the scan-paths and do not modify the functionality of the circuit. The dependency of the second pattern in a transition test is reduced using the proposed test points which significantly reduce the number of inputs (and flip-flops) that need to be specified to detect a particular fault. Reducing the specified bits for each fault, results in higher test pattern compaction as well as higher test compression. The inventive method uses a very fast Satisfiability (SAT) based process with rules depending on the function of the register transfer RT level component to identify scan flip-flops that are difficult to control. By inserting the test points identified using the invention, the data volume of transition test patterns can be reduced significantly while the impact on area and delay are negligible.
Test generation for transition faults using LOC (broadside) approach is somewhat similar to two time-frame sequential test generation. It is explained below using the example circuit in
This is illustrated by the diagram 10 of
Boolean Satisfiability refers to the problem of determining a satisfying variable assignment for a Boolean function, or a proof that no such variable assignment exists in which case the function is unsatisfiable (UNSAT). A SAT problem takes as input a propositional formula that is represented in the conjunctive normal form (CNF). The CNF is a conjunction of several clauses, each of which is a disjunction of literals. A literal is a variable in its positive or negative polarity.
Generally any circuit representing a Boolean function can be transformed into a propositional formula. For instance, a two input AND gate with input a, b and output o can be represented as (a+ō)(b+ō)(ā+
Recent advances in SAT make it possible to identify the unsatisfiable segment if the SAT instance is unsatisfiable. From the UNSAT segment, a minimal set of clauses (called UNSAT core) can be extracted. This is explained in further detail in where a scheme for non-scan DFT based on extracting the UNSAT core is proposed. The UNSAT core is useful in identifying the regions of the circuit which are difficult to solve. Other information about the circuit can be obtained from the learned clauses which are generated by the SAT engine while solving a SAT instance during test generation. In this work, we use both the UNSAT core and learned clauses to identify specific characteristics of the circuit.
The key feature of the invention is to insert test points such that the number of specified bits required in transition fault testing is reduced. This is done by reducing the dependency of the second time-frame pattern on the first time-frame pattern. The scan flip-flops in the second time-frame which require a large number of scan flip-flops to be specified in the first time-frame are controlled directly, thereby reducing the number of specified bits to detect transition faults. This results not only in higher static and dynamic compaction but also higher test compression since the effectiveness of most compression schemes is directly related to the number of specified bits in test patterns. Under the invention, test points are inserted such that these flip-flops are directly loaded with the second time-frame value using a multiplexer. The test point is an extra flip-flop that stores the required second time-frame value.
Consider again the example circuit 10 in
An alternative way of inserting test points in accordance with the invention is shown by the diagram 30 of
As mentioned above, the proposed test point is an additional flip-flop which is added to the scan chain so that it stores the required second time-frame value. As seen from
Under the teachings of the present invention, test points are identified based on the functional information of RTL elements. If behavioral RTL is given, we analyze and elaborate the design into a temporary structural RTL netlist which gives a basic sense of circuit topology. A fast search is then done on this temporary structural RTL netlist to identify flip-flops that are (i) specified most in test patterns for transition faults and (ii) difficult to control in the second time-frame. Since adequate structural information is not available, the traditional controllability/observability analysis techniques cannot capture all the information. A functional approach is required and since RTL primitives like adders, multiplexers etc. can be easily transformed into CNF formula, a SAT based heuristic is used.
In the proposed scheme, a fast (and approximate) test generation for transition faults is done using SAT on the temporary RT Level netlist and the UNSAT and LEARNED clauses are utilized to identify potential flip-flops where test points can be inserted. A subset of transition faults is sampled for test generation to reduce the computation overhead. A score is maintained for each flip-flop in the design that indicates the number of times it has been utilized for test generation. For a sample of the transition faults in the temporary RT Level netlist, SAT instances for test patterns are generated and sent to the SAT solver. If the instances are satisfiable, the score of flip-flops appearing in the LEARNED clauses is increased. If the SAT instances are unsatisfiable, the score of flip-flops appearing in the UNSAT clauses are increased. The scan flip-flop with the highest score after the sampling is identified for test point insertion. Note that we can use weighted scores to differentiate between UNSAT and LEARNED clauses and the weights can be adjusted depending on the type of circuit, test generation ease etc. After each test point insertion, the clause used to represent constraints on the chosen flip-flop needs to be modified in the CNF representation of the circuit.
An exemplary flow chart 50 of the present test point insertion method is shown in
The heuristic used for fault sampling and propagation path selection is explained below. A two phase sampling is used for selecting the faults. Initially, faults are selected randomly. In the second phase, faults are selected on lines with lowest scores. A score Sg is maintained for each line (variable) g, that represents the number of times it has appeared in UNSAT cores and LEARNED clauses. In this application, we define the score as Sg=Ug×w+Lg where Ug represents the number of times the line g occurs in UNSAT cores and Lg represents the corresponding number in LEARNED clauses. The weight, w depends on the test generation complexity of the circuit. In the proposed scheme, a probable propagation path for the sampled fault is selected using a greedy heuristic. The next node in the path is selected as the one with minimum Sg till the path reaches a primary or pseudo-primary output.
Note that Ftf actually represents a possible scenario to detect fault f. If Ftf is satisfiable 507, 512 then f is testable. The opposite is not true because there may be other sensitizable propagation paths. The key idea is not about checking whether Ftf is satisfiable but to locate the appropriate parts of the circuit that hinder test generation. If Ftf is unsatisfiable, an UNSAT core is extracted 516. On the other hand, if Ftf is satisfiable, a set of conflict LEARNED clauses 511 are obtained. Both the UNSAT core and conflict LEARNED clauses represent the difficulty of test pattern generation and the scores 510 for each line are updated appropriately. After enough faults have been sampled 509, the state element which has the highest score 515 is selected as the candidate for test point insertion. Since inserting a test point will change the testability of the circuit, if multiple test points are inserted 514, the test points need to be added iteratively. In each iteration, only one flip-flop is selected to add the test point. The CNF for the circuit Fc is updated with this test point for the new iteration 508. If enough test points Ts 514 are arrived at, then an output circuit with test points inserted is obtained 513.
In summary, the inventive insertion methodology with RTL level test points provides delay testing data reduction. When taking into account a high level design, a subset of flip-flops are identified as test points at RTL level using satisfiability. Extra flip-flops are inserted at these test points to improve the testability of the circuit. The original design along with the test points are synthesized together to a gate level netlist. Experiments on several benchmark designs and industry designs demonstrate that a very significant delay testing data volume reduction is achievable without violating the timing constraints, while still maintaining the minimum area overhead.
The present invention has been shown and described in what are considered to be the most practical and preferred embodiments. It is anticipated, however, that departures may be made there from and that obvious modifications will be implemented by those skilled in the art. It will be appreciated that those skilled in the art will be able to devise numerous arrangements and variations which, although not explicitly shown or described herein, embody the principles of the invention and are within their spirit and scope.
This application claims the benefit of U.S. Provisional Application No. 60/829,171, entitled “RTL TEST POINT INSERTION TO REDUCE DELAY TEST VOLUME”, filed on Oct. 12, 2006, the contents of which is incorporated by reference herein. This application is also related to U.S. patent application Ser. No. 11/851,137, entitled “PARTIAL ENHANCED SCAN TECHNIQUE FOR TRANSITION DELAY TEST PATTERNS”, filed on Sep. 6, 2007, an to U.S. Provisional Application No. 60/829,183, entitled “LOW OVERHEAD PARTIAL ENHANCED SCAN TECHNIQUE FOR COMPACT AND HIGH FAULT COVERAGE TRANSITION DELAY TEST PATTERNS”, both of which are also incorporated by reference herein.
Number | Date | Country | |
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60829171 | Oct 2006 | US |