Data generators or compressors

Industry

CPC
G01R31/318547

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318547Data generators or compressors

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus to identify faults in processors
- Patent number 12,085,610
- Issue date Sep 10, 2024
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Grant
Wrapper cell design and built-in self-test architecture for 3DIC te...
- Patent number 12,066,490
- Issue date Aug 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Hybrid solver for integrated circuit diagnostics and testing
- Patent number 12,038,478
- Issue date Jul 16, 2024
- Xerox Corporation
- Aleksandar B. Feldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-sensitive scan-chain testing
- Patent number 12,025,661
- Issue date Jul 2, 2024
- MARVELL ASIA PTE. LTD.
- Balaji Upputuri
- G01 - MEASURING TESTING
Information Patent Grant
Programmable test compression architecture input/output shift regis...
- Patent number 12,013,434
- Issue date Jun 18, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for scan chain stitching
- Patent number 12,007,440
- Issue date Jun 11, 2024
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface system for interconnected die and MPU and communication m...
- Patent number 11,971,446
- Issue date Apr 30, 2024
- Jinghe Wei
- G01 - MEASURING TESTING
Information Patent Grant
Test compression in a JTAG daisy-chain environment
- Patent number 11,965,930
- Issue date Apr 23, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Single “A” latch with an array of “B” latches
- Patent number 11,961,575
- Issue date Apr 16, 2024
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test architecture for electronic circuits, corresponding device and...
- Patent number 11,940,492
- Issue date Mar 26, 2024
- STMicroelectronics S.r.l.
- Lorenzo Re Fiorentin
- G01 - MEASURING TESTING
Information Patent Grant
Memory tester and test method that uses memory tester
- Patent number 11,933,846
- Issue date Mar 19, 2024
- Kioxia Coporation
- Kenji Yasui
- G01 - MEASURING TESTING
Information Patent Grant
Compressed scan chain diagnosis by internal chain observation, proc...
- Patent number 11,921,159
- Issue date Mar 5, 2024
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Using scan chains to read out data from integrated sensors during s...
- Patent number 11,921,160
- Issue date Mar 5, 2024
- Synopsys, Inc.
- Bartosz Grzegorz Gajda
- G01 - MEASURING TESTING
Information Patent Grant
Generating multiple pseudo static control signals using on-chip JTA...
- Patent number 11,899,063
- Issue date Feb 13, 2024
- Texas Instruments Incorporated
- Mudasir Shafat Kawoosa
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods to detect cell-internal defects
- Patent number 11,837,308
- Issue date Dec 5, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ankita Patidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Universal compactor architecture for testing circuits
- Patent number 11,815,555
- Issue date Nov 14, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Grant
Programmable scan chain debug technique
- Patent number 11,754,624
- Issue date Sep 12, 2023
- Seagate Technology LLC
- Bharat Londhe
- G01 - MEASURING TESTING
Information Patent Grant
Scan test control decoder with storage elements for use within inte...
- Patent number 11,747,399
- Issue date Sep 5, 2023
- Texas Instruments Incorporated
- Mudasir Shafat Kawoosa
- G01 - MEASURING TESTING
Information Patent Grant
Input data compression for machine learning-based chain diagnosis
- Patent number 11,681,843
- Issue date Jun 20, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Yu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test compression in a JTAG daisy-chain environment
- Patent number 11,639,963
- Issue date May 2, 2023
- Texas Instmments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scalable scan architecture for multi-circuit block arrays
- Patent number 11,639,962
- Issue date May 2, 2023
- Xilinx, Inc.
- Niravkumar Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressed scan chain diagnosis by internal chain observation, proc...
- Patent number 11,592,483
- Issue date Feb 28, 2023
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Trajectory-optimized test pattern generation for built-in self-test
- Patent number 11,585,853
- Issue date Feb 21, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Grant
Utilizing single cycle ATPG test patterns to detect multicycle cell...
- Patent number 11,579,194
- Issue date Feb 14, 2023
- Cadence Design Systems, Inc.
- Arvind Chokhani
- G01 - MEASURING TESTING
Information Patent Grant
Maximization of side-channel sensitivity for trojan detection
- Patent number 11,579,185
- Issue date Feb 14, 2023
- University of Florida Research Foundation, Inc.
- Prabhat Kumar Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable test compression architecture input/output shift regis...
- Patent number 11,567,131
- Issue date Jan 31, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for scan dump of latch array
- Patent number 11,443,823
- Issue date Sep 13, 2022
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-on-chip for AT-SPEED test of logic circuit and operating met...
- Patent number 11,442,107
- Issue date Sep 13, 2022
- Samsung Electronics Co., Ltd.
- Beom Seok Shin
- G01 - MEASURING TESTING
Information Patent Grant
Method and circuit for row scannable latch array
- Patent number 11,443,822
- Issue date Sep 13, 2022
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Suspect resolution for scan chain defect diagnosis
- Patent number 11,423,202
- Issue date Aug 23, 2022
- SIEMENS INDUSTRY SOFTWARE INC.
- Grzegorz Mrugalski
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...
- Publication number 20240361385
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORS
- Publication number 20240345160
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Application
PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER
- Publication number 20240337691
- Publication date Oct 10, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
X-Masking for In-System Deterministic Test
- Publication number 20240337693
- Publication date Oct 10, 2024
- Siemens Industry Software Inc.
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT
- Publication number 20240264230
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20240249791
- Publication date Jul 25, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC DEVICE AND METHOD OF TESTING ELECTRONIC DEVICE
- Publication number 20240210471
- Publication date Jun 27, 2024
- Samsung Electronics Co., Ltd.
- Seaeun Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing Devices for reducing scan traffic, Method and Computer P...
- Publication number 20240159829
- Publication date May 16, 2024
- Intel Corporation
- Min LIU
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC VOLTAGE FREQUENCY SCALING TO REDUCE TEST TIME
- Publication number 20240110979
- Publication date Apr 4, 2024
- MEDIATEK INC.
- Anshul Varma
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS AND METHODS TO DETECT CELL-INTERNAL DEFECTS
- Publication number 20240087668
- Publication date Mar 14, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ankita Patidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT PACKAGE FOR SCAN TESTING SEMICONDUCTOR CHIP, OPE...
- Publication number 20240061040
- Publication date Feb 22, 2024
- Samsung Electronics Co., Ltd.
- Taewoong AHN
- G01 - MEASURING TESTING
Information Patent Application
PROVIDING CONFIGURABLE SECURITY FOR INTELLECTUAL PROPERTY CIRCUITS...
- Publication number 20240003973
- Publication date Jan 4, 2024
- Intel Corporation
- Ratheesh Thekke Veetil
- G01 - MEASURING TESTING
Information Patent Application
Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...
- Publication number 20230366930
- Publication date Nov 16, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
MEMORY TESTER AND TEST METHOD THAT USES MEMORY TESTER
- Publication number 20230296671
- Publication date Sep 21, 2023
- KIOXIA Corporation
- Kenji YASUI
- G01 - MEASURING TESTING
Information Patent Application
TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT
- Publication number 20230266389
- Publication date Aug 24, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20230194605
- Publication date Jun 22, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGIS...
- Publication number 20230176123
- Publication date Jun 8, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Stacked Integrated Circuit Device
- Publication number 20230116320
- Publication date Apr 13, 2023
- Graphcore Limited
- Stephen FELIX
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCAN TEST CONTROL DECODER WITH STORAGE ELEMENTS FOR USE WITHIN INTE...
- Publication number 20220326302
- Publication date Oct 13, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Mudasir Shafat KAWOOSA
- G01 - MEASURING TESTING
Information Patent Application
GENERATING MULTIPLE PSEUDO STATIC CONTROL SIGNALS USING ON-CHIP JTA...
- Publication number 20220326303
- Publication date Oct 13, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Mudasir Shafat Kawoosa
- G01 - MEASURING TESTING
Information Patent Application
INTERFACE SYSTEM FOR INTERCONNECTED DIE AND MPU AND COMMUNICATION M...
- Publication number 20220276304
- Publication date Sep 1, 2022
- 58th Research Institute of China Electronics Technology Group Corporation
- Jinghe Wei
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS AND METHODS TO DETECT CELL-INTERNAL DEFECTS
- Publication number 20220230699
- Publication date Jul 21, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ankita Patidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGIS...
- Publication number 20220074989
- Publication date Mar 10, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUSPECT RESOLUTION FOR SCAN CHAIN DEFECT DIAGNOSIS
- Publication number 20220065932
- Publication date Mar 3, 2022
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20210364569
- Publication date Nov 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT
- Publication number 20210356522
- Publication date Nov 18, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
EMPIRICAL LBIST LATCH SWITCHING AND STATE PROBABILITY DETERMINATION
- Publication number 20210270898
- Publication date Sep 2, 2021
- International Business Machines Corporation
- Franco Motika
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM-ON-CHIP FOR AT-SPEED TEST OF LOGIC CIRCUIT AND OPERATING MET...
- Publication number 20210223315
- Publication date Jul 22, 2021
- Samsung Electronics Co., Ltd.
- Beom Seok SHIN
- G01 - MEASURING TESTING
Information Patent Application
PROGRAMMABLE SCAN COMPRESSION
- Publication number 20210072311
- Publication date Mar 11, 2021
- SEAGATE TECHNOLOGY LLC
- Bharat P. Londhe
- G01 - MEASURING TESTING
Information Patent Application
PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGIS...
- Publication number 20210041500
- Publication date Feb 11, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Data generators or compressors

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods and apparatus to identify faults in processors

Wrapper cell design and built-in self-test architecture for 3DIC te...

Hybrid solver for integrated circuit diagnostics and testing

Power-sensitive scan-chain testing

Programmable test compression architecture input/output shift regis...

Systems and methods for scan chain stitching

Interface system for interconnected die and MPU and communication m...

Test compression in a JTAG daisy-chain environment

Single “A” latch with an array of “B” latches

Test architecture for electronic circuits, corresponding device and...

Memory tester and test method that uses memory tester

Compressed scan chain diagnosis by internal chain observation, proc...

Using scan chains to read out data from integrated sensors during s...

Generating multiple pseudo static control signals using on-chip JTA...

Systems and methods to detect cell-internal defects

Universal compactor architecture for testing circuits

Programmable scan chain debug technique

Scan test control decoder with storage elements for use within inte...

Input data compression for machine learning-based chain diagnosis

Test compression in a JTAG daisy-chain environment

Scalable scan architecture for multi-circuit block arrays

Compressed scan chain diagnosis by internal chain observation, proc...

Trajectory-optimized test pattern generation for built-in self-test

Utilizing single cycle ATPG test patterns to detect multicycle cell...

Maximization of side-channel sensitivity for trojan detection

Programmable test compression architecture input/output shift regis...

Method and circuit for scan dump of latch array

System-on-chip for AT-SPEED test of logic circuit and operating met...

Method and circuit for row scannable latch array

Suspect resolution for scan chain defect diagnosis

Patents Applicationslast 30 patents

Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...

METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORS

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER

X-Masking for In-System Deterministic Test

TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

ELECTRONIC DEVICE AND METHOD OF TESTING ELECTRONIC DEVICE

Processing Devices for reducing scan traffic, Method and Computer P...

DYNAMIC VOLTAGE FREQUENCY SCALING TO REDUCE TEST TIME

SYSTEMS AND METHODS TO DETECT CELL-INTERNAL DEFECTS

INTEGRATED CIRCUIT PACKAGE FOR SCAN TESTING SEMICONDUCTOR CHIP, OPE...

PROVIDING CONFIGURABLE SECURITY FOR INTELLECTUAL PROPERTY CIRCUITS...

Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...

MEMORY TESTER AND TEST METHOD THAT USES MEMORY TESTER

TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGIS...

Stacked Integrated Circuit Device

SCAN TEST CONTROL DECODER WITH STORAGE ELEMENTS FOR USE WITHIN INTE...

GENERATING MULTIPLE PSEUDO STATIC CONTROL SIGNALS USING ON-CHIP JTA...

INTERFACE SYSTEM FOR INTERCONNECTED DIE AND MPU AND COMMUNICATION M...

SYSTEMS AND METHODS TO DETECT CELL-INTERNAL DEFECTS

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGIS...

SUSPECT RESOLUTION FOR SCAN CHAIN DEFECT DIAGNOSIS

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT

EMPIRICAL LBIST LATCH SWITCHING AND STATE PROBABILITY DETERMINATION

SYSTEM-ON-CHIP FOR AT-SPEED TEST OF LOGIC CIRCUIT AND OPERATING MET...

PROGRAMMABLE SCAN COMPRESSION

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGIS...