This application claims the priority benefit of Taiwan application serial no. 101119681, filed on May 31, 2012. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The disclosure relates to a resistance random access memory (RRAM) and a method of fabricating the same.
A resistance random access memory (RRAM), having a high memory density (minimum unit area of storage) and a high operation speed and requiring a low power consumption and low costs, is a memory device that has been widely studied in recent years. RRAM uses a conversion of electrons and/or ions in a resistance conversion material to generate two completely different states of a high resistance state and a low resistance state so as to distinguish whether a memory storage unit is turned on or off.
A hafnium oxide RRAM has a good durability and a high switching speed and is one of the most eye-catching memory devices in next-generation non-volatile memory devices. However, a titanium/hafnium oxide RRAM used currently has a wide distribution of resistance values under a high resistance state (HRS), which poses a considerable restriction on an operation thereof.
The disclosure provides a RRAM including a first electrode layer, a second electrode layer, and a stacked structure. The stacked structure is located between the first electrode layer and the second electrode layer and includes a HfZrON layer and a ZrON layer, wherein the HfZrON layer is located between the first electrode layer and the ZrON layer, and the ZrON layer is located between the HfZrON layer and the second electrode layer.
The disclosure further provides a method of fabricating a RRAM, the method including forming a hafnium oxide layer on the first electrode layer and then forming a zirconium layer. Then, a second electrode layer is formed on the zirconium layer. Next, an annealing process is performed to make the zirconium layer react with the hafnium oxide layer to form a stacked structure between the first electrode layer and the second electrode layer, the stacked structure including a HfZrON layer and a ZrON layer, wherein the HfZrON layer is located between the first electrode layer and the ZrON layer, and the ZrON layer is located between the HfZrON layer and the second electrode layer.
The disclosure further provides another method of fabricating a RRAM, the method including providing a first electrode layer. A stacked structure is formed on the first electrode layer. The stacked structure includes a HfZrON layer and a ZrON layer. Then, a second electrode layer is formed on the stacked structure. The HfZrON layer is located between the first electrode layer and the ZrON layer, and the ZrON layer is located between the HfZrON layer and the second electrode layer. The HfZrON layer and the ZrON layer are formed by deposition process.
In order to make the aforementioned features and advantages of the disclosure more comprehensible, embodiments accompanying figures are described in detail below.
The accompanying drawings are included to provide further understanding and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments and, together with the description, serve to explain the principles of the disclosure.
Referring to
A material of the first electrode layer 10 is, for example, a metal or a metal nitride, including conductive materials such as platinum (Pt), iridium (Ir), titanium, titanium nitride (TiN), tantalum, tantalum nitride (TaN), tungsten (W), tungsten nitride (WN) or any combination thereof. A material of the second electrode layer 30 is, for example, a metal or a metal nitride, including conductive materials such as platinum, iridium, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride or any combination thereof.
The stacked structure 20 is located between the first electrode layer 10 and the second electrode layer 30. The stacked structure 20, the first electrode layer 10 and the second electrode layer 30 form a metal-insulator-metal (MIM) structure. The stacked structure 20 at least includes a hafnium zirconium oxynitride (HfZrON) layer 24 and a zirconium oxynitride (ZrON) layer 26. The HfZrON layer 24 may be composed of a single material layer. The HfZrON layer 24 may also include a first material layer 24a and a second material layer 24b, and a mole ratio of nitrogen, oxygen, zirconium and hafnium in the first material layer 24a is different from a mole ratio of nitrogen, oxygen, zirconium and hafnium in the second material layer 24b. In an embodiment, a material of the first electrode layer 10 and the second electrode layer 30 includes a titanium nitride. In addition to including the HfZrON layer 24 and the ZrON layer 26, the stacked structure 20 further includes a hafnium titanium oxynitride (HfTiON) layer 22 and a zirconium titanium nitride (ZrTiN) layer 28. The HfTiON layer 22 is located between the first electrode layer 10 and the HfZrON layer 24. The ZrTiN layer 28 is located between the ZrON layer 26 and the second electrode layer 30.
The stacked structure 20 may be formed by deposition process or by reaction.
Referring to
Then, the stacked structure 20 is formed on the first electrode layer 10 by deposition process. The stacked structure 20 includes at least the HfZrON layer 24 and the ZrON layer 26. The HfZrON layer 24 may be composed of a single material layer. The HfZrON layer 24 may also include the first material layer 24a and the second material layer 24b, and the mole ratio of nitrogen, oxygen, zirconium and hafnium in the first material layer 24a is different from the mole ratio of nitrogen, oxygen, zirconium and hafnium in the second material layer 24b. The HfZrON layer 24 and the ZrON layer 26 may be formed sequentially by deposition process, such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
In addition to including the HfZrON layer 24 and the ZrON layer 26, the stacked structure 20 further includes the HfTiON layer 22 and the ZrTiN layer 28. The HfTiON layer 22 is located between the first electrode layer 10 and the HfZrON layer 24. The ZrTiN layer 28 is located between the ZrON layer 26 and the second electrode layer 30. The HfTiON layer 22, the HfZrON layer 24, the ZrON layer 26, and the ZrTiN layer 28 of the stacked structure 20 may be formed sequentially by deposition process, such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
Then, the second electrode layer 30 is formed on the stacked structure 20. The material of the second electrode layer 30 is, for example, a metal or a metal nitride, including conductive materials such as platinum, iridium, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride or any combination thereof.
Referring to
Then, referring to
Then, a second electrode material layer 130 is formed on the hafnium oxide layer 124 and the zirconium layer 126. The second electrode material layer 130 may be a single-layered material layer or a double-layered material layer. A material of the second electrode material layer 130 includes titanium nitride.
Thereafter, referring to
Then, referring to
A process temperature of the annealing process is greater than or equal to 400° C. A highest temperature of the annealing process is adjusted according to actual requirements. When the RRAM is formed in a back-end process, and a metal line has been formed on the substrate 100 before the RRAM is formed, then the highest temperature of the annealing process has to be set with a melting point of the metal line taken into consideration. A gas introduced into the annealing process includes nitrogen or the annealing process is performed in vacuum. The process temperature of the annealing process is greater than or equal to 400° C. and less than or equal to 500° C. The annealing process includes a furnace annealing process or a rapid thermal annealing (RTA) process. In an embodiment, the annealing process is the furnace annealing process, and an annealing temperature is in a range form 400 to 500° C., and an annealing time is in a range form 1 to 10 minutes. In an embodiment, the annealing process is the rapid thermal annealing process, and an annealing temperature is in a range form 400 to 500° C., and an annealing time is in a range form 1 to 30 minutes.
Then, referring to
Thereafter, referring to
In the embodiment, the first electrode layer 110 is viewed as a bottom electrode layer, and the second electrode layer 130a is viewed as a top electrode layer. The stacked structure 220 includes the HfTiON layer 222, the HfZrON layer 224, the ZrON layer 226, and the ZrTiN layer 228. The HfTiON layer 222, the HfZrON layer 224 and the ZrON layer 226 are insulating layers, and the ZrTiN layer 228 is a conductive layer.
A method of fabricating the stacked structure of the RRAM of the above embodiment may form the stacked structure including the HfTiON layer, the HfZrON layer, the ZrON layer, and the ZrTiN layer through the annealing process after the hafnium oxide layer and the zirconium layer are deposited; therefore, the fabrication process thereof is very simple. In addition, the required annealing time is in a ranged from 1 to 30 minutes, so the fabrication process is very quick. However, a method of forming the HfZrON layer and the ZrON layer of the disclosure is not limited to the above way of using reactions; the HfZrON layer and the ZrON layer may be formed by deposition process, such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
Experiment 1
A 5 nm thick hafnium oxide layer and a 10 nm thick zirconium layer are sequentially deposited on a titanium nitride and titanium (TiN/Ti) bottom electrode, and then a titanium nitride top electrode is formed on the zirconium layer. Then, an annealing is performed for 5 minutes with a furnace process under a nitrogen gas ambiance at a temperature of 400° C. Then, a measurement is performed by an X-ray energy dispersive spectrometer (EDS), and results of the measurement are as shown in
According to the method of Experiment 1, a 5 nm thick hafnium oxide layer and a 10 nm thick zirconium layer are sequentially deposited on a TiN/Ti electrode, and then a titanium nitride electrode is formed. Then, the annealing process of Experiment 1 is not performed. Thereafter, a measurement is performed by the X-ray energy dispersive spectrometer (EDS), and results of the measurement are as shown in
According to the method of Experiment 1, a 5 nm thick hafnium oxide layer and a 5 nm thick zirconium layer are sequentially deposited on a TiN/Ti electrode, and then a titanium nitride electrode is formed. Then, an annealing process is not performed. Next, an electrical test and an operating characteristic analysis are performed. Results of the electrical test are as shown by Curves 300 or by Line 300 in
According to the method of Experiment 1, a 3 nm thick hafnium oxide layer and a 5 nm thick zirconium layer are sequentially deposited on a TiN/Ti electrode, and then a titanium nitride electrode is formed. Then, an annealing process is not performed. Next, an electrical test and an operating characteristic analysis are performed. Results of the electrical test are as shown by Curves 400 or by Line 400 in
According to the method of Experiment 1, a 20 nm thick hafnium oxide layer and a 10 nm thick zirconium layer are sequentially deposited on a TiN/Ti electrode, and then a titanium nitride electrode is formed. Then, an annealing process is not performed. Next, an electrical test and an operating characteristic analysis are performed. Results of the electrical test are as shown by Curves 500 or by Line 500 in
Experiment 2
According to the method of Experiment 1, a 5 nm thick hafnium oxide layer and a 10 nm thick zirconium layer are sequentially deposited on a TiN/Ti electrode, and then a titanium nitride electrode is formed to fabricate memory cells of various sizes. Then, an annealing is performed with a rapid thermal annealing process under a nitrogen gas ambiance at various temperatures. Next, an electrical test is performed, and results thereof are as shown in
Compared with
In a current-voltage characteristic curve diagram shown in
In a current-voltage characteristic curve diagram shown in
Results of Line 100 and Lines 200-500 in
Results of
Bonding results obtained from FIGS. 13A and 14A-14H show that after the hafnium oxide layer, the zirconium layer and the titanium nitride top electrode are sequentially deposited on the bottom electrode composed of titanium nitride and titanium and before the annealing process is performed, the hafnium oxide layer reacts with the underlying titanium nitride layer after deposited to form a HfTiN layer and a HfON layer. After the zirconium layer is deposited, since the activity of zirconium is very high, the zirconium layer reacts with an interface of the HfON layer below to form two HfZrON layers which have different atomic mole ratios and a ZrON layer, and the zirconium itself may not oxidize and form an oxygen-doped zirconium layer.
The bonding results obtained from FIGS. 13B and 14A-14H show that after the hafnium oxide layer, the zirconium layer and the titanium nitride top electrode are sequentially deposited on the bottom electrode composed of titanium nitride and titanium and after the annealing process is performed, a HfTiON layer, and the two HfZrON layers which have different atomic mole ratios, the ZrON layer, and a ZrTiN layer are formed sequentially between the top electrode and the bottom electrode.
In summary of the above, because there is the HfZrON layer in the stacked structure between the two electrodes, the RRAM of the disclosure has a relatively stable and narrowly distributed reset/set voltage, high resistance, low resistance and maximum reset current, a good operational stability, and an endurance thereof reaches 105 cycles, which prolongs the service life thereof. In addition, the RRAM of the disclosure forms the HfZrON layer by simply depositing the hafnium oxide layer and the zirconium layer and by the annealing process; the fabrication process is simple, and the time the fabrication process requires is relatively short.
Although the disclosure has been disclosed by the above embodiments, they are not intended to limit the disclosure. It will be apparent to those of ordinary skill in the art that modifications and variations to the disclosure may be made without departing from the spirit and the scope of the disclosure. Accordingly, the protection scope of the disclosure falls in the appended claims.
Number | Date | Country | Kind |
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101119681 | May 2012 | TW | national |