Claims
- 1. In a RISC type microprocessor, an improved on-chip cache system organized into X rows and Y columns, where X and Y are non-zero integers, with each of (X.times.Y) storage locations, located at the intersection of each row and column, accessed by a unique index field, said cache system comprising:
- a plurality of N cache segments, where N is a non-zero integer less than Y, each segment having a subset of the Y columns included in the cache and X segmented word lines;
- a predecoder, that receives a first portion of said unique index field and has outputs coupled to N segment select lines, each corresponding to one of said cache segments, for decoding said first portion to assert only one segment select signal on a unique one of said segment select lines identified by said first portion;
- a bus system for transferring data to and from the cache;
- a plurality of sense amp/write amp units, one of said units coupling each cache segment to said bus system and each having a select input coupled to a unique one of said segment select lines, each unit activated for either writing data from the bus system to the cache segment or reading data from the cache segment to the bus system when a segment select signal is asserted on the unique segment select line coupled to the unit and with said unit consuming power only when activated;
- a plurality of X word line drivers, disposed in each segment, each word line driver in a given cache segment coupled to a unique one of said segmented word lines in the given cache segment;
- a plurality of N row decoders, with each row decoder coupled to the X word line drivers of a unique cache segment, with each row decoder receiving a second portion of said unique index field and having a select input coupled to a unique one of said segment select lines, each row decoder activated for decoding said second portion to activate a unique one of said X word line drivers when a select signal is asserted on the unique segment select line coupled to the row decoder;
- a staging register for receiving a group of K data words, said group having a length of Y/N bits, from said segment when a select signal is asserted on said unique segment select line associated with said segment; and
- a K:1 multiplexer for receiving a third portion of said unique index field and decoding said third portion to select one of said K data words.
- 2. The cache of claim 1 wherein said bus system includes a read bus and a write bus and further comprising:
- a plurality of bus drivers, one of said bus drivers coupling each sense amp/write amp unit to said read bus and having a select input coupled to a unique one of said segment select lines, each bus driver activated to drive data on said read bus when a segment select signal is asserted on the unique segment select line coupled to the driver with said bus driver consuming power only when activated.
Parent Case Info
This application is a continuation of application Ser. No. 08/064,189, filed May 17, 1993, now abandoned.
US Referenced Citations (16)
Continuations (1)
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Number |
Date |
Country |
Parent |
64189 |
May 1993 |
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