Patent Application
20110204518
The present disclosure relates to miniaturized semiconductor devices with improved contact resistance and reliability. The present disclosure is particularly applicable to miniaturized semiconductor devices with improved liner/barrier layer properties.
Conductive contacts and vias are formed to electrically connect source/drain regions and conductive features of an integrated circuit. The contacts/vias are conventionally formed by patterning and etching a dielectric material layer to form an opening therein, depositing a liner/barrier layer, typically a combination of layers, such as of titanium (Ti), tantalum (Ta), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and/or cobalt (Co), to line the side surfaces and bottom of the opening, and depositing a conductive plug, such as tungsten (W) or copper (Cu), to fill the opening. The liner/barrier prevents diffusion of conductive material into the dielectric material layer and enhances adhesion of the conductive plug to the walls of the contact opening.
As the dimensions of contacts/vias decrease, the amount of resistive barrier material, e.g., TiN, inside the contact must be minimized to facilitate better filling and lower contact resistance. However, barrier thickness scaling required for reducing contact resistance is often accompanied by deterioration of barrier properties, i.e., the ability of the barrier to prevent fluorine attack of the underlying Ti during W or Cu deposition resulting in defects, unfilled contacts, increased contact resistance, and reduced device reliability.
Barrier layers are conventionally deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques using metal organic precursors, which results in residual carbon in the deposited layers. The ability of the deposited layer to block fluorine attack of the underlying Ti decreases with increasing carbon content of the deposited layer. Direct and remote plasma treatments in a nitrogen/hydrogen (N2/H2), N2, or H2 ambient have been employed to densify barrier layers.
Direct plasma treatments densify the barrier layers by volatilizing the carbon through direct ionic bombardment. However, due to the directional nature of the plasma, the barrier layer is typically thicker and less densified on the sidewalls as compared to the field area and the contact/via bottom. While increasing plasma power and/or time can further reduce carbon content in the field area and contact/via bottom, it cannot densify the film on the sidewall. This, in turn, leads to defects associated with fluorine attack, and degraded contact resistance and transistor performance. Remote plasma treatments densify the barrier layer isotropically by volatilizing carbon through chemical reactions with radicals created by the plasma. However, in both types of plasma treatments, some residual carbon remains in the barrier layer.
Fluorine attack of the underlying metal containing layer, e.g., Ti, that accompanies a barrier layer thickness reduction, can be mitigated somewhat by increasing the W nucleation thickness. However, the step coverage of W nucleation layers is worse than of bulk CVD W processes, and the resistivity is higher, leading to poor fill, with large seam voids, and high resistance, especially as feature sizes become smaller. Decreasing the temperature of the bulk CVD W fill portion of the process can also result in reduced fluorine attack of the underlying Ti. However, this adversely impacts W grain size and, consequently, contact resistance.
A need therefore exists for methodology enabling a reduction in barrier layer thickness of a contact or via without deteriorating its barrier properties or adversely affecting the contact resistance.
An aspect of the present disclosure is a semiconductor device comprising a metal containing layer with increased density and decreased carbon content.
Another aspect of the present disclosure is a method of fabricating a semiconductor device comprising a metal containing layer with increased density and decreased carbon content.
Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
According to the present disclosure, some technical effects may be achieved in part by a method of fabricating a semiconductor device, the method comprising: depositing a liner/barrier layer, for example, a metal containing layer; and annealing the deposited metal/barrier layer under conditions sufficient to increase the density and decrease the carbon content of the barrier layer.
Aspects of the present disclosure include the liner/barrier layer comprising at least one member selected from the group consisting of Ti, Ta, TiN, TaN, WN, Co, and Ru, for example, a first liner layer comprising Ti, and a second barrier layer thereon comprising TiN. The second barrier layer may alternatively comprise, for example, TaN, WN, Co, or Ru. Further aspects include forming a dielectric layer over a substrate; forming an opening in the dielectric layer; and depositing the liner/barrier layer to line the opening. Another aspect includes depositing the liner/barrierlayer to a thickness of about 5 Å to about 50 Å. Additional aspects include filling the opening by depositing W by CVD employing fluorine-containing tungsten precursors, or by depositing copper (Cu) by CVD employing fluorine-containing Cu precursors, subsequent to annealing. Further aspects include depositing the liner/barrierlayer by CVD or ALD. Another aspect includes annealing the liner/barrierlayer in a non-oxidizing gas atmosphere, e.g., an atmosphere comprising a noble gas, N2, H2, or a forming gas comprising N2 and H2. A further aspect includes annealing the liner/barrierlayer at a temperature of about 100° C. to about 500° C., e.g., at a temperature of about 100° C. to about 400° C. An additional aspect includes performing the deposition and annealing steps in a single chamber with no vacuum break after the deposition.
Another aspect of the present disclosure is a semiconductor device comprising: a dielectric layer; an opening formed in the dielectric layer; an annealed metal containing layer lining the opening; and a conductive material in contact with the annealed metal containing layer filling the opening.
Aspects include the metal containing layer comprising at least one member selected from the group consisting of Ti, TiN, TaN, WN, Co, and Ru. Another aspect includes the metal containing layer comprising a first layer comprising Ti, and a second layer thereon comprising TiN, TaN, WN, Co, or Ru. A further aspect includes the conductive material comprises W or Cu. An additional aspect includes the annealed metal containing layer having a thickness of about 5 Å to about 50 Å.
Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments.
The present disclosure addresses and solves the problem of degradation of metal containing layer barrier properties in contacts/vias as the thickness of the metal containing layer decreases with increasing scalability. In accordance with embodiments of the present disclosure, the metal containing layer is annealed under conditions designed to remove residual carbon and increase its density, thereby decreasing defects and improving its barrier properties. Consequently, a conductive plug subsequently deposited on the metal containing layer to fill the opening exhibits decreased roughness and improved contact resistance.
Methodology in accordance with embodiments of the present disclosure includes depositing a metal containing layer and annealing the deposited metal containing layer under conditions sufficient to increase its density and decrease its carbon content. In this way the thickness of the metal containing layer may be reduced, such as to about 5 Å to about 50 Å, without degrading its barrier properties. The metal containing layer may be formed of Ti, TiN, TaN, WN, Co, and Ru, e.g., a composite comprising a first layer of Ti, and a second layer thereon of TiN, TaN, WN, Co, or Ru. To maintain the conductivity of the layer, the anneal may take place in a non-oxidizing gas atmosphere, such as a noble gas, nitrogen (N2), hydrogen (H2), or a forming gas comprising N2 and H2. A H2 containing atmosphere advantageously results in a reaction between the H2 and the residual carbon to form a hydrocarbon, thereby reducing the amount of residual carbon in the metal containing layer and, hence, improving its barrier properties. In an embodiment, a dielectric layer is formed over a substrate, an opening is formed in the dielectric layer in a conventional manner, and the metal containing layer is deposited, as by CVD or ALD, to line the opening. The opening is then filled by depositing W, as by CVD employing WF6, or by depositing Cu by CVD employing fluorine-containing Cu precursors, subsequent to annealing. Embodiments include annealing at a temperature of about 100° C. to about 500° C., e.g., about 100° C. to about 400° C. By employing low temperature annealing, e.g., below about 400° C., other elements of the semiconductor device are not adversely affected. Other embodiments include conducting deposition and annealing in a single chamber or tool with no vacuum break after the deposition, thereby improving efficiency, reducing the rejection rate, and improving manufacturing throughput.
Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
Adverting to
A metal containing layer is deposited to line the opening (step 205). This lining layer may be formed of Ti, TiN, TaN, WN, Co, or Ru, for example, by initially forming a first layer of Ti followed by a second layer of TiN. The metal lining layer is typically deposited to a thickness of about 5 Å to about 50 Å by CVD or ALD using metal organic precursors, and may be treated by an in situ plasma to reduce carbon content.
In step 207, the metal containing layer is annealed under conditions sufficient to modify its density, and alter its material composition, for example, further reduce its residual carbon content. Annealing may be conducted in a non-oxidizing atmosphere, e.g., nitrogen (N2), hydrogen (H2), a forming gas of N2 and H2, or a noble gas, such as argon Annealing in a H2-containing atmosphere causes a reaction of H2 with the residual carbon to form hydrocarbon(s), thereby reducing the amount of residual carbon in the metal containing layer. The annealing temperature and duration are dependent on the device and the underlying materials, and may range from about 100° C. to about 500° C., for example about 100° C. to about 400° C. Annealing at temperatures below about 400° C. avoids degradation of both metal/high-K gate electrodes and silicide layers in the semiconductor device.
Advantageously, steps 205 and 207 are conducted in the same stand-alone tool with no break in the vacuum between the two steps. In this way, efficiency is improved, defects further minimized, and manufacturing throughput increased.
In step 209, the opening is filled, for example by depositing W by or Cu.
The embodiments of the present disclosure can achieve several technical effects, including improved contact resistance and reliability through improvement in the barrier properties of the liner, potential for improvement in W or Cu nucleation growth rate, uniformity, and reduced film roughness, and improved scalability and extendibility of currently used liner/barrier materials to smaller feature sizes through improvement of barrier properties. This translates to cost savings by postponing the introduction of newer liner materials and the associated process development and integration costs, while the annealing step is low cost and can be done in existing toolsets, such as degas chambers of liner tools and standalone RTP chambers. The present disclosure enjoys industrial applicability in any of various types of highly integrated semiconductor devices.
In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.
