Scan Read Block Wherein a Scan Latch Circuit and a Bit Cell Have Substantially Identical Circuit Structures

Abstract

A scan read block has a relatively short latch circuit and an acceptable noise margin. The scan read block includes a bit cell array and a scan latch block. The bit cell array includes bit cells transmitting data through a corresponding bit line and inverted bit line. The data is transmitted in response to word line scan signals. The scan latch block includes scan latch circuits latching data stored in a corresponding bit cell through the bit lines and the inverted bit lines. In the scan latch block, the scan latch signal is enabled after the word line scan signals are enabled, and thereafter, data of the bit cell array is latched into a corresponding scan latch circuit during a time when the word line scan signals and the scan latch signal are both enabled.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the exemplary embodiments of the present disclosure are described in detail with reference to the attached drawings in which:

FIG. 1 is an embodiment of a conventional scan read block of a semiconductor memory apparatus;

FIG. 2 is a circuit diagram of a bit cell array illustrated in FIG. 1;

FIG. 3 is a circuit diagram of a bit cell illustrated in FIG. 2;

FIG. 4 is a circuit diagram of a latch circuit included in a scan latch circuit illustrated in FIG. 1;

FIG. 5 is a circuit diagram of the latch circuit illustrated in FIG. 4;

FIG. 6 is a circuit diagram of a scan control circuit illustrated in FIG. 1;

FIG. 7 is a circuit diagram of a latch control circuit illustrated in FIG. 1;

FIG. 8 is a scan read block according to an exemplary embodiment of the present invention;

FIG. 9 is a block diagram of a scan latch block illustrated in FIG. 8;

FIG. 10 is a circuit diagram of a scan latch circuit illustrated in FIG. 9;

FIG. 11 is a block diagram of a scan control block illustrated in FIG. 8;

FIG. 12 is a view of a partial layout including the conventional scan read circuit; and

FIG. 13 is a view of a partial layout including a scan read circuit according to an exemplary embodiment of the present invention.

Claims

1. A scan read block comprising: a bit cell array comprising a plurality of bit cells, each of the plurality of bit cells having a corresponding bit line from among a plurality of bit-lines, and a corresponding inverted bit line from among a plurality of inverted bit lines, wherein each of the plurality of bit cells communicates data through the corresponding bit line and the corresponding inverted bit line in response to a corresponding signal from among a plurality of word line scan signals; anda scan latch block comprising a plurality of scan latch circuits, wherein each scan latch circuit latches data stored in a corresponding bit cell through the corresponding bit line and the corresponding inverted bit line in response to a scan latch signal,wherein the scan latch signal is enabled after the plurality of word line scan signals are enabled and data of the bit cell array is latched to a corresponding scan latch circuits during a time when the plurality of word line scan signals and the scan latch signal are both enabled.

2. The scan read block of claim 1, wherein the communication of data through the bit lines by the bit cells comprises inputting the data.

3. The scan read block of claim 1, wherein the communication of data through the bit lines by the bit cells comprises outputting the data.

4. The scan read block of claim 1, wherein the scan latch block includes: a first scan latch circuit latching data of a zero-th bit line and a zero-th inverted bit line output from the bit cell array in response to the scan latch signal; anda second scan latch circuit latching data of a first bit line and a first inverted bit line output from the bit cell array in response to the scan latch signal.

5. The scan read block of claim 4, wherein each of the first and second scan latch circuits has a substantially identical structure as a first bit cell and a second bit cell from among the plurality of bit cells.

6. The scan read block of claim 5, wherein each of the first and second scan latch circuits comprises: a latch circuit storing and communicating data through two input/output terminals;a first switch switching between the corresponding bit line and one of the input/output terminals of the latch circuit in response to the scan latch signal; anda second switch switching between the corresponding inverted bit line and the other of the input/output terminals of the latch circuit in response to the scan latch signal.

7. The scan read block of claim 6, wherein the latch circuit comprises: a first inverter of which an input terminal is connected to one terminal of the latch circuit, and an output terminal is connected to the other terminal of the latch circuit; anda second inverter of which an input terminal is connected to the output terminal of the first inverter, and an output terminal is connected to the input terminal of the first inverter.

8. The scan read block of claim 6, wherein the first switch is a first MOS transistor of which a drain terminal is connected to a corresponding bit line, and a source terminal is connected to one of the input/output terminals of the latch circuit and a gate terminal receives the scan latch signal; andthe second switch is a second MOS transistor of which a drain terminal is connected to a corresponding inverted bit line, a source terminal is connected to the other of the input/output terminals of the latch circuit, and a gate terminal receives the scan latch signal.

9. The scan read block of claim 6, wherein the first switch is a first MOS transistor of which a source terminal is connected to a corresponding bit line, and a drain terminal is connected to one of the input/output terminals of the latch circuit and a gate terminal receives the scan latch signal; andthe second switch is a second MOS transistor of which a source terminal is connected to a corresponding inverted bit line, a drain terminal is connected to the other of the input/output terminals of the latch circuit, and a gate terminal receives the scan latch signal.

10. The scan read block of claim 6, wherein the scan latch circuit further comprises: a third inverter of which a corresponding input terminal receives an output signal of one of the input/output terminals of the latch circuit; anda fourth inverter of which a corresponding input terminal receives an output signal of the other of the input/output terminals of the latch circuit.

11. The scan read block of claim 1, further comprising a scan control block outputting corresponding word line scan signals from among the plurality of word line scan signals and the scan latch signal in response to a plurality of word line selection signals, a latch signal, and an enable signal.

12. The scan read block of claim 11, wherein the scan control block comprises: a latch control circuit outputting the scan latch signal in response to the enable signal and the latch signal;a zero-th control circuit outputting a zero-th word line scan signal in response to the enable signal and the zero-th word line selection signal; anda first control circuit outputting a first word line scan signal in response to the enable signal and the first word line selection signal.

13. The scan read block of claim 12, wherein each of the latch control circuit, the zero-th control circuit and the first control circuit comprises a two-input NAND gate.

14. A scan read block comprising: a bit cell array comprising a plurality of bit cells, each of the plurality of bit cells having a corresponding bit line from among a plurality of bit lines, and a corresponding inverted bit line from among a plurality of inverted bit lines, wherein each of the plurality of bit cells communicates data through the corresponding bit line and the corresponding inverted bit line in response to a corresponding signal from among a plurality of word line scan signals;a scan latch block comprising a plurality of scan latch circuits, wherein each scan latch circuit latches data stored in a corresponding bit cell through the corresponding bit line and the corresponding inverted bit line in response to a scan latch signal;a latch control circuit outputting the scan latch signal in response to an enable signal and a latch signal; anda plurality of scan control circuits outputting the plurality of word line scan signals in response to the enable signal and a plurality of word line selection signals,wherein the scan latch signal is enabled after the plurality of word line scan signals are enabled, and data of the bit cell array is latched into a corresponding scan latch circuit during a time when the plurality of word line scan signals and the scan latch signal are both enabled.

15. The scan read block of claim 14, wherein the communication of data through the bit lines by the bit cells comprises inputting the data.

16. The scan read block of claim 14, wherein the communication of data through the bit lines by the bit cells comprises outputting the data.

17. The scan read block of claim 14, wherein structures of the scan latch circuit and the bit cell are substantially identical.

18. The scan read block of claim 14, wherein structures of the scan control circuit and the latch control circuit are substantially identical.

19. A semiconductor memory apparatus comprising the scan read block of claim 14.