SEAL RING STRUCTURES WITH UNLANDED VIA STACKS

Abstract

Techniques for an integrated circuit device are provided. The integrated circuit device includes a semiconductor substrate, an integrated circuit, a dielectric layer, and a sealing structure. The sealing structure surrounds the integrated circuit and is disposed within the dielectric layer to prevent damage to the integrated circuit. The sealing structure includes a plurality of metal traces organized in vertical layers and a plurality of vias. Each via of the plurality of vias couples at least two metal traces of the plurality of metal traces from adjacent vertical layers. Each via of the plurality of vias contacts at least two orthogonal surfaces of a lower metal trace of the at least two metal traces. The plurality of metal traces and plurality of vias form a continuous boundary.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified diagrams illustrating an integrate circuit device according to an embodiment of the present invention;

FIGS. 2A-2C illustrate simplified diagrams of a seal structure according to an embodiment of the present invention; and

FIG. 3 illustrates a simplified diagram of a seal structure according to an embodiment of the present invention.

Claims

1. An integrated circuit device, the device comprising: a semiconductor substrate;an integrated circuit;a dielectric layer; anda sealing structure surrounding the integrated circuit and disposed within the dielectric layer to prevent damage to the integrated circuit, the sealing structure comprising:a plurality of metal traces organized in vertical layers; anda plurality of vias, each via of the plurality of vias couples at least two metal traces of the plurality of metal traces from adjacent vertical layers, and each via of the plurality of vias contacts at least two orthogonal surfaces of a lower metal trace of the at least two metal traces,wherein the plurality of metal traces and plurality of vias form a continuous boundary in the dielectric layer.

2. The device of claim 1 wherein the dielectric layer comprises at least one of PECVD silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, flowable oxide, BPSG, BSG, PSG, carbon doped silicon oxide, Black Diamond low k film, Corel CVD dielectric, SiLK dielectric resin, and Aurora low-k dielectric.

3. The device of claim 1 wherein the sealing structure forms at least one of a square, rectangle, rounded corner rectangle, oval, circle, and polyon around the integrated circuit.

4. The device of claim 1 further comprising a buffer region in the dielectric layer between the integrated circuit and the sealing structure.

5. The device of claim 4 wherein the buffer region extends at least about 1 micron.

6. The device of claim 1 wherein the plurality of metal traces each comprises at least one of copper, aluminum, tungsten, and polysilicon.

7. The device of claim 1 wherein the plurality of vias each comprises at least one of copper, aluminum, tungsten, and polysilicon.

8. The device of claim 1 wherein the plurality of vias each directly couple to at least 20% of a top surface of the two orthogonal surfaces.

9. The device of claim 8 wherein the plurality of vias each directly couple to at least 10% of a second surface of the two orthogonal surfaces.

10. The device of claim 1 further comprising a barrier layer between the dielectric layer and each of the plurality of metal traces and plurality of vias.

11. The device of claim 10 wherein the barrier layer comprises at least one of Ta and TaNi.

12. The device of claim 1 wherein the sealing structure is a first sealing structure, and a second sealing structure is disposed between the first sealing structure and the integrated circuit.

13. The device of claim 1 wherein a portion of the sealing structure abuts a sawing trace.

14. The device of claim 1 wherein the sealing structure is disposed about 0 microns to about 10 microns from a sawing trace.

15. An integrated circuit device, the device comprising: a semiconductor substrate;an integrated circuit;a dielectric layer; anda sealing structure surrounding the integrated circuit and disposed within the dielectric layer, the sealing structure comprising:a first metal trace;a second metal trace, the second metal trace underlying a portion of the first metal trace; anda via coupling the first metal trace to the second metal trace,wherein the via is coupled to a first surface of the second metal trace and a second surface of the second metal trace, andthe first surface and the second surface are orthogonal.

16. The device of claim 15 further comprising a barrier layer between the dielectric layer and each of the first metal trace, second metal trace, and the via.

17. The device of claim 16 wherein the barrier layer comprises at least one of Ta and TaNi.

18. The device of claim 15 wherein the dielectric layer comprises at least one of PECVD silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, flowable oxide, BPSG, BSG, PSG, carbon doped silicon oxide, Black Diamond low k film, Corel CVD dielectric, SiLK dielectric resin, and Aurora low-k dielectric.

19. The device of claim 15 wherein the sealing structure forms at least one of a square, rectangle, rounded corner rectangle, oval, circle, and polyon around the integrated circuit.

20. The device of claim 15 further comprising a buffer region in the dielectric layer between the integrated circuit and the sealing structure.

21. The device of claim 20 wherein the buffer region extends at least about 1 micron from the integrated circuit and the sealing structure.

22. The device of claim 15 wherein the first metal trace, second metal trace, and via each comprises at least one of copper, aluminum, tungsten, and polysilicon.

23. The device of claim 15 wherein the via is directly coupled to at least 20% of the first surface, the first surface being a top surface of the second metal trace.

24. The device of claim 15 wherein the via is directly coupled to at least 10% of the second surface, the second surface being a surface orthogonal to a top surface of the second metal trace.

25. The device of claim 15 wherein the sealing member further comprises: a third metal trace overlying a portion of the first metal trace; anda second via coupling the third metal trace to the first metal trace, whereinwherein the second via is coupled to a first surface of the first metal trace and a second surface of the first metal trace, andthe first surface and the second surface are orthogonal.

26. The device of claim 15 wherein the sealing structure is a first sealing structure, and a second sealing structure is disposed between the first sealing structure and the integrated circuit.

27. The device of claim 15 wherein a portion of the sealing structure abuts a sawing trace.

28. The device of claim 15 wherein the sealing structure is disposed about 0 microns to about 10 microns from a sawing trace.

29. An integrated circuit device, the device comprising: a semiconductor substrate;an integrated circuit; anda sealing structure disposed around the integrated circuit, the sealing structure comprising:a first metal trace;a second metal trace, the second metal trace underlying the first metal trace;a via disposed between the first metal trace and second metal trace; anda portion of the via disposed beyond a distal surface of the second metal trace and below a top surface of the second metal trace, the distal surface and the top surface of the second metal trace being orthogonal,wherein the via couples a bottom surface of the first metal trace to both the top and distal surfaces and the distal of the second metal trace.