The present invention relates generally to a junction gate field-effect transistor (JFET), and particularly to a compact trench JFET and methods of production thereof.
A conventional n-channel junction gate field-effect transistor (JFET) 100, as shown in
In addition, a source metal 112 is provided above the oxide layers 114 and a tungsten plug 110. The tungsten plug 110 is used to connect the N+ material in the source region 102 and the source metal 112.
In addition, a source metal 112 is provided above the oxide layers 114 and a tungsten plug 110. The tungsten plug 110 is used to connect the N+ material in the source region 102 and the source metal 112. There are also contact areas between the source region 102, the drain 118, and the gate region 104.
The critical dimension of the JFET is the gate length d. This gate length d limits the performance of conventional JFET devices, since channel length is substantially larger than the minimum gate length size. In addition, the capacitances of the vertical sidewalls of the gate diffusion to drain and source regions are also quite large.
Thus, it would be advantageous to provide a JFET in which a minimum distance between the source region and drain could be maintained while the overall size of the JFET is reduced.
According to one embodiment, a self-aligned trench structure junction gate field-effect transistor (JFET) includes a silicon substrate, two or more trenches having a P-type polysilicon gate region near a bottom portion of the trench and an interlayer dielectric layer (ILDL) above the P-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, an N+ source region above the channel region extending between a top of each trench, and a source metal above the N+ source region.
In another embodiment, a self-aligned trench structure JFET includes a silicon substrate, two or more trenches having an N-type polysilicon gate region near a bottom portion of the trench and an ILDL above the N-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, a P+ source region above the channel region extending between a top of each trench, and a source metal above the P+ source region.
In accordance with another embodiment, a method for producing a self-aligned trench structure JFET includes applying a mask to a substrate wherein the mask leaves portions of the substrate exposed, forming a trench in the exposed portions of the substrate, implanting a dopant into a bottom portion of the trench to form a P+ region, removing the mask, depositing a polysilicon into the trench, removing the polysilicon deposited above the top surface of the substrate, etching the polysilicon in the trench such that the polysilicon is recessed from a top surface of the substrate, depositing an ILDL into the trench above the polysilicon, forming a N+ source layer above the top surface of the substrate, and forming a source metal layer above the N+ source layer.
In another embodiment, a method for producing a self-aligned trench structure JFET includes applying a mask to a substrate wherein the mask leaves portions of the substrate exposed, forming a trench in the exposed portions of the substrate, implanting a dopant into a bottom portion of the trench to form a N+ region, removing the mask, depositing a polysilicon into the trench, removing the polysilicon deposited above the top surface of the substrate, etching the polysilicon in the trench such that the polysilicon is recessed from a top surface of the substrate, depositing an ILDL into the trench above the polysilicon, forming a P+ source layer above the top surface of the substrate, and forming a source metal layer above the P+ source layer.
The present invention can be further understood with reference to the following detailed description and the appended drawings, wherein like elements are provided with like reference signs.
One problem associated with conventional junction gate field-effect transistors (JFETs) is in maintaining enough breakdown voltage, which forces the N+ of the source region to be far enough away from the P-type polysilicon of the gate region. If the N+ source region is too close, the voltage sustained by the channel in between is too little. Because of this, conventional JFETs had to be very big.
According to one general embodiment, a self-aligned trench structure junction gate field-effect transistor (JFET) includes a silicon substrate, two or more trenches having a P-type polysilicon gate region near a bottom portion of the trench and an interlayer dielectric layer (ILDL) above the P-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, an N+ source region above the channel region extending between a top of each trench, and a source metal above the N+ source region.
In another general embodiment, a self-aligned trench structure JFET includes a silicon substrate, two or more trenches having an N-type polysilicon gate region near a bottom portion of the trench and an ILDL above the N-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, a P+ source region above the channel region extending between a top of each trench, and a source metal above the P+ source region.
In accordance with another general embodiment, a method for producing a self-aligned trench structure JFET includes applying a mask to a substrate wherein the mask leaves portions of the substrate exposed, forming a trench in the exposed portions of the substrate, implanting a dopant into a bottom portion of the trench to form a P+ region, removing the mask, depositing a polysilicon into the trench, removing the polysilicon deposited above the top surface of the substrate, etching the polysilicon in the trench such that the polysilicon is recessed from a top surface of the substrate, depositing an ILDL into the trench above the polysilicon, forming a N+ source layer above the top surface of the substrate, and forming a source metal layer above the N+ source layer.
In another general embodiment, a method for producing a self-aligned trench structure JFET includes applying a mask to a substrate wherein the mask leaves portions of the substrate exposed, forming a trench in the exposed portions of the substrate, implanting a dopant into a bottom portion of the trench to form a N+ region, removing the mask, depositing a polysilicon into the trench, removing the polysilicon deposited above the top surface of the substrate, etching the polysilicon in the trench such that the polysilicon is recessed from a top surface of the substrate, depositing an ILDL into the trench above the polysilicon, forming a P+ source layer above the top surface of the substrate, and forming a source metal layer above the P+ source layer.
As illustrated in
Referring again to
Referring again to
In one approach, the source metal 212 may comprise aluminum and/or compounds thereof. In addition, a barrier metal layer (not shown) may be formed between the source region 202 and the source metal 212. The barrier metal layer may be comprised of any suitable material as would be known to one of skill in the art. For example, for a silicon/aluminum interface, the barrier metal layer may comprise titanium nitride, e.g., a thin layer of titanium on the source region 202, with a titanium nitride layer on the thin titanium layer, the titanium nitride layer contacting the source metal 212. Other barrier metals may be selected depending on the materials used for the source metal 212 and the source region 202, in various combinations. The barrier metal layer is intended to improve the contact 210 and reduce stress levels, in preferred embodiments.
In another embodiment, when the source metal 212 is an aluminum silicon copper alloy or some other alloy that can avoid spiking, the barrier metal layer may be omitted.
In more embodiments, the N+ source region 202 may comprise silicon in a compound having one or more of arsenic, phosphorous, antimony, etc. According to one embodiment, silicon is doped with a secondary element, such as arsenic, phosphorous, antimony, etc., in order to form a compound thereof.
According to one embodiment, the N epitaxial layer 220 may comprise epitaxial silicon or a compound thereof, silicon composites, silicon alloys, gallium composites, gallium nitrides, etc., such as silicon germanium (binary compound), silicon carbide (particularly for high voltage applications), gallium nitride, etc., according to various embodiments. In addition, the N+ substrate drain 218 may comprise silicon or a compound thereof having a slightly higher density that the N epitaxial layer 220.
In another embodiment, the oxide layer 214 may comprise silicon oxide formed through any method known in the art, such as thermally grown, deposited, etc.
The P+ region 206 may comprise silicon implanted with an element causing it to become P-type, such as boron, according to one embodiment. The element may be implanted via ion bombardment, according to one embodiment.
According to some embodiments, preferred dimensions may include some or all of the following illustrative dimensions. These dimensions are not meant to be limiting on the scope of the invention in any way, and are illustrative only.
In one embodiment, the depth of the trench 216 may be from about 0.5 micron to about 3 microns. In another embodiment, the width of the trench 216 may be from about 0.1 micron to about 0.5 micron, such as about 0.25 micron. According to various embodiments, an aspect ratio (depth/width) of the trench 216 may be about 10 or greater, such as 12, 15, 20, etc.
In addition, in some embodiments, the trench 216 has walls which are non-parallel, thereby creating a trench 216 which does not have vertical walls. For example, the walls may be tapered outward from vertical from a bottom of the trench 216 to a top of the trench 216, making it easier to fill the trench 216 with material during formation of the JFET 200, as a top of the trench 216 is wider than a bottom of the trench 216.
Additionally, a depth of the oxide layer 214 may correspond to a voltage region of the JFET 200. Therefore, the oxide layer 214 depth may vary depending on the voltage rating of the JFET 200. According to preferred embodiments, a thinnest oxide layer 214 that still provides a desired voltage rating of the JFET 200 may be used. As the desired voltage rating increases, the depth of the oxide layer 214 may also increase to provide this desired voltage capability.
In more embodiments, a thickness of the N+ source region 202 may be from about 0.1 micron to about 2 microns, depending on the desired breakdown voltage and materials of construction. In a further embodiment, the thickness of the N+ source region 202 may be about 0.25 micron.
Any of the layers described above may be deposited using any method known in the art, such as chemical vapor deposition (CVD), plasma enhanced vapor deposition (PEVD), sputtering, plating, etc.
According to various embodiments, N- and P-regions may be reversed. For example, the N-regions shown in
Now referring to
In operation 302, a mask is applied to a substrate leaving portions of the substrate exposed. The mask may be comprised of any material known in the art, and may be a hard mask or a soft mask, according to various embodiments.
In operation 304, a trench is formed in the exposed portions of the substrate. The trench may be formed via any technique known in the art, such as etching (dry or wet), milling, etc. In some embodiments, the trench may be formed to a depth of greater than about 0.5 micron and less than about 3 microns.
In operation 306, a dopant is implanted into a bottom portion of the trench to form a P+ region. Any technique known in the art may be used to implant the dopant, such as ion bombardment. The dopant, according to one embodiment, may comprise boron. According to some embodiments, bottom portions of walls of the trench may also be implanted with the dopant along with the bottom portion of the trench.
In operation 308, the mask is removed. Any method may be used to remove the mask as would be known to one of skill in the art, such as stripping, dissolving, etc.
In operation 310, a polysilicon is deposited into the trench. During this process, the polysilicon may be deposited full film, thereby also being deposited onto the top surface of the substrate.
According to one embodiment, the polysilicon, when deposited, may be P-type polysilicon. In an alternate embodiment, the polysilicon may be undoped when deposited, and then doped to make it P-type after being deposited into the trench. If the polysilicon is deposited undoped, the doping of the top surface of the substrate is minimal, and therefore does not adversely affect the performance of the JFET when formed.
In operation 312, the polysilicon deposited above the top surface of the substrate is removed. Any technique known in the art may be used to remove the polysilicon, such as a blank etch, chemical mechanical polish (CMP), etc.
In operation 314, the polysilicon in the trench is etched such that the polysilicon is recessed from the substrate. Any etching technique may be used as known in the art, as well as any other technique for removal of the polysilicon from the trench, as would be known to one of skill in the art.
In operation 316, an interlayer dielectric layer (ILDL) is deposited into the trench such that the ILDL fills the remaining portion of the trench. Any method known in the art may be used to deposit the ILDL, such as sputtering, CVD, PEVD, etc.
In some embodiments, the ILDL may be a silicon oxide or any other oxide of the substrate material.
In operation 318, an N+ source layer is formed above the top surface of the substrate. Any method known in the art may be used to form the N+ source layer, such as ion bombardment, doping, etc. In some embodiments, areas above the ILDL may also be doped N+, but this is not necessary or harmful to the performance of the JFET.
In operation 320, a source metal layer is formed above the N+ source layer. Any method known in the art may be used to deposit the source metal layer, such as sputtering, CVD, PEVD, etc.
According to preferred embodiments described herein, for a JFET rated at 100 volts, RDS×A (Resistance when on (Ω)×Contact Area) may be more than about 5 times less than that of a comparable JFET produced through conventional methods.
The above detailed description of embodiments of the present invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
The terminology used in the Detailed Description is intended to be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific embodiments of the invention. Certain terms may even be emphasized; however, any terminology intended to be interpreted in any restricted manner will be overtly and specifically defined as such in this Detailed Description section. In general, the terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification, unless the above Detailed Description section explicitly defines such terms. Accordingly, the actual scope of the invention encompasses not only the disclosed embodiments, but also all equivalent ways of practicing or implementing the invention under the claims.