Patent Application
20070123053
The present invention relates to the formation of semiconductor devices.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes, a photoresist (PR) material is deposited on the wafer and then is exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials, the exposed regions are removed, and in the case of negative photoresist materials, the unexposed regions are removed. Thereafter, the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material, and thereby define the desired features in the wafer.
Various generations of photoresist are known. The photoresist patterns have a critical dimension (CD), which may be the width of the smallest feature. Due to optical properties dependent on wavelength, photoresist exposed by longer wavelength light has larger theoretical minimal critical dimensions. Features are etched through the photoresist pattern. Ideally, the CD of the features (the width of the features) is equal to the CD of the feature in the photoresist. In practice, the CD of the feature may be larger than the CD of the photoresist due to faceting, erosion of the photoresist, or undercutting. The feature may also be tapered, where the CD of the feature is at least as great as the CD of the photoresist, but where the feature tapers to have a smaller width near the feature bottom. Such tapering may provide unreliable features.
In order to provide features with smaller CD, features formed using shorter wavelength light are being pursued. 193 nm photoresist is exposed by 193 nm light. Using phase shift reticles and other technology, a 90-100 nm CD photoresist pattern may be formed, using 193 nm photoresist. This would be able to provide a feature with a CD of 90-100 nm. 157 nm photoresist is exposed by 157 nm light. Using phase shift reticles and other technology sub 90 nm CD photoresist patterns may be formed. This would be able to provide a feature with a sub 90 nm CD.
The use of shorter wavelength photoresists may provide additional problems over photoresists using longer wavelengths. To obtain CD's close to the theoretical limit the lithography apparatus should be more precise, which would require more expensive lithography equipment. Presently 193 nm photoresist and 157 nm photoresist may not have selectivities as high as longer wavelength photoresists and may more easily deform under plasma etch conditions.
In the etching of conductive layers, such as in the formation of memory devices, it is desirable to increase device density
To achieve the foregoing and in accordance with the purpose of the present invention a method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A patterned mask is formed over the sacrificial layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The features of the first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, wherein spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer, wherein the spaces have widths. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
In another manifestation of the invention, a method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A patterned mask is formed over the sacrificial layer. A set of sacrificial layer features is etched into the sacrificial layer. The sacrificial layer features are shrunk by forming a shrink deposition, comprising at least one cycle, wherein each cycle comprises a shrink deposition phase, which forms deposits on sidewalls of the sacrificial layer features to shrink the sacrificial layer features and a shrink profile shaping phase, which shapes the deposition on the sidewalls of the sacrificial layer features. A first set of dielectric layer features is etched into the dielectric layer through the shrink deposition. The shrink deposition is removed. The features of the first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, wherein spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer, wherein the spaces have widths. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition, wherein the shrinking the widths of the spaces comprises at least one shrink cycle, wherein each shrink cycle comprises a shrink deposition phase, which forms deposits on sidewalls of the filler material to shrink the spaces and a shrink profile shaping phase, which shapes the deposition on the sidewalls of the filler material. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
In another manifestation of the invention, an apparatus for forming features in a dielectric layer over which a sacrificial layer under a patterned mask has been placed is provided. A plasma processing chamber, comprising a chamber wall forming a plasma processing chamber enclosure, a substrate support for supporting a substrate within the plasma processing chamber enclosure, a pressure regulator for regulating the pressure in the plasma processing chamber enclosure, at least one electrode for providing power to the plasma processing chamber enclosure for sustaining a plasma, a gas inlet for providing gas into the plasma processing chamber enclosure, and a gas outlet for exhausting gas from the plasma processing chamber enclosure is provided. A gas source in fluid connection with the gas inlet and comprises a sacrificial layer etchant source, a dielectric layer etchant source, a shrink deposition gas source, and a shrink profile shaping gas source. A controller controllably is connected to the gas source and the at least one electrode and comprises at least one processor and computer readable media. The computer readable media comprises computer readable code for etching sacrificial layer features into the sacrificial layer without etching the dielectric layer, computer readable code for shrinking the sacrificial layer features with a sacrificial layer sidewall deposition, computer readable code for etching a first set of dielectric features into the dielectric layer through the sacrificial layer sidewall deposition, computer readable code for removing the sacrificial layer sidewall deposition, wherein the features are subsequently filled with a filler material, computer readable code for removing the sacrificial layer, so that parts of the filler material remain exposed above a surface of the dielectric layer, wherein spaces are between the exposed parts of the filler material, computer readable code for shrinking widths of the spaces between parts of the filler material with a shrink deposition, comprising at least one cycle, wherein each cycle comprises computer readable code for providing a shrink deposition gas from the shrink deposition gas source, computer readable code for generating a plasma from the shrink deposition gas, computer readable code for stopping the shrink deposition gas from the shrink deposition gas source, computer readable code for providing a shrink profile shaping gas from the shrink profile shaping gas source, computer readable code for generating a plasma from the shrink profile shaping gas, and computer readable code for stopping the shrink profile shaping gas from the shrink profile shaping gas source, and computer readable code for etching a second set of features into the dielectric layer through the shrink deposition.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
FIGS. 2A-L are schematic cross-sectional and top views of a stack processed according to an embodiment of the invention.
FIGS. 5A-B illustrate a computer system, which is suitable for implementing a controller used in embodiments of the present invention.
The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention.
To facilitate understanding,
A mask 214 is formed over the sacrificial layer (step 108), as shown in
CPU 1322 is also coupled to a variety of input/output devices, such as display 1304, keyboard 1310, mouse 1312, and speakers 1330. In general, an input/output device may be any of: video displays, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, biometrics readers, or other computers. CPU 1322 optionally may be coupled to another computer or telecommunications network using network interface 1340. With such a network interface, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments of the present invention may execute solely upon CPU 1322 or may execute over a network such as the Internet in conjunction with a remote CPU that shares a portion of the processing.
In addition, embodiments of the present invention further relate to computer storage products with a computer-readable medium that have computer code thereon for performing various computer-implemented operations. The media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts. Examples of computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and ROM and RAM devices. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.
Preferably, the shrink deposition phase (step 304) uses a deposition gas comprising at least one of a combination of CF4 and H2 or a combination of CH3F and N2 or CxFy or CxHyFz with an oxidizing or reducing additive such as hydrogen, nitrogen, or oxygen, and carrier gases such as He, Ar, Ne, Kr, Xe etc. More generally, the deposition gas comprises at least one of hydrocarbon, fluorocarbon, and hydrofluorocarbon. More preferably, the deposition gas further comprises a carrier gas, such as argon or xenon. More preferably, the deposition gas further comprises at least one of an oxidizing additive and a reducing additive, such as O2, H2, or NH3.
An example of a shrink deposition phase (step 304) provides a flow of 150 sccm CH3F, 75 sccm N2, and 100 sccm Ar. The pressure is set to 80 mTorr. The substrate is maintained at a temperature of 20° C. The second RF source 448 provides 400 Watts at a frequency of 27 MHz and 0 Watts a frequency of 2 MHz. During the deposition phase the deposition gas is provided, the deposition gas is transformed into a plasma, and then the deposition gas is stopped.
Preferably, the shrink profile shaping stage uses a profile shaping gas different from the deposition gas and comprising at least one of CxFy and NF3 and CxHyFz. More preferably, the profile shaping gas further comprises a carrier gas, such as argon or xenon. More preferably, the profile shaping gas further comprises at least one of an oxidizing additive and a reducing additive, such as O2, H2, or NH3.
An example of the shrink profile shaping phase (step 308) provides a halogen (i.e. fluorine, bromine, chlorine) containing gas, such as 100 sccm CF4. In this example, CF4 is the only gas provided during the profile shaping. A pressure of 20 mTorr is provided to the chamber. The second RF source 448 provides 600 Watts at a frequency of 27 MHz and 0 Watts a frequency of 2 MHz. During the profile shaping phase the profile shaping gas is provided, the profile shaping gas is transformed into a plasma, and then the profile shaping gas is stopped.
Preferably, the process is performed for between 2 to 20 cycles. More preferably, the process is performed between 3 to 10 cycles. The combination of deposition and profile shaping over a plurality of cycles allows for the formation of vertical sidewalls for the shrink. Preferably, the vertical sidewalls are sidewalls that from bottom to top make an angle between 88° to 90° with the bottom of the sacrificial layer feature.
Preferably, the shrink sidewalls cause widths of the sacrificial layer features to be reduced by between 5-80%. More preferably, the shrink sidewalls cause the widths of the sacrificial layer features to be reduced by between 5-50%. The cyclical cycle may have additional deposition and/or shaping phases or may have other additional phases.
In another embodiment, the shrink may be made of features in the photoresist mask before the sacrificial layer is etched. In such a case, the etching of the sacrificial layer and the dielectric layer may be done in a single step or in separate steps.
Features 220 of a first set of features are then etched into the dielectric layer 208 through the shrunken features in the sacrificial layer and patterned mask 214 the (step 120), as shown in
The patterned mask and shrink sidewall is stripped (step 124), as shown in
The features are then filled with a filler material 224 (step 128), as shown in
The filler material 224 is planarized (step 132) as shown in
In an alternative embodiment, a cyclical process of deposition and shaping phases may be used to fill the features with a filler material and planarize and expose the sacrificial layer in a single step. Other processes may be used to replace steps 128 and 132 with a single step.
The sacrificial layer is removed (step 136), as shown in
As a result of the removal of the sacrificial layer, parts of the filler material 224 extend above the surface of the dielectric layer 208, where spaces 217 are formed between the parts of the filler material 224 that extend above the surface of the dielectric layer 208, where the spaces 217 are in the area formerly occupied by the sacrificial layer. The spaces 217 have widths “w1”, as shown in
The spaces between the polymer material 224 are shrunk (step 140), as shown in
Features 236 of a second set of features are etched into the dielectric layer 208 through the reduced spaces between the shrink sidewalls 228, as shown in
The filler material and shrink sidewall of the filler material are removed (step 148) as shown if
The table below provides various combinations of sacrificial layer materials and filler materials. Duo is a hydrocarbon material with silicon. The organic polymer may be amorphous carbon, photoresist, or bottom antireflective coating (BARC). The combinations allow the sacrificial layer to be selectively removed with respect to the filler material and dielectric layer using either a plasma etch or wet strip and the filler material to be selectively removed with respect to the dielectric layer using an oxidizing, reducing, or wet strip.
In this example, an O2 plasma strip is used to remove the polymer filler material.
In this example, individual features 220 of the first set of features are between features 236 of the second set of features and where features 236 of the second set of features are between features 220 of the first set of features, so that features alternate between, a feature 220 of the first set of features and a feature 236 of the second set of features. In addition, features 220 of the first set of features are separated from features 236 of the second set of features by the dielectric material of the dielectric layer.
Additional steps, such as filling the features with a conductive material may be provided.
This process provides etched features with half the CD and half the pitch of features formed using the same photoresist mask using a conventional etch process. This process allows the use of a single photoresist mask to halve the pitch, while providing an automatic alignment between the first set of features and the second set of features.
Some of the steps in the above preferred embodiment may be omitted or changed without increasing CD and/or increasing the pitch. Other steps in the preferred embodiment may be omitted or changed, but which still reduces the CD and/or reduces pitch with respect to conventional processes.
In other embodiments, the process is repeated using additional masks to further reduce CD and reduce the pitch. For an example, a second mask may be used for another half pitch reduction.
While this invention has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents, which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present invention.
