Patent Application
20120146150
1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection of integrated circuits and, more specifically, to a self-protected electrostatic discharge field effect transistor (SPESDFET), to an integrated circuit incorporating the SPESDFET as an input/output (I/O) pad driver and to methods of forming the SPESDFET and the integrated circuit.
2. Description of the Related Art
An electrostatic discharge (ESD) event may cause extremely high currents to flow through the semiconductor devices in an integrated circuit and, thereby cause device junctions, gate oxides, and other adjacent structures to be permanently damaged. As device sizes are decreased and device density is increased with technology scaling, it has become increasingly challenging to achieve adequate protection against such ESD damage. For example, with older technologies, a single silicided N-type field effect transistor (NFET) alone could adequately function as an input/output (I/O) pad driver, providing the necessary protection against ESD discharge. However, with technology scaling, such a single silicided NFET is no longer robust against ESD discharge.
In view of the foregoing disclosed herein are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.
More particularly, disclosed herein are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). This SPESDFET can comprise a semiconductor layer, having a top surface; an isolation structure in the semiconductor layer at the top surface; and gate structure on the top surface of the semiconductor layer offset from the isolation structure.
The semiconductor layer can comprise a channel region, shallow source/drain extension regions, and deep source drain regions. The channel region can be positioned below the gate structure. The shallow source/drain extension regions can be positioned on opposing sides of the channel region. Specifically, each shallow source/drain extension region can extend vertically from the top surface of the semiconductor layer to a first depth below the top surface and can comprise a first end portion adjacent to the channel region, a second end portion adjacent to the isolation structure and a center portion positioned laterally between the first end portion and the second end portion. The deep source/drain regions can also be positioned on opposing sides of the channel region. Specifically, each deep source/drain region can comprise a first section and a second section. The first section can be positioned adjacent to the channel region and can extend vertically through the first end portion of a corresponding shallow source/drain extension region to a second depth that is below the first depth. The second section can be positioned adjacent to the isolation structure and can extend vertically through the second portion of the corresponding shallow source/drain extension region, also to the second depth.
The SPESDFET can further comprise first and second dielectric layers and a metal silicide layer. The first dielectric layer can be positioned on the top surface of the semiconductor layer abutting the center portion of the shallow source/drain extension region only (i.e., above the resistance region only). The second dielectric layer can be on the top surface of the semiconductor layer abutting and cover the first section of the deep source/drain region. Finally, the metal silicide layer can be positioned on the top surface of the semiconductor layer abutting the second section of the deep source/drain region. However, the first section of the deep source/drain region adjacent to the channel region and the center portion of the shallow source/drain extension region (i.e., the resistance region) are non-silicided due to blocking, during the silicide formation process, by the first and second dielectric layers.
Also disclosed herein are embodiments of an integrated circuit. This integrated circuit can comprise an input/output (I/O) pad and an input/output (I/O) pad driver connected in series between the input/output (I/O) pad and ground. In this case, the input/output (I/O) pad driver can comprise a single N-type SPESDFET configured as described above.
Also disclosed herein are embodiments of a method of forming the above-described SPESDFET. The method embodiments can comprise providing a semiconductor layer. An isolation structure can be formed in the semiconductor layer at the top surface. Then, a gate structure can be formed on the top surface of the semiconductor layer offset from the isolation structure and above a designated channel region.
After the gate structure is formed, shallow source/drain extension regions can be formed on opposing sides of the channel region. Specifically, each shallow source/drain extension region can be formed so as to extend vertically from the top surface of the semiconductor layer to a first depth below the top surface. Then, a first dielectric layer can be formed so as to cover a center portion only of the shallow source/drain extension region. This center portion can be positioned laterally between a first end portion, which is adjacent to the channel region, and a second end portion, which is adjacent to the isolation structure. Next, deep source/drain regions can be formed on opposing sides of the channel region. Specifically, each deep source/drain region can be formed so as to comprise a first section and a second section. The first section can be adjacent to the channel region and can extend vertically through the first end portion of the shallow source/drain extension region to a second depth below the first depth. The second section can be adjacent to the isolation structure and can extend vertically through the second end portion of the shallow source/drain extension region to the second depth. After the deep source/drain regions are formed, a second dielectric layer can be formed so as to cover at least the first section of the deep source/drain region. Then, a metal silicide layer can be formed on the second section. During the process, the first and second dielectric layers block silicide formation on the first section of the deep source/drain region adjacent to the channel region and on the center portion of the shallow source/drain extension region (i.e., on the resistance region).
Also disclosed are embodiments of a method of forming such an integrated circuit. Specifically, the method embodiments can comprise providing a semiconductor layer. An N-type SPESDFET can be formed, in the manner described above, on the semiconductor layer. Then, an input/output (I/O) pad can be formed on the semiconductor layer and the N-type SPESDFET can be electrically connected in-series between the input/output (I/O) pad and ground so that the SPESDFET can function as an input/output (I/IO) pad driver.
The embodiments disclosed herein will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:
The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description.
As mentioned above, an electrostatic discharge (ESD) event may cause extremely high currents to flow through the semiconductor devices in an integrated circuit and, thereby cause device junctions, gate oxides, and other adjacent structures to be permanently damaged. As device sizes are decreased and device density is increased with technology scaling, it has become increasingly challenging to achieve adequate protection against such ESD damage. For example, with older technologies, a single silicided N-type field effect transistor (NFET) alone could adequately function as an input/output (I/O) pad driver and provide the necessary protection against ESD discharge. However, with technology scaling, such a single silicided NFET is no longer robust against ESD discharge.
Various solutions have been proposed to solve this ESD protection problem. For example, one proposed solution, as shown in
In view of the foregoing disclosed herein are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.
More particularly,
It should be understood that the SPESDFET 100, as described below and illustrated in
In each of these embodiments, the SPESDFET 100 can comprise a semiconductor layer 104. For example, this semiconductor layer 104 can comprise a semiconductor layer of a semiconductor-on-insulator (SOI) wafer 101. Specifically, the SOI wafer 101 can comprise a semiconductor substrate 102 (e.g., a single crystalline silicon substrate or other suitable semiconductor layer). The SOI wafer 101 can further comprise an insulator layer 103 (e.g., a silicon dioxide (SiO2) layer or other suitable insulator layer) on the semiconductor substrate 102 and a semiconductor layer 104 (e.g., a single crystalline silicon layer or other suitable semiconductor layer) on the insulator layer 103. Alternatively, the semiconductor layer 104 can comprise a bulk semiconductor wafer, such as a bulk silicon wafer (not shown).
The semiconductor layer 104 can have a first conductivity type. For example, in an NFET, it can be doped with a relatively low concentration of a P-type dopant (i.e., it can comprise a P− semiconductor layer). Those skilled in the art will recognize that, if a bulk semiconductor wafer is used rather than an SOI wafer, such an NFET would be formed within a P− well region of the wafer.
A trench isolation structure 105 can define the active region for the SPESDFET 100 and can electrically isolate the SPESDFET 100 from other devices on the substrate 101. This trench isolation structure can, optionally, extend vertically through the semiconductor layer 104 to the insulator layer 103 and can comprise, for example, a conventional shallow trench isolation (STI) structure comprising a trench filled with one or more isolation materials (e.g., a silicon oxide, silicon nitride, silicon oxynitride, etc.).
A gate structure 150 can be positioned on the top surface 110 of the semiconductor layer 104 offset from the isolation structure 105 and traversing a designated channel region 120 within the active region. This gate structure 150 can comprise a gate dielectric layer 151 on the top surface 110 of the semiconductor layer 104 and a gate conductor layer 152 on the gate dielectric layer 151. The gate dielectric layer 151 can comprise, for example, a silicon dioxide (SiO2) gate dielectric layer, a high-k gate dielectric layer or any other suitable gate dielectric layer. The gate conductor layer 152 can comprise, for example, a polysilicon gate conductor layer doped with a second conductivity type dopant such that it has the second conductivity type. For example, in an NFET, the polysilicon gate conductor layer can be doped with an N-type dopant. For a PFET, the polysilicon gate conductor layer can be doped with a P-type dopant. Alternatively, the gate conductor layer can comprise a metal gate conductor layer having the appropriate work function (i.e., energy band). In one embodiment of the SPESDFET 100, as shown in
The SPESDFET 100 can further comprise a channel region 120, having the first conductivity type, within the semiconductor layer 104 at the top surface 110 and aligned below the gate structure 150. For example, in an NFET, the channel region 120 can comprise a P-channel region.
The SPESDFET 100 can further comprise shallow source/drain extension regions 130 within the semiconductor layer 104 and positioned on opposing sides of the channel region 120. Each shallow source/drain extension region 130 can extend vertically from the top surface 110 of the semiconductor layer 104 to a first depth 136 below the top surface 110 and can comprise a first end portion 131 adjacent to the channel region 120, a second end portion 132 adjacent to the isolation structure 105 and a center portion 133 positioned laterally between the first end portion 131 and the second end portion 132. As mentioned above, gate sidewall spacers 155 can be positioned on the top surface of the semiconductor layer 104 on opposing sides of the gate structure 150 and, thereby above the first portions 131 of the source/drain extension regions 130. The shallow source/drain extension regions 130 can have a second conductivity type different from the first conductivity type and can be doped with a relatively low concentration of a second conductivity type dopant. For example, in an NFET, the shallow source/drain extension regions 130 can be N− or N shallow dopant implant regions.
The SPESDFET 100 can further comprise deep source/drain regions 140 within the semiconductor layer 104 also positioned on opposing sides of the channel region 120. Each deep source/drain region 140 can comprise a first section 141 and a second section 142. The first section 141 can be positioned adjacent to the channel region 120 and can extend vertically through the first end portion 131 of a corresponding shallow source/drain extension region 130 to a second depth 146 that is below the first depth 136. The interface 125 between the first section 141 of the deep source/drain region 140 and the channel region 120 can be aligned below the outer edge of a gate sidewall spacer 155 on the same side of the gate structure 150. The second section 142 can be positioned adjacent to the isolation structure 105 and can extend vertically through the second portion 132 of the corresponding shallow source/drain extension region 130, also to the second depth 146. Each of the sections 141-142 of the deep source/drain regions 140 can have the second conductivity type and can be doped with a relatively high concentration of the second conductivity type dopant. For example, in an NFET, each of the sections 141-142 of the deep source/drain regions 140 can be N+ deep dopant implant regions. Thus, within each second conductivity type deep source/drain region 140, the first and second sections 141-142 are separated by a resistance region 160 that comprises the center portion 133 of the second conductivity type shallow source/drain extension region 130 as well as a portion 114 of the first conductivity type semiconductor layer 104 below.
Optionally, the SPESDFET 100 can further comprise halo regions (not shown) within the semiconductor layer 104 on opposing sides of the channel region 120 for reducing short channel effects. Such halo regions can be positioned between the deep source/drain regions 140 and the channel region 120 and/or the shallow source/drain extension regions 130 and the channel region 120. These halo regions can have the same conductivity type as the channel region (i.e., a first conductivity type) but can be doped with a higher concentration of first conductivity type dopant. For example, in an NFET, the channel region can comprise a P-channel region and each halo region can comprise a P+ dopant implant region.
The SPESDFET 100 can further comprise first and second dielectric layers 171-172 and a metal silicide layer 111 on the top surface 110 of the semiconductor layer 104 on each side of the gate structure 150. Specifically, on each side of the gate structure 150, a first dielectric layer 171 (e.g., a silicon nitride (SiN) layer or other suitable dielectric silicide blocking layer) can be positioned above and abutting (i.e., in direct physical contact with) the center portion 133 of the shallow source/drain extension region 130 only (i.e., above the resistance region 160 only). Additionally, a second dielectric layer 172 (e.g., another silicon nitride (SiN) layer or other suitable dielectric silicide blocking layer) can be positioned above and abutting (i.e., in direct physical contact with) the first section 141 of the deep source/drain region 140 such that the first section 141 is covered by the second dielectric layer 172. Thus, the second dielectric layer 172 is further positioned laterally adjacent to and abutting the outer edge of the gate sidewall spacer 155 on the same side of the gate structure 150. The second dielectric layer 172 can further extend laterally over the first dielectric layer 171 and, optionally, onto a portion of the second section 142 of the deep source/drain region 140. The metal silicide layer 111 can be positioned above and abutting the second section 142 of the deep source/drain region 140. Like the metal silicide layer 112 above the gate conductor layer 152 in the embodiment shown in
In addition to the features described above, the SPESDFET 100 can further comprise one or more additional blanket dielectric layers 106 (i.e., interlayer dielectrics) over the structure, as described above. For example, the additional dielectric layer(s) can cover the gate structure 150 as well as the metal silicide layer 111 and the second dielectric layer 172 on each side of the gate structure 150. Contacts 160 (i.e., conductor filled vias) can extend vertically through the additional dielectric layer(s) 106 landing on the metal silicide layer 111 above each second section 142 of each source/drain regions and also to the gate structure 150 (not shown).
Referring to
Referring to
It should be understood that the method embodiments, as described below, can be used to form an N-type field effect transistor (NFET) or a P-type field effect transistor (PFET). Therefore, it should further be understood that, for an NFET, the “first conductivity type” refers to P-type conductivity and the “second conductivity type” refers to N-type conductivity. However, for a PFET, the reverse is true. That is, for a PFET, the first conductivity type refers to N-type conductivity and the second conductivity type refers to P-type conductivity. Additionally, those skilled in the art will recognize that P-type conductivity is typically achieved in a semiconductor material by doping with a P-type dopant (e.g., a Group III dopant, such as boron (B) or indium (In)), whereas N-type conductivity is typically achieved in a semiconductor material by doping with an N-type dopant (e.g., a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb)).
The method embodiments can comprise providing a semiconductor layer 104. The provided semiconductor layer 104 can comprise a semiconductor layer of a semiconductor-on-insulator (SOI) wafer 101 (302, see
Alternatively, the provided semiconductor layer 104 can comprise a bulk semiconductor wafer, such as a bulk silicon wafer (not shown). This bulk semiconductor wafer can further comprise a well region doped with a relatively low concentration of the first conductivity type and the SPESDFET 100 can be formed, as described below, within this first conductivity type well region. For example, an N-type SPESDFET 100 can be formed within well region doped with a relatively low concentration of a P-type dopant (i.e., a P well region or P− well region).
A trench isolation structure 105 can be formed in the semiconductor layer 104 so as to define the active region for the SPESDFET 100 and so as to electrically isolate the SPESDFET 100 from other devices on the substrate 101 (304, see
Then, a gate structure 150 can be formed on the top surface 110 of the semiconductor layer 104 offset from the isolation structure 105 and above a designated channel region 120 (306, see
The above-described technique for forming the gate structure 150 is offered for illustration purposes only and is not intended to be limiting. Techniques for forming gate structures with different configurations (e.g., gate structures with a metal gate conductor layer having a specific work function, with multiple metal and/or polysilicon gate conductor layers having dual work functions, etc.) are well-known in the art and can, alternatively, be incorporated into the method embodiments disclosed.
After the gate structure 150 is formed at process 306, shallow source/drain extension regions 130 can be formed on opposing sides of the channel region 120 (308, see
After the shallow source/drain extension regions 130 are formed at process 308, gate sidewall spacers 155 can be formed on opposing sides of the gate structure 150 (310, see
Next, a first dielectric layer 171 (i.e., a first silicide blocking layer) can be formed on the center portion 133 only of each of source/drain extension region 130 (312, see
Then, deep source/drain regions 140 can be formed on opposing sides of the channel region 120 (314, see
After the deep source/drain regions 140 are formed at process 314, a second dielectric layer 172 (i.e., a second silicide blocking layer) can be formed so as to cover at least the first section 141 of each of the deep source/drain regions 140 (316, see
Once the second dielectric layer 172 is formed at process 316, a metal silicide layer 106 can be formed on the second section 142 of each deep source/drain region 140 (318, see
It should be noted that, if the nitride cap layer 113 is removed from the gate structure 150 at process 316, as shown in
Additional processing can then be performed in order to complete the FET structure (320, see
Referring to
The method embodiments as described above can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
It should be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should further be understood that the terms “comprises”, “comprising”, “includes” and/or “including”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Additionally, it should be understood that the corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Therefore, disclosed above are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.
