Claims
- 1. A semiconductor circuit configuration, comprising:
a semiconductor substrate of a first conductivity type; a first line and a second line; a first individual line and a second individual line; a substrate level connected to said semiconductor substrate; a driver circuit integrated in said semiconductor substrate and containing a first and a second positive voltage (PV) switching transistor for switching positive and zero-value voltage levels, and a first and a second negative voltage (NV) switching transistor for switching negative and the zero-value voltage levels, said first PV switching transistor connected between said first line and said first individual line, said first NV switching transistor connected between said substrate level and said first individual line, said second NV switching transistor connected between said second line and said second individual line, said second PV switching transistor connected between said substrate level and said second individual line, said driver circuit having a number of circuit stages including a stage having an inversion and level-changing circuit, said driver circuit having outputs formed by at least one activation line pair formed of two complementary lines being said first individual line and said second individual line; said first PV switching transistor and said first NV switching transistor able to connect a first activation voltage present on said first line to said first individual line, said second PV switching transistor and said second NV switching transistor at a same time able to connect a second activation voltage present on said second line to said second individual line, the first activation voltage and the second activation voltage can be of opposite polarity; said first PV switching transistor and said first NV switching transistor able to connect said first individual line to said substrate level, said second PV switching transistor and said second NV switching transistor at a same time able to connect said second individual line to said substrate level; an outer well disposed in said semiconductor substrate and formed of a second conductivity type being opposite to said first conductivity type, said first NV switching transistor and said second NV switching transistor of said driver circuit formed within said outer well, said outer well connected to a supply voltage; and an actuation circuit disposed upstream of and connected to said driver circuit and formed in said semiconductor substrate.
- 2. The semiconductor circuit configuration according to claim 1, wherein said actuation circuit is formed by a decoder having a number of outputs which are coupled to said driver circuit.
- 3. The semiconductor circuit configuration according to claim 2, wherein one of said outputs of said decoder is able to be switched to be active and supplies a zero level voltage, while all others of said outputs of said decoder, which are switched to be passive, each supply a positive potential level voltage.
- 4. The semiconductor circuit configuration according to claim 3, wherein said inversion and level-changing circuit is followed by and connected to said first PV switching transistor and said second NV switching transistor, which switch a negative activation voltage, which is applied to said driver circuit, to at least said first individual line of said at least one activation line pair, and switch a positive activation voltage, which is likewise applied to said driver circuit, to said second individual line of said at least one activation line pair, respectively.
- 5. The semiconductor circuit configuration according to claim 4, wherein a potential of the positive activation voltage is equal to or greater than a potential of the supply voltage.
- 6. The semiconductor circuit configuration according to claim 5, wherein:
said driver circuit has a further inversion and level-changing circuit following said inversion and level-changing circuit; and said first NV switching transistor and said second PV switching transistor each have a control terminal connected to said further inversion and level-changing circuit and each have electrode connections connected to said substrate level and to said two complementary individual lines.
- 7. The semiconductor circuit configuration according to claim 6,
wherein said inversion and level-changing circuit and said first PV switching transistor together with said second NV switching transistor switch the first activation voltage and the second activation voltage; and including protection transistors of a predefined conductivity type, a first of said protection transistors having a control terminal connected to the supply voltage and electrode terminals connected to said inversion and level-changing circuit and to said first PV switching transistor, a second of said protection transistors having a control terminal connected to the supply voltage and electrode terminals connected to said inversion and level-changing circuit and to said second NV switching transistor.
- 8. The semiconductor circuit configuration according to claim 7, including a holding transistor having a control terminal connected to an output of said inversion and level-changing circuit and electrode terminals connected to the supply voltage and to an input of said inversion and level-changing circuit.
- 9. The semiconductor circuit configuration according to claim 8, wherein said holding transistor is a MOS transistor having a positive conductivity type.
- 10. The semiconductor circuit configuration according to claim 7, wherein said inversion and level-changing circuit, said further inversion and level, said protection transistors, said first PV switching transistor, said second PV switching transistor, said first NV switching transistor and said second NV switching transistor are embedded within said outer well in said semiconductor substrate.
- 11. The semiconductor circuit configuration according to claim 8, wherein said holding transistor is embedded within said outer well.
- 12. The semiconductor circuit configuration according to claim 6, wherein at least one of said inversion and level-changing circuit and said further inversion level-changing circuit is formed of two transistors of opposite polarity integrated in said semiconductor substrate, a signal input connected to said two transistors, and a signal output connected to said two transistors.
- 13. The semiconductor circuit configuration according to claim 12, wherein said two transistors have control inputs connected to said signal input, one of said two transistors is a positive type transistor having a first electrode connected to a positive supply voltage and a second electrode connected to said output, another of said two transistors is a negative type transistor having a first electrode connected to said output and a second electrode connected to a negative voltage, said negative type transistor is formed within said outer well and said outer well is connected to the supply voltage.
- 14. The semiconductor circuit configuration according to claim 6, wherein at least one of said inversion and level-changing circuit and said further inversion level-changing circuit is formed of transistors, including positive type transistors and negative type transistors integrated in said semiconductor substrate, a first input connected to said transistors, a second input connected to said transistors, and an output connected to said transistors.
- 15. The semiconductor circuit configuration according to claim 14, wherein:
a first negative type transistor of said negative type transistors has a control input connected to said first input, a first electrode connected to a negative supply voltage, and a second electrode connected to said output; one of said positive type transistors has a first electrode connected to said output, a second electrode connected to a positive supply voltage, and a control input connected to said first input; and a second negative type transistor of said negative type transistor has a first electrode connected to said control input of said one of said positive type transistors, a second electrode connected to the negative supply voltage, and a control input connected to said output, said negative type transistors are formed within said outer well and said outer well is connected to the supply voltage.
- 16. The semiconductor circuit configuration according to claim 15, wherein another transistor of said positive type transistors is connected upstream of said first input and has a control input connected to a zero potential voltage, a first electrode connected to said second input and a second electrode connected to said first input.
Priority Claims (1)
Number |
Date |
Country |
Kind |
198 41 445.5 |
Sep 1998 |
DE |
|
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of copending International application Ser. No. PCT/DE99/02831, filed Sep. 7, 1999, which designated the United States.
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/DE99/02831 |
Sep 1999 |
US |
Child |
09804322 |
Mar 2001 |
US |