Semiconductor device and a method of manufacturing the same

Abstract

A memory cell has a control gate electrode disposed on a main surface of a semiconductor substrate through a gate insulating film, an ONO film disposed along a side surface of the control gate electrode and the main surface of semiconductor substrate, a memory gate electrode disposed on a side surface of the control gate electrode and also on the main surface of the semiconductor substrate through the ONO film. The control gate electrode and the memory gate electrode are formed, over the upper portions thereof, with a silicide film and an insulating film formed by oxidation of the surface of the silicide film, respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view showing an essential part of a semiconductor device according to one embodiment of the invention;

FIG. 2 is an enlarged view of a memory cell of FIG. 1;

FIG. 3 is a graphical representation illustrating a withstand voltage characteristic between a control gate electrode and a memory gate electrode of the memory cell of FIG. 1;

FIG. 4 is an enlarged view of a peripheral transistor of FIG. 1;

FIG. 5 is a schematic sectional view showing an essential part of a semiconductor device in a manufacturing step thereof according to another embodiment of the invention;

FIG. 6 is a schematic sectional view showing a step subsequent to FIG. 5;

FIG. 7 is a schematic sectional view showing a step subsequent to FIG. 6;

FIG. 8 is a schematic sectional view showing a step subsequent to FIG. 7;

FIG. 9 is a schematic sectional view showing a step subsequent to FIG. 8;

FIG. 10 is a schematic sectional view showing a step subsequent to FIG. 9;

FIG. 11 is a schematic sectional view showing a step subsequent to FIG. 10;

FIG. 12 is a schematic sectional view showing a step subsequent to FIG. 11;

FIG. 13 is a schematic sectional view showing a step subsequent to FIG. 12;

FIG. 14 is a graphical representation of a temperature dependence of a thickness of an oxide film formed on a silicide film;

FIG. 15 is a graphical representation illustrating a cumulative frequency distribution of sheet resistance;

FIG. 16 is a schematic sectional view showing a memory cell checked by us;

FIG. 17 is a graphical representation illustrating a withstand voltage characteristic between a control gate electrode and a memory gate electrode of a memory cell of FIG. 16;

FIG. 18 is a schematic sectional view showing another type of memory cell checked by us;

FIG. 19 is a graphical representation illustrating a withstand voltage characteristic between a control gate electrode and a memory gate electrode of a memory cell of FIG. 18; and

FIG. 20 is a schematic sectional view showing a peripheral transistor checked by us.

Claims

1. A semiconductor device having a non-volatile memory device comprising: a semiconductor substrate;a first insulating film formed over a main surface of the semiconductor substrate;a control gate electrode formed over the semiconductor substrate through the first insulating film;a second insulating film formed along a side surface of the control gate electrode and the main surface of the semiconductor substrate; anda memory gate electrode formed through the second insulating film over the side surface of the control gate electrode and the main surface of the semiconductor substrate, respectively,wherein a silicide film and an oxide film formed by oxidation of the silicide film on a surface thereof are, respectively, formed over an upper portion of the control gate electrode and also over an upper portion of the memory gate electrode.

2. The semiconductor device according to claim 1, wherein the oxide film covers the surface of the silicide film.

3. The semiconductor device according to claim 1, wherein the silicide film is a cobalt silicide film.

4. A method of manufacturing a semiconductor device having an MIS transistor including: a silicon substrate;a gate insulating film formed over a main surface of the silicon substrate;a gate electrode including a silicon film formed over the silicon substrate through the gate insulating film;a side wall formed on a side surface of the gate electrode; anda diffusion layer formed over the main surface of the silicon substrate in self-alignment with the side wall, the method comprising the steps of:(a) forming a metal film formed entirely over the main surface of the silicon substrate so as to cover the gate electrode therewith;(b) reacting the silicon film with the metal film and also the diffusion layer with the metal film through a first thermal treatment to form a first silicide film over an upper portion of the gate electrode and an upper portion of the diffusion layer, respectively;(c) removing the metal film left unreacted after the step (b); and(d) subjecting the first silicide film to phase transformation by a second thermal treatment in an atmosphere containing oxygen to form a second silicide film and an oxide film on a surface of the second silicide film.

5. The method according to claim 4, wherein the first thermal treatment is carried out in an atmosphere of nitrogen, and a ratio of nitrogen in an atmosphere of the second thermal treatment is lower than a ratio of nitrogen in the atmosphere of the thermal treatment.

6. The method according to claim 4, wherein a temperature of the silicon substrate in the second thermal treatment is higher than a temperature of the silicon substrate in the first thermal treatment.

7. The method according to claim 4, wherein the temperature of the silicon substrate in the second thermal treatment is at 680° C. to 800° C.

8. The method according to claim 4, wherein the temperature of the silicon substrate in the second thermal treatment is at 680° C. to 730° C.

9. The method according to claim 4, further comprising the steps of: (e) forming a polysilicon film over the gate insulating film to implant an ion into the polysilicon film; and(f) after the step (e), forming the silicon film having the polysilicon film by a third thermal treatment in an atmosphere containing oxygen,wherein a ratio of oxygen in the atmosphere of the second thermal treatment is higher than a ratio of oxygen in the atmosphere of the third thermal treatment.

10. The method according to claim 4, wherein a ratio of oxygen in the atmosphere of the second thermal treatment ranges 5% to 100%.

11. A method of manufacturing a semiconductor device having a non-volatile memory device including: a silicon substrate;a first insulating film formed over a main surface of the silicon substrate;a control gate electrode including a silicon film formed over the silicon substrate through the first insulating film;a second insulating film formed along a side wall of the control gate electrode and the main surface of the silicon substrate; anda memory gate electrode including a second silicon film formed over the side wall of the control gate electrode and the main surface of the silicon substrate, the method comprising the steps of:(a) forming a metal film entirely over the main surface of the silicon substrate so as to cover the control gate electrode and the memory gate electrode therewith;(b) reacting the first silicon film with the metal film and also the second silicon film with the metal film through a first thermal treatment to form a first silicide film over an upper portion of the control gate electrode and an upper portion of the memory gate electrode, respectively;(c) removing the metal film left unreacted in the step (b); and(d) subjecting the first silicide film to phase transformation by a second thermal treatment in an atmosphere containing oxygen to form a second silicide film and an oxide film on a surface of the second silicide film.

12. The method according to claim 11, wherein the first thermal treatment is carried out in an atmosphere of nitrogen, and a ratio of nitrogen in the atmosphere of the second thermal treatment is smaller than a ratio of nitrogen in the atmosphere of the first thermal treatment.

13. The method according to claim 11, wherein a temperature of the silicon substrate in the second thermal treatment is higher than a temperature of the silicon substrate in the first thermal treatment.

14. The method according to claim 11, wherein the temperature of the silicon substrate in the second thermal treatment is at 680° C. to 800° C.

15. The method according to claim 11, wherein the temperature of the silicon substrate in the second thermal treatment is at 680° C. to 730° C.

16. The method according to claim 11, further comprising the steps of: (e) forming a polysilicon film over the gate insulating film to implant an ion into the polysilicon film; and(f) after the step (e), forming the silicon film made of the polysilicon film by a third thermal treatment in an atmosphere containing oxygen,wherein a ratio of oxygen in the atmosphere of the second thermal treatment is higher than a ratio of oxygen in the atmosphere of the third thermal treatment.

17. The method according to claim 11, wherein a ratio of oxygen in the atmosphere of the second thermal treatment ranges 5% to 100%.