Patent Application
20230061301
This application claims benefit of priority to Korean Patent Application No. 10-2021-0115769 filed on Aug. 31, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
Example embodiments of the present disclosure relate to a semiconductor device and a data storage system including the same.
There has been demand for a semiconductor device for storing high-capacity data in an electronic system requiring data storage. Accordingly, a method of increasing data storage capacity of a semiconductor device has been studied. For example, as one method for increasing data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally, instead of memory cells arranged two-dimensionally, has been suggested.
According to an embodiment, a semiconductor device includes a lower structure including a substrate and a peripheral circuit on the substrate; and an upper structure on the lower structure, wherein the upper structure includes a stack structure including interlayer insulating layers and gate layers, a vertical memory structure penetrating through the stack structure, a bit line electrically connected to the vertical memory structure below the stack structure, a conductive pattern electrically connected to the vertical memory structure on the stack structure, an upper insulating layer covering the conductive pattern and a capping insulating layer on the upper insulating layer, wherein the vertical memory structure includes an insulating core region, a first pad pattern electrically connected to the conductive pattern on the insulating core region, a dielectric structure on a side surface of the insulating core region and a side surface of the first pad pattern, and a channel layer between the insulating core region and the dielectric structure and between the insulating core region and the first pad pattern, and wherein the channel layer includes a first portion contacting the dielectric structure and a second portion extending from the first portion and between a lower surface of the first pad pattern and an upper surface of the insulating core region.
According to an embodiment, a semiconductor device includes a lower structure including a substrate and a peripheral circuit on the substrate; and an upper structure bonded to the lower structure on the lower structure, wherein the upper structure includes a stack structure including interlayer insulating layers and gate layers; a vertical memory structure penetrating through the stack structure; a bit line electrically connected to the vertical memory structure below the stack structure; gate contact plugs contacting pad regions of the gate layers and below the gate layers; a source contact plug and an input/output contact plug spaced apart from the gate layers, and having upper surfaces on a level higher than a level of an uppermost gate layer among the gate layers, and lower surfaces on a level lower than a level of a lowermost gate layer among the gate layers; a first conductive pattern electrically connected to the vertical memory structure and the source contact plug on a level higher than a level of the stack structure; a second conductive pattern electrically connected to the input/output contact plug on the same level as a level of the first conductive pattern; an upper insulating layer covering the first and second conductive patterns; a capping insulating layer on the upper insulating layer; and an input/output pattern penetrating through the capping insulating layer and the upper insulating layer and electrically connected to the second conductive pattern, wherein the vertical memory structure includes an insulating core region, a channel layer covering at least a side surface of the insulating core region, a first pad pattern contacting the channel layer on a level higher than a level of the uppermost gate layer, a dielectric structure contacting the first pad pattern and the channel layer, and a second pad pattern contacting the channel layer below the insulating core region, wherein the insulating core region is spaced apart from the first pad pattern, wherein the dielectric structure includes a first dielectric layer, a second dielectric layer and a data storage layer between the first dielectric layer and the second dielectric layer, and wherein the second dielectric layer includes a portion contacting the channel layer and a portion contacting the first pad pattern, and is spaced apart from the second pad pattern.
According to an embodiment, a data storage system includes a semiconductor device including an input/output pattern; and a controller electrically connected to the semiconductor device through the input/output pattern and controlling the semiconductor device, wherein the semiconductor device includes a lower structure including a substrate and a peripheral circuit on the substrate; and an upper structure bonded to the lower structure on the lower structure, wherein the upper structure includes a stack structure including interlayer insulating layers and gate layers; a vertical memory structure penetrating through the stack structure; a bit line electrically connected to the vertical memory structure below the stack structure; gate contact plugs contacting pad regions of the gate layers and below the gate layers; a source contact plug and an input/output contact plug spaced apart from the gate layers, and having upper surfaces on a level higher than a level of an uppermost gate layer among the gate layers, and lower surfaces on a level lower than a level of a lowermost gate layer among the gate layers; a first conductive pattern electrically connected to the vertical memory structure and the source contact plug on a level higher than a level of the stack structure; a second conductive pattern electrically connected to the input/output contact plug on the same level as a level of the first conductive pattern; an upper insulating layer covering the first and second conductive patterns; and a capping insulating layer on the upper insulating layer, wherein the input/output pattern penetrates the capping insulating layer and the upper insulating layer and is electrically connected to the second conductive pattern, wherein the vertical memory structure includes an insulating core region, a channel layer covering at least a side surface of the insulating core region, a first pad pattern contacting the channel layer on a level higher than a level of the uppermost gate layer, a dielectric structure contacting the first pad pattern and the channel layer, and a second pad pattern below the insulating core region, wherein the dielectric structure includes a first dielectric layer, a second dielectric layer, and a data storage layer between the first dielectric layer and the second dielectric layer, and wherein the second dielectric layer includes a portion contacting the channel layer and a portion contacting the first pad pattern, and is spaced apart from the second pad pattern.
Features will become apparent to those of skill in the art by describing in detail example embodiments with reference to the attached drawings in which:
A semiconductor device according to an example embodiment will be described with reference to
Referring to
The lower structure LS may include a substrate 3, peripheral circuit structures 9 and 12, a lower insulating structure 15, and first bonding pads 18.
The substrate 3 may be a semiconductor substrate. For example, the substrate 3 may be a single crystal semiconductor substrate. For example, the substrate 3 may be a single crystal silicon layer. The peripheral circuit structures 9 and 12 may include a peripheral circuit 9 on the substrate 3, and a peripheral wiring structure 12 (e.g., a peripheral interconnection structure) electrically connected to the peripheral circuit 9 and on the substrate 3. The peripheral circuit 9 may include source/drain regions 9b in an active region 6a defined by a device isolation region 6s on the substrate 3, and a peripheral gate 9a on the active region 6a between the source/drain regions 9b. The lower insulating structure 15 may cover the peripheral circuit structures 9 and 12 on the substrate 3. The first bonding pads 18 may be electrically connected to the peripheral wiring structure 12, and may be embedded in the lower insulating structure 15. Upper surfaces of the first bonding pads 18 may be coplanar with an upper surface of the lower insulating structure 15. The first bonding pads 18 may include a metal material forming the intermetallic bonding, e.g., copper.
The upper structure US may include a stack structure ST including interlayer insulating layers 105 and gate layers 140 alternately stacked, a vertical memory structure VCa penetrating through the stack structure ST, a bit line 160b electrically connected to the vertical memory structure VCa below the stack structure ST, a first conductive pattern 189a electrically connected to the vertical memory structure VCa on the stack structure ST, an upper insulating layer 192 covering the first conductive pattern 189a, and a capping insulating layer 195 on the upper insulating layer 192. The upper insulating layer 192 may include silicon oxide. The capping insulating layer 195 may include at least one of silicon nitride and polyimide.
The stack structure ST may include a first stack region ST1 and a second stack region ST2 below the first stack region ST1. Each of the first and second stack regions ST1 and ST2 may include the interlayer insulating layers 105 and the gate layers 140 alternately stacked. The interlayer insulating layers 105 may include silicon oxide.
The upper structure US may include a first region CA and a second region SA adjacent to the first region CA. The first region CA may be a memory region or a memory cell array region. The second region SA may be a staircase region.
The gate layers 140 may be vertically stacked and spaced apart from each other in the first region CA, and may extend from the first region CA to the second region SA. The gate layers 140 may include gate pads GP arranged in a staircase shape in the second region SA. The gate pads GP may face the lower structure LS. For example, a gate layer disposed relatively in an upper portion may further extend to the second region SA than a gate layer disposed relatively in a lower portion.
In an example, each of the gate layers 140 may include a gate electrode including a conductive material, e.g., at least one of doped polysilicon, metal nitride (e.g., TiN, etc.), a metal-semiconductor compound (e.g., TiSi, NiSi, etc.), and a metal (e.g., W, etc.).
In a modified example, each of the gate layers 140 may include a conductive layer and a dielectric layer covering the upper and lower surfaces of the conductive layer and covering the side surface of the conductive layer facing the vertical memory structure VCa. The conductive layer may be a gate electrode. The dielectric layer may be a gate dielectric formed of a high dielectric.
The upper structure US may further include a separation structure SS penetrating through the stack structure ST. In an example, the separation structure SS may be formed of an insulating material. In the modified example, the separation structure SS may include a conductive pattern and an insulating spacer covering a side surface of the conductive pattern.
The upper structure US may further include a second conductive pattern 189b on the same level as a level of the first conductive pattern 189a and spaced apart from the first conductive pattern 189a. Each of the first and second conductive patterns 189a and 189b may include a first conductive layer 188a and a second conductive layer 188b on the first conductive layer 188a. Each of the first and second conductive patterns 189a and 189b may have an inclined side surface. For example, each of the first and second conductive patterns 189a and 189b may have side surfaces inclined such that a width thereof may increase downwardly. The first conductive layer 188a may include a metal material, e.g., Ti and/or TiN. The second conductive layer 188b may include a metal material, e.g., aluminum or tungsten.
The upper structure US may include gate contact plugs 150g contacting and electrically connected to the gate pads GP below the gate layers 140, the source contact plug 150s contacting and electrically connected to the first conductive pattern 189a below the first conductive pattern 189a, and the input/output contact plug 150i contacting and electrically connected to the second conductive pattern 189b below the second conductive pattern 189b.
The upper structure US may further include gate interconnections 160g, a source interconnection 160s, and an input/output interconnection 160i on the same level as a level of the bit line 160b. The bit line 160b, the gate interconnections 160g, the source interconnection 160s, and the input/output interconnection 160i may include the same metal material, e.g., tungsten or copper. The bit line 160b, the gate interconnections 160g, the source interconnection 160s, and the input/output interconnection 160i may form the interconnections 160b, 160g, 160s, and 160i. The interconnections 160b, 160g, 160s, and 160i may be wirings.
The upper structure US may further include studs 155b, 155g, 155s, and 155i. The studs 155b, 155g, 155s, and 155i may include a bit line stud 155b electrically connecting the bit line 160b to the vertical memory structure VCa between the bit line 160b and the vertical memory structure VCa, gate studs 155g electrically connecting the gate contact plugs 150g to the gate interconnections 160g between the gate contact plugs 150g and the gate interconnections 160g, a source stud 155s electrically connecting the source contact plug 150s to the source interconnection 160s between the source contact plug 150s and the source interconnection 160s, and an input/output stud 155i electrically connecting the input/output contact plug 150i to the input/output interconnection 160i between the input/output contact plug 150i and the input/output interconnection 160i.
The upper structure US may further include the second bonding pads 170. The second bonding pads 170 may be formed of the same material as that of the first bonding pads 18, and may be in contact with and bonded to the first bonding pads 18.
The upper structure US may further a include a connection structure 165 electrically connecting the interconnections 160b, 160g, 160s, and 160i including the bit line 160b, the gate interconnections 160g, the source interconnection 160s, and the input/output interconnection 160i to the second bonding pads 170. The connection structure 165 may have various shapes. For example, the connection structure 165 may be formed in a shape including a vertically extending via and a horizontally extending line-shaped wiring.
The upper structure US may further include an upper insulating structure 175. The upper insulating structure 175 may contact the lower insulating structure 15. The stack structure ST, the contact plugs 150g, 150s, and 150i, the interconnections 160b, 160g, 160s, and 160i, and the studs 155b, 155g, 155s, and 155i may be embedded in the upper insulating structure 175. An upper surface of the stack structure ST may be coplanar with an upper surface of the upper insulating structure 175, and lower surfaces of the second bonding pads 170 may be coplanar with a lower surface of the upper insulating structure 175.
The first conductive pattern 189a may include a portion covering the stack structure ST and a portion covering the upper surface of the upper insulating structure 175. The second conductive pattern 189b may be on the upper insulating structure 175.
The upper structure US may further include an input/output pattern 198 penetrating through the capping insulating layer 195 and the upper insulating layer 192 on the second conductive pattern 189b, and electrically connected to the second conductive pattern 189b. The input/output pattern 198 may include a conductive liner 198a and a conductive layer 198b on the conductive liner 198a in order. The conductive liner 198a may include a conductive material, e.g., Ti and/or TiN. The conductive layer 198b may include a conductive material, e.g., aluminum or copper. The input/output pattern 198 may include a portion penetrating through the capping insulating layer 195, a portion penetrating through the upper insulating layer 192, and a portion on the capping insulating layer 195.
In the description below, an example of the vertical memory structure VCa will be described with reference to
Referring to
The first pad pattern 124 may be on a level higher than a level of an uppermost gate layer 140L1 among the gate layers 140. The first pad pattern 124 may be on a level higher than a level of the lower surface of the uppermost interlayer insulating layer 105L1 among the interlayer insulating layers 105, and may be on a level substantially the same as a level of the upper surface of the uppermost interlayer insulating layer 105L1. In a modified example, the first pad pattern 124 may be on a level lower than a level of an upper surface of the uppermost interlayer insulating layer 105L1. A lower surface of the first pad pattern 124 may have a concave shape.
The channel layer 126 may include a first portion 126_1 contacting the dielectric structure 115, and a second portion 126_2 extending from the first portion 126_1 and between the lower surface of the first pad pattern 124 and the upper surface of the insulating core region 129.
The vertical memory structure VCa may further include a second pad pattern 132 below the insulating core region 129. The channel layer 126 may contact the second pad pattern 132. The channel layer 126 may cover a side surface of the second pad pattern 132. The dielectric structure 115 may cover the external side surface of the channel layer 126 on a level on which the second pad pattern 132 is disposed.
The first and second pad patterns 124 and 132 may include doped silicon, e.g., polysilicon having an N-type conductivity. The channel layer 126 may be formed of a silicon layer. The channel layer 126 may be formed of a single silicon layer.
The second pad pattern 132 may have a width greater than that of the first pad pattern 124.
The dielectric structure 115 may include a first dielectric layer 116, a data storage layer 118, and a second dielectric layer 120. The data storage layer 118 may be interposed between the first dielectric layer 116 and the second dielectric layer 120. The first dielectric layer 116 may include silicon oxide and/or a high dielectric. The data storage layer 118 may include a material able to store data in a memory device, e.g., silicon nitride able to trap charges. The second dielectric layer 120 may be a tunnel dielectric layer contacting the channel layer 126. The second dielectric layer 120 may be silicon oxide or silicon oxide doped with impurities. The second dielectric layer 120 may include a region contacting the channel layer 126 and a region contacting a side surface of the first pad pattern 124.
The semiconductor device 1 may further include a metal-semiconductor compound layer 185 between the first pad pattern 124 and the first conductive pattern 189a. The metal-semiconductor compound layer 185 may be formed of a metal silicide, e.g., TiSi, CoSi, WSi, or NiSi.
The metal-semiconductor compound layer 185 may be configured as a portion of the first conductive pattern 189. For example, a component formed of silicon in contact with the first conductive pattern 189, e.g., a region of the first conductive pattern 189 in contact with the first pad pattern 124, may be the metal-semiconductor compound layer 185.
An upper end of the dielectric structure 115 may contact the first conductive pattern 189a. For example, an upper end of the first dielectric layer 116, an upper end of the data storage layer 118, and an upper end of the second dielectric layer 120 may contact the first conductive pattern 189a.
The data storage layer 118 may include a bent portion 118v on a level higher than a level of the uppermost gate layer 140L1 among the gate layers 140. The channel layer 126 may include a bent portion 126V on a level higher than a level of the uppermost gate layer 140L1 among the gate layers 140.
The channel layer 126 may include a first doped region 126a contacting the first pad pattern 124, a second doped region 126c contacting the second pad pattern 132, and an undoped region 126b between the first doped region 126a and the second doped region 126c. The first and second doped regions 126a and 126c may be silicon regions having an N-type conductivity. The undoped region 126b may be an undoped silicon region.
The gate layers 140 may include a plurality of upper gate layers 140L1 and 140L2, a plurality of lower gate layers 140U1 and 140U2, and intermediate gate layers 140M between the plurality of upper gate layers 140L1 and 140L2 and the plurality of lower gate layers 140U1 and 140U2. The intermediate gate layers 140M may include word lines.
The first doped region 126a may extend from a portion contacting the first pad pattern 124, and may face at least one of the plurality of upper gate layers 140L1 and 140L2. The second doped region 126c may extend from a portion contacting the second pad pattern 132, and may face at least one of the plurality of lower gate layers 140U1 and 140U2.
The semiconductor device 1 may be a flash memory device, in which case at least one of the plurality of upper gate layers 140L1 and 140L2 may be an upper erase control gate electrode used for an erase operation of the flash memory device, and at least one of the plurality of lower gate layers 140U1 and 140U2 may be a lower erase control gate electrode used in an erase operation of the flash memory device. The number of erase control gates may be determined according to the total number of the stacked gate layers 140. Accordingly, the number of the plurality of upper gate layers 140L1 facing the first doped region 126a, and the number of the plurality of lower gate layers 140U1 and 140U2 facing the second doped region 126c may be determined.
Among the gate layers 140, a gate layer between the upper erase control gate electrode and the word lines may be a ground select gate electrode, and a gate layer between the lower erase control gate electrode and the word lines may be a string select gate electrode.
In an example, as illustrated in
In the modified example, referring to
Referring back to
In an example, the width change region VC_v may be defined as a region in which a width may change as the width of the lower region of the upper vertical region VC_a is different from the width of the upper region of the upper vertical region ST2.
In the modified example, the width change region VC_v may be defined as a region formed as the side surface of the upper vertical region VC_a and the side surface of the upper vertical region ST2 are not vertically aligned.
Also, in the modified example, the width change region VC_v may define a region having a slope different from those of the side surface of the upper vertical region VC_a and the side surface of the upper vertical region ST2. For example, the width change region VC_v may be defined as a slope change region having a slope gentler than the slopes of the side surface of the upper vertical region VC_a and the side surface of the upper vertical region ST2.
Also, in the modified example, as the width change region VC_v may extend while being bent from the side surface of the upper vertical region VC_a and the side surface of the upper vertical region ST2, the width change region VC_v may be defined as a “bent portion.”
Hereinafter, the elements using the term “width change region” may be a width change region formed as the width of the upper region is different from the width of the lower region, or a slope change region having a slope different from the slopes of the upper and lower regions, e.g., a gentle slope, unless otherwise indicated.
In the first stack region ST1, a lowermost interlayer insulating layer 105M among the interlayer insulating layers 105 may have a thickness greater than a thickness of the interlayer insulating layer vertically adjacent to the lowermost interlayer insulating layer 105M.
In the first stack region ST1, an interlayer insulating layer 105L2 between the plurality of upper gate layers 140L1 and 140L2 and the plurality of intermediate gate layers 140M may have a thickness greater than a thickness of the interlayer insulating layer 105 vertically adjacent to the interlayer insulating layer 105L2.
In the first stack region ST1, the uppermost interlayer insulating layer 105L1 of the interlayer insulating layers 105 may be coplanar with the upper surface of the upper insulating structure 175 (in
In the second stack region ST2, a lowermost interlayer insulating layer 105U among the interlayer insulating layers 105 may have a thickness greater than a thickness of the interlayer insulating layer vertically adjacent to the lowermost interlayer insulating layer 105U.
In an example embodiment, since the vertical memory structure VCa includes the first pad pattern 124 and the second pad pattern 132, performance of the semiconductor device 1 may improve. For example, the first pad pattern 124 may be a source supplying a dopant in the first doped region 126a of the channel layer 126, and the second pad pattern 132 may be a source supplying a dopant in the second doped region 126c of the channel layer 126. The first and second doped regions 126a and 126c in the channel layer 126 may increase erase efficiency of an erase operation using a gate induced drain leakage (GIDL) phenomenon in a flash memory device.
Hereinafter, various modified examples of a portion of the components of the semiconductor device 1 according to an example embodiment will be described. Hereinafter, mainly the modified components will be described. Also, the elements indicated by the same terms may be formed of the same material unless otherwise indicated. For example, the first pad pattern 124 in
Modified examples of a semiconductor device according to an example embodiment will be described with reference to
Each of
In the modified example, referring to
Accordingly, the area or overlap between the first conductive pattern 189a and the first pad pattern 123 may increase, such that resistive properties may improve. For example, the contact region between the metal-semiconductor compound layer 185 interposed between the first conductive pattern 189a and the first pad pattern 123 and the first pad pattern 123 may increase, contact resistance may decrease. Accordingly, since resistive properties of the semiconductor device 1 may improve, performance of the semiconductor device 1 may improve.
In the modified example, referring to
In an example, the buffer layer 103a may include a semiconductor material, e.g., silicon. For example, the buffer layer 103a may be configured as a silicon layer having an N-type conductivity.
In the modified example, the buffer layer 103a may include an insulating material, e.g., at least one of silicon nitride and silicon oxide.
The first pad pattern 124 (in
The vertical memory structure VCa may include a bent portion VC_vp between side surfaces of a portion VC_p penetrating through the buffer layer 103a, and a portion VC_p penetrating through the buffer layer 103a and a side surface of a portion penetrating through the stack structure (ST in
The buffer layer 103a may prevent the thickness of the uppermost interlayer insulating layer 105L1 from being excessively reduced. That is, by disposing the buffer layer 103a, the uppermost interlayer insulating layer 105L1 may be formed to have a constant thickness. Accordingly, defects such as leakage current or electric shorts between the first conductive pattern 189a and the uppermost gate layer 140L1, caused by the reduced thickness of the uppermost interlayer insulating layer 105L1, may be prevented, or degradation of performance of the semiconductor device, caused by the excessively reduced thickness of the first pad pattern 123, may be prevented.
In the modified example, referring to
Since the extension portion 189a_p of the first conductive pattern 189a may increase the area of overlap between the first conductive pattern 189a and the first pad pattern 123, resistive properties may improve
In the description below, referring to
The first conductive pattern 189a may contact an upper surface of the source contact plug 150s. The second conductive pattern 189b may contact an upper surface of the input/output contact plug 150i.
In the description below, a modified example of the source contact plug 150s and the input/output contact plug 150i will be described with reference to
In the modified example, referring to
In the description below, a modified example of a semiconductor device will be described with reference to
In the modified example, referring to
The vertical memory structure VCb may include an insulating core region 229, a first pad pattern 224 on the insulating core region 229, dielectric structure 215 on a side surface of the insulating core region 229 and a side surface of the first pad pattern 224, a channel layer 226 between the insulating core region 229 and the dielectric structure 215 and between the insulating core region 229 and the first pad pattern 224, and a second pad pattern 232 contacting the channel layer 226 below the insulating core region 229. The dielectric structure 215 may include a first dielectric layer 216, a data storage layer 218, and a second dielectric layer 220 corresponding to the first dielectric layer 116 of the dielectric structure 115 (in
The channel layer 226 may include a first doped region 226a, an undoped region 226b, and a second doped region 226c, corresponding to the first doped region 126a, the undoped region 126b, and the second doped region 126c described with reference to
In the various modified embodiments below, the “first doped region” of the channel layer may correspond to the first doped region 126a described with reference to
A metal-semiconductor compound layer 285 may be between the first pad pattern 224 and the first conductive pattern 189a. A lower surface of the first pad pattern 224 may have a concave shape.
The structure of the vertical memory structure VCb penetrating through the second stack region ST2 may be substantially the same as the vertical memory structure VCa (in
The vertical memory structure VCb may include a lower vertical region VC_b penetrating through the second stack region ST2, a first upper vertical region VC_a extending from the lower vertical region VC_b and penetrating through the at least the intermediate gate layers 140M in the first stack region ST1, a second upper vertical region VC_c extending from the first upper vertical region VC_a and penetrating at least the upper gate layers 140L1 and 140L2, a first width change region VC_v1 between the lower vertical region VC_b and the first upper vertical region VC_a, and a second width change region VC_v2 between the first upper vertical region VC_a and the second upper vertical region VC_c
The second width change region VC_v2 may be on a level between the plurality of upper gate layers 140L1 and 140L2 and the plurality of intermediate gate layers 140M. The second width change region VC_v2 may contact the interlayer insulating layer 105L2 between the plurality of upper gate layers 140L1 and 140L2 and the plurality of intermediate gate layers 140M.
The second upper vertical region VC_c may have an inclined side surface, such that a width of the second upper vertical region VC_c may decrease upwardly, and the lower region of the second upper vertical region VC_c may be greater than a width of an upper region of the first upper vertical region VC_a. The second width change region VC_v2 may also be defined as a slope change region described with reference to
In the description below, modified examples of a semiconductor device will be described with reference to
Each of
In the modified example, referring to
In the modified example, referring to
In the modified example, referring to
In the modified example, referring to
The first pad pattern 224 in
The first conductive pattern 189a may contact the upper surface of the buffer layer 203a and the upper end of the dielectric structure 215, and may cover the upper surface of the first pad pattern 223.
In the modified example, referring to
In the description below, a modified example of the semiconductor device will be described with reference to
In the modified example, referring to
The vertical memory structure VCc may include an insulating core region 329, a first pad pattern 323 on the insulating core region 329, a dielectric structure 315 on a side surface of the insulating core region 329 and a side surface of the first pad pattern 323, a channel layer 326 between the insulating core region 329 and the dielectric structure 315 and between the insulating core region 329 and the first pad pattern 323, and a second pad pattern 332 contacting the channel layer 326 below the insulating core region 329.
The dielectric structure 315 may include a first dielectric layer 316, a data storage layer 318, and a second dielectric layer 320 corresponding to the first dielectric layer 116, the data storage layer 118, and the second dielectric layer 120 of the dielectric structure 115 (in
The structure of the vertical memory structure VCc penetrating through the second stack region ST2 may be substantially the same as the vertical memory structure VCa (in
The vertical memory structure VCc may include a lower vertical region VC_b penetrating through the second stack region ST2, an upper vertical region VC_a extending from the er vertical region VC_b and penetrating through the first stack region ST1, a protruding region VC_pa extending from the upper vertical region VC_a and on a level higher than a level of the upper surface of the stack structure ST, a first width change region VC_v1 between the lower vertical region VC_b and the upper vertical region VC_a, and a second width change region VC_v2a between the upper vertical region VC_a and the protruding region VC_pa. The second width change region VC_v2a may also be defined as a slope change region as described above.
The insulating core region 329 may extend upwardly from a portion penetrating through the stack structure ST. The first pad pattern 323 may be on a level higher than a level of the uppermost interlayer insulating layer 105L1. The channel layer 326 may include a region 326p interposed between the insulating core region 329 and the first pad pattern 323 on a level higher than a level of the uppermost interlayer insulating layer 105L1.
The first pad pattern 323 may include a first side surface 323s1 inclined such that a width of the first pad pattern 323 may increase upwardly, and a second side surface 323s2 on a level higher than a level of the first side surface 323s1, extending from the first side surface 323s1, and inclined such that a width of the first pad pattern 323 may decrease upwardly.
The first conductive pattern 189a may cover the first and second side surfaces 323s1 and 323s2 of the first pad pattern 323. The first conductive pattern 189a may include a metal-semiconductor compound layer in a portion covering the first pad pattern 323, in which case the first conductive pattern 189a may contact the first and second side surfaces 323s1 and 323s2 of the first pad pattern 323.
A component referred to as a “first conductive pattern” may include a metal-semiconductor compound layer in a region contacting a component formed of silicon, e.g., the first pad pattern or the channel layer, unless otherwise indicated.
An upper end of the dielectric structure 315 may be on a level lower than a level of the first pad pattern 323. The first conductive pattern 189a may contact an upper end of the dielectric structure 315. The first conductive pattern 189a may contact the channel layer 326 on a level between the upper end of the dielectric structure 315 and the lower end of the first pad pattern 323.
In the description below, modified examples of a semiconductor device will be described with reference to
Each of
In the modified example, referring to
In the modified example, referring to
The first pad pattern 323 may include a first side surface 323s1 inclined such that the width of the first pad pattern 323 may increase upwardly, a second side surface 323s2 on a level higher than a level of the first side surface 323s1, extending from the first side surface 323s1 and inclined such that the width of the first pad pattern 323 may decrease upwardly, and a flat upper surface 323u extending from the upper end of the second side surface 323s2. The buffer layer 303a may surround the first and second side surfaces 323s1 and 323s2 of the first pad pattern 323. The dielectric structure 315 may extend to a region between the buffer layer 303a and the first pad pattern 323. Upper surfaces of the buffer layer 303a, the dielectric structure 315, and the first pad pattern 323 may be coplanar with each other.
In the modified example, referring to
In the description below, a modified example of the semiconductor device will be described with reference to
In the modified example, referring to
The vertical memory structure VCd may include an insulating core region 429, a first pad pattern 423 on the insulating core region 429, a dielectric structure 415 on a side surface of the insulating core region 429 and a side surface of the first pad pattern, a channel layer 426 between the insulating core region 429 and the dielectric structure 415 and between the insulating core region 429 and the first pad pattern 423, and a second pad pattern 432 contacting the channel layer 426 below the insulating core region 429.
The dielectric structure 415 may include a first dielectric layer 416, a data storage layer 418, and a second dielectric layer 420 corresponding to the first dielectric layer 116, the data storage layer 118, and the second dielectric layer 120 of the dielectric structure 115 (in
The structure of the vertical memory structure VCd penetrating through the second stack region ST2 may be substantially the same as the vertical memory structure VCa (in
The vertical memory structure VCd may include a lower vertical region VC_b penetrating through the second stack region ST2, an upper vertical region VC_a extending from the er vertical region VC_b and penetrating through the first stack region ST1, a protruding region VC_pa extending from the upper vertical region VC_a and on a level higher than a level of the upper surface of the stack structure ST, a first width change region VC_v1 between the lower vertical region VC_b and the upper vertical region VC_a, and a second width change region VC_2a between the upper vertical region VC_a and the protruding region VC_pa. The second width change region VC_2a may also be defined as a slope change region.
The insulating core region 429 may extend upwardly from a portion penetrating through the stack structure ST. The first pad pattern 423 may be on a level higher than a level of the uppermost interlayer insulating layer 105L1. The channel layer 426 may include a region 426p interposed between the insulating core region 429 and the first pad pattern 423 on a level higher than a level of the uppermost interlayer insulating layer 105L1.
The first pad pattern 423 may have a width greater than a width of a portion of the vertical memory structure VCd adjacent to the first pad pattern 423, and on the same level as a level of the uppermost interlayer insulating layer 105L1.
The dielectric structure 415 may include a portion extending from a portion penetrating through the uppermost interlayer insulating layer 105L1 to the upper surface of the uppermost interlayer insulating layer 105L1, and interposed between the first pad pattern 423 and the uppermost interlayer insulating layer 105L1.
The dielectric structure 415 may include a side surface 415s contacting the first conductive pattern 189a on a level higher than a level of the uppermost interlayer insulating layer 105L1. An end portion of the first dielectric layer 416, an end portion of the data storage layer 418, and an end portion of the second dielectric layer 420 may be on the side surface 415s of the dielectric structure 415.
The first pad pattern 423 may include a side surface 423s, an upper surface 423U, and lower surfaces 423L1 and 423L2. In the first pad pattern 423, the lower surfaces 423L1 and 423L2 may include a first lower surface 423L1 contacting the channel layer 426 and a second lower surface 423L2 contacting the second dielectric layer 420 of the dielectric structure 415. The first lower surface 423L1 may extend from the second lower surface 423L2 and may have a concave shape. For example, the first lower surface 423L1 may have a curved shape, and an upper end of the first lower surface 423L1 may be on a level higher than a level of the second lower surface 423L2.
The side surface 415s of the dielectric structure 415 may be aligned with the side surface 423s of the first pad pattern 423.
The first conductive pattern 189a may contact the side surface 415s of the dielectric structure 415, the side surface 423s of the first pad pattern 423 and the upper surface 423U.
In the description below, modified examples of the semiconductor device in will be described with reference to
Each of
In the modified example, referring to
In the modified example, referring to
The buffer layer 303a may surround the side surface 423s of the first pad pattern 423. The dielectric structure 415 may cover the second lower surface 423L2 of the first pad pattern 423, and may extend to a region between the buffer layer 403a and the first pad pattern 423. An end portion of the first dielectric layer 416, an end portion of the data storage layer 418, and an end portion of the second dielectric layer 420 may be on an upper surface 415e of the dielectric structure 415.
Upper surfaces of the buffer layer 403a, the dielectric structure 415, and the first pad pattern 423 may be coplanar with each other. Upper surfaces of the buffer layer 403a, the dielectric structure 415, and the first pad pattern 423 may contact the first conductive pattern 189a.
In the modified example, referring to
In the modified example, referring to
In the description below, a modified example of the semiconductor device will be described with reference to
In the modified example, referring to
The vertical memory structure VCe may include an insulating core region 529 penetrating through the stack structure ST and extending upwardly, a first pad pattern 523 on the side surface of the insulating core region 529 on a level higher than a level of the stack structure ST and on a level lower than a level of the upper surface of the insulating core region 529, a channel layer 526 covering the side surface of the insulating core region 529 and the upper surface of the insulating core region 529, and a first pad pattern 523 between the dielectric structure 515 and the channel layer 526 on a level higher than a level of the stack structure ST.
The dielectric structure 515 may include a first dielectric layer 516, a data storage layer 518, and a second dielectric layer 520 corresponding to the first dielectric layer 516, the data storage layer 118, and the second dielectric layer 120 of the dielectric structure 115 (in
The structure of the vertical memory structure VCd penetrating through the second stack region ST2 may be substantially the same as the vertical memory structure VCa (in
The vertical memory structure VCd may include a lower vertical region VC_b penetrating through the second stack region ST2, an upper vertical region VC_a extending from the lower vertical region VC_b and penetrating through the first stack region ST1, a first protruding region VC_d extending from the upper vertical region VC_a on a level higher than a level of the upper surface of the stack structure ST, a first width change region VC_v1 between the lower vertical region VC_b and the upper vertical region VC_a, a second width change region VC_v2a between the upper vertical region VC_a and the first protruding region VC_d, and a third width change region VC_v3 between the first protruding region VC_d and a second protruding region VC_e.
The insulating core region 529 may extend upwardly from a portion penetrating through the stack structure ST. The first pad pattern 523 may be on a level higher than a level of the uppermost interlayer insulating layer 105L1. The channel layer 526 may include a first region 526e1 interposed between the insulating core region 529 and the first pad pattern 5623 on a level higher than a level of the uppermost interlayer insulating layer 105L1, and a second region 526e2 extending from the first region 526e1 and covering an upper surface and a side surface of the insulating core region 529. The first pad pattern 523 may surround an external side surface of the first region 526e1 of the channel layer 526.
The insulating core region 529 may have a shape in which a width thereof may increase on a level between an upper surface and a lower surface of the first pad pattern 523.
An upper surface, a lower surface, and an external side surface of the first pad pattern 523 may contact the second dielectric layer 520 of the dielectric structure 513, and an internal side surface of the first pad pattern 523 may contact the channel layer 526.
The semiconductor device 1 according to an example embodiment may further include a first buffer layer 507a on the uppermost interlayer insulating layer 105L1 and covering a side surface of the first protruding region VC_d of the vertical memory structure VCe. The first buffer layer 507a may be formed of a silicon layer or, e.g., an insulating material. The first buffer layer 507a may contact the separation structure SS.
The semiconductor device 1 according to an example embodiment may further include a second buffer layer 505 on the first protruding region VC_d and the first buffer layer 507a ,and covering the side surface of the second protruding region VC_e. The second buffer layer 505 may include an insulating material, e.g., silicon oxide.
The first conductive pattern 189a may contact an upper surface of the second buffer layer 505, an upper surface 515U of the dielectric structure 515, and an upper surface 526U of the channel layer 526. The upper surface of the second buffer layer 505, the upper surface 515U of the dielectric structure 515, and the upper surface 526U of the channel layer 526 may be coplanar with each other.
An end portion of the first dielectric layer 516, an end portion of the data storage layer 518, and an end portion of the second dielectric layer 520 may be on the upper surface 515U of the dielectric structure 515.
In the description below, modified examples of a semiconductor device will be described with reference to
Each of
In the modified example, referring to
In the modified example, referring to
The first conductive pattern 189a may contact the upper surface 523U of the first pad pattern 523 and the upper surface and the external side surface of the first doped region 526a of the channel layer 526 on a level higher than a level of the first pad pattern 523.
In the modified example, referring to
Hereinafter, a method of forming a semiconductor device according to an example embodiment will be described with reference to
Referring to
A second semiconductor chip including a memory structure and second bonding pads 170 may be formed (S20). The memory structure may include a stack structure ST including gate layers 140 and interlayer insulating layers 105 alternately stacked, and vertical memory structures VCa penetrating through the stack structure ST.
The second semiconductor chip may include an upper insulating structure 175, contact plugs 150g, 150s, and 150i, the studs 155b, 155g, 155s, and 155i, interconnections 160b, 160g, 160s, and 160i, and a connection structure 165, as described in the aforementioned example embodiments. The second bonding pads 170 may be embedded in the upper insulating structure 175, and may have a surface coplanar with the surface of the upper insulating structure 175.
A bonding semiconductor structure may be formed by bonding the first semiconductor chip to the second semiconductor chip (S30).
A portion of the vertical memory structure VCa and a portion of the contact plugs may be exposed by removing a portion of the second semiconductor chip (S40). The contact plugs may be the source contact plug 150s and the input/output contact plug 150i described above. Accordingly, a second semiconductor chip US′ from which a portion thereof is removed may be formed on the first semiconductor chip LS. As a portion of the vertical memory structure VCa and a portion of the contact plug are exposed, the upper insulating structure 175 around the stack structure ST may be exposed.
A first conductive pattern 189a and a second conductive pattern 189b may be formed (S50). An upper insulating layer 192 and a capping insulating layer 195 may be formed in order (S70). An input/output opening may be formed (S80). The input/output opening may penetrate the capping insulating layer 195 and the upper insulating layer 192 in order, and may expose the second conductive pattern 189b. A conductive input/output pattern 198 may be formed (S80). The input/output conductive pattern 198 may include a portion filling the input/output opening and on the capping insulating layer 195.
Each of the vertical memory structures VCa may be the vertical memory structure described with reference to
In the description below, examples of a method of forming the vertical memory structures described with reference to
First, a method of forming the vertical memory structure VCa described with reference to
Referring to
The shape of the side surface of the channel hole 110 in the portion penetrating through the mold structure MS may be substantially the same as the shape of the side surface of the vertical memory structure VCa (
Referring to
Referring to
Referring to
Referring to
Referring to
A heat treatment process may be performed to diffuse impurities in the first pad pattern 123 and the second pad pattern 132 (in
An upper insulating structure covering the mold structure MS may be formed on the semiconductor substrate 103.
Referring to
Thereafter, the contact plugs 150g, 150s, and 150i, the studs 155b, 155g, 155s, and 155i, the interconnections 160b, 160g, 160s, and 160i, the connection structure 165 and the second bonding pads 170 described in the aforementioned example embodiment with reference to
Thereafter, as described with reference to
Referring to
Thereafter, the first and second conductive patterns 189a and 189b, the upper insulating layer 192, the capping insulating layer 195, and the input/output pattern 198 as in
In the modified example, referring to
In another example, a buffer layer may be formed by allowing a portion of the semiconductor substrate 103 to remain (in
In another example, after the first pad pattern 123 or 124 is formed, the dielectric structure 115 may be partially etched to expose a portion of a side surface of the first pad pattern 123 or 124.
According to an example embodiment, before performing the process of forming the bonding semiconductor structure by bonding the first semiconductor chip to the second semiconductor chip (S30 in
Since the second semiconductor chip including the vertical memory structure VCa is bonded to the first semiconductor chip, after the process of forming the bonding semiconductor structure (S30 in
Accordingly, degradation of performance of the semiconductor device 1 (due to the heat treatment process performed after forming the bonding semiconductor structure) may be prevented. For example, degradation of performance of the semiconductor device 1 (due to a heat treatment process performed after forming the bonding semiconductor structure, e.g., defects due to a subsequent thermal process in a portion in which the first bonding pads 18 and second bonding pads 170 are bonded) may be prevented.
In the description below, a method of forming the vertical memory structure VCb described with reference to
Referring to
A lower channel hole 203 penetrating through the lower mold structure MSa and extending into the semiconductor substrate 103 may be formed. The lower channel hole 203 may have an inclined side surface, such that a width thereof may decrease downwardly. A sacrificial gap-fill layer 205 filling the lower channel hole 203 may be formed.
Referring to
An upper channel hole 207 may be formed to penetrate through the interlayer insulating layers 105 and the mold layers 107 on a level higher than a level of the lower mold structure MSa, and to expose a portion of the upper surface of the sacrificial gap-fill layer 205 (in
The side profile of the channel hole including the lower and upper channel holes 203 and 207 penetrating through the mold structure MS may be substantially the same as the shape of the side surface of the vertical memory structure VCb (in
Referring to
Referring to
Referring to
Referring to
A heat treatment process for diffusing impurities in the first pad pattern 223 and the second pad pattern 232 (in
An upper insulating structure covering the mold structure MS may be formed on the semiconductor substrate 103.
Referring to
Referring to
In another example, the first pad pattern 224 defined in the stack structure ST as illustrated in
In another example, after the first pad pattern 223 or 224 is formed, a portion of the dielectric structure 215 may be etched.
In another example, the buffer layer 203a as in
In the description below, a method of forming the vertical memory structure VCc described with reference to
Referring to
Referring to
Referring to
Referring to
Referring to
A heat treatment process for diffusing impurities in the first pad pattern 323 and the second pad pattern 332 (in
Referring to
Referring to
In another example, the method may further include partially etching the dielectric structure 215.
In another example, the buffer layer 303a as illustrated in
In the description below, a method of forming the vertical memory structure VCd described with reference to
Referring to
A channel hole 407 penetrating through the mold structure MS and exposing the sacrificial pattern 405 may be formed. The shape of the side surface of the channel hole 410 in the portion penetrating through the mold structure MS may be substantially the same as the shape of the side surface of the vertical memory structure VCd (in
Referring to
Referring to
Referring to
A heat treatment process for diffusing impurities in the first pad pattern 423 and the second pad pattern (432 in
Referring to
Referring to
In another example, the dielectric structure 215 on a level higher than a level of the stack structure ST may be partially etched, thereby forming the dielectric structure 215 illustrated in
In another example, the buffer layer 403a as in
In the description below, a method of forming the vertical memory structure VCe described with reference to
Referring to
A mold structure MS, including the interlayer insulating layers 105 and the mold layers 107 alternately stacked on the upper buffer layer 507, may be formed.
A channel hole 510 penetrating through the mold structure MS, the upper buffer layer 507, and the lower buffer layer 505 and extending into the semiconductor substrate 103 may be formed. A shape of the side surface of the channel hole 510 in a portion penetrating through the mold structure MS may be the same as a shape of the side surface of the vertical memory structure VCe (in
Referring to
Referring to
Referring to
By performing a heat treatment process for diffusing impurities in the first pad pattern 523 and the second pad pattern 532 (in
Referring to
Referring to
In another example, by partially etching the second buffer layer 505 and the dielectric structure 215, a portion of the channel layer 526 as illustrated in
In another example, by removing the second buffer layer 505 and the dielectric structure 215 on a level higher than a level of the first pad pattern 523, the channel layer 526 as illustrated in
In another example, the second buffer layer 505, the dielectric structure 215, the channel layer 526, and the insulating core region 529 on a level higher than a level of the first pad pattern 523 may be removed, thereby forming the channel layer 526 as in
In the description below, a data storage system including the semiconductor device according to an example embodiment will be described with reference to
Referring to
In an example embodiment, the data storage system 1000 may be implemented as an electronic system for storing data.
The semiconductor device 1100 may be a semiconductor device according to one of the example embodiments described above with reference to
The first structure 1100F may be the lower structure LS described with reference to
The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. For example, the first structure 1100F may include the peripheral circuit 9 (in
The second structure 1100S may be a memory structure including a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1 and UL2, first and second gate lower lines LL1 and LL2, and memory cell strings CSTR between the bit line BL and the common source CSL.
In the second structure 1100S, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be varied in example embodiments.
In example embodiments, the upper transistors UT1 and UT2 may include string select transistors, and the lower transistors LT1 and LT2 may include ground select transistors. The gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.
The gate layers 140 (in
The gate lower lines LL1 and LL2 may correspond to the plurality of upper gate layers 140L1 and 140L2 in
In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected to each other in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected to each other in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 may be used in an erase operation for erasing data stored in the memory cells using a gate induce drain leakage (GIDL) phenomenon. The erase control gate electrode of the lower erase control transistor LT1 may be at least one of the plurality of upper gate layers 140L1 and 140L2 in
The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through first connection wirings 1115 extending from the first structure 1100F to the second structure 1100S.
The bit lines BL may be electrically connected to the page buffer 1120 through second connection wirings 1125 extending from the first structure 1100F to the second structure 1100S.
In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one of the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130.
The semiconductor device 1100 may further include an input/output pad 1101. The input/output pad 1101 may be the input/output pattern (in
The semiconductor device 1100 may communicate with the controller 1200 through the input/output pad 1101 electrically connected to the logic circuit 1130. The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S. Accordingly, the controller 1200 may be electrically connected to the semiconductor device 1100 through the input/output pad 1101, and may control the semiconductor device 1100.
The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In example embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.
The processor 1210 may control overall operation of the data storage system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 for processing communications with the semiconductor device 1100. A control command for controlling the semiconductor device 1100, data to be written in the memory cell transistors MCT of the semiconductor device 1100, and data to be read from the memory cell transistors MCT may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.
Referring to
The main substrate 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and the arrangement of the plurality of pins in the connector 2006 may be varied depending on a communication interface between the data storage system 2000 and the external host. In example embodiments, the data storage system 2000 may communicate with the external host through one of interfaces such as a universal serial bus (USB), a peripheral component interconnect express (PCI-Express), a serial advanced technology attachment (SATA), and an M-phy for universal flash storage (UFS). In example embodiments, the data storage system 2000 may operate by power supplied from the external host through the connector 2006. The data storage system 2000 may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003.
The controller 2002 may write data in the semiconductor package 2003 or may read data from the semiconductor package 2003, and may improve an operation speed of the data storage system 2000.
The DRAM 2004 may be configured as a buffer memory for mitigating a difference in speeds between the semiconductor package 2003, which may be a data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 may also operate as a cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003. When the DRAM 2004 is included in the data storage system 2000, the controller 2002 further may include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003
The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each of the semiconductor chips 2200 may include a semiconductor device described in one of the aforementioned example embodiments described with reference to
Each of the first and second semiconductor packages 2003a and 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, adhesive layers 2300 on lower surfaces of the semiconductor chips 2200, respectively, a connection structure 2400 electrically connecting the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.
The package substrate 2100 may be configured as a printed circuit board including package upper pads 2130. Each of the semiconductor chips 2200 may include an input/output pad 2210.
In example embodiments, the connection structure 2400 may be a bonding wiring electrically connecting the input/output pad 2210 to the package upper pads 2130. Accordingly, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other through a bonding wire method, and may be electrically connected to the package upper pads 2130 of the package substrate 2100. In example embodiments, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through silicon via (TSV), instead of the connection structure 2400 of a bonding wire method.
In example embodiments, the controller 2002 and the semiconductor chips 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chips 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 may be connected to the semiconductor chips 2200 by wirings formed on the interposer substrate.
Referring to
The first structure 4100 may include a peripheral circuit region including peripheral wiring 4110 and first bonding structures 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, memory channel structures 4220 and a separation structure 4230 penetrating through the gate stack structure 4210, and second bonding structures 4250 electrically connected to the word lines WL (in
Each of the semiconductor chips 2200b may further include an input/output pad 2210 (in
The semiconductor chips 2200 in
In
As described above, embodiments may provide a semiconductor device which may improve integration density, and a data storage system including a semiconductor device.
According to the aforementioned example embodiments, before forming a bonding semiconductor structure by bonding a first semiconductor chip including a peripheral circuit to a second semiconductor chip including a memory structure, the memory structure of the second semiconductor chip may include a vertical memory structure including a channel layer, a first pad pattern contacting the upper region of the channel layer, supplying impurities to the upper region of the channel layer and forming the upper region of the channel layer as a doped region and a second pad pattern contacting the lower region of the channel layer, supplying impurities to the lower region of the channel layer and forming the lower region of the channel layer as a doped region.
Since the second semiconductor chip including the vertical memory structure is bonded to the first semiconductor chip after the bonding semiconductor structure is formed, an ion implantation process for doping the channel layer and a heat treatment process for diffusing impurities may not be performed. Accordingly, degradation of performance of the semiconductor device due to a heat treatment process performed after forming the bonding semiconductor structure, e.g., defects caused by a subsequent thermal process in a portion in which the bonding pads are bonded may be prevented.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2021-0115769 | Aug 2021 | KR | national |
