Semiconductor device and fabrication method thereof

Abstract

A semiconductor device includes: a gate electrode on a semiconductor substrate; side wall spacers on side surfaces of the gate electrode; a source portion and a drain portion in the semiconductor substrate, the source portion and the drain portion being provided laterally to the side wall spacers; an on-source silicide film on the source portion; an on-drain silicide film on the drain portion; source contacts over the source portion; and at least a pair of drain contacts which are provided over the drain portion and which are aligned in the gate width direction of the gate electrode. Part of the drain portion between the pair of drain contacts includes a high resistance region at least in an area between the side wall spacer and edges of the drain contacts facing the gate electrode such that the on-drain silicide film is not provided in the high resistance region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating a structure of an electrostatic discharge protection transistor 50 of Embodiment 1 of the present invention.

FIGS. 2A through 2D are cross sections of the electrostatic discharge protection transistor 50 whose plan view is shown in FIG. 1, wherein FIG. 2A is a cross section taken along the line Ia-Ia′ of FIG. 1, FIG. 2B is a cross section taken along the line Ib-Ib′ of FIG. 1, FIG. 2C is a cross section taken along the line Ic-Ic′ of FIG. 1, and FIG. 2D is a cross section taken along the line Id-Id′ of FIG. 1.

FIGS. 3A through 3E are cross sections with which a fabrication method of a semiconductor device of Embodiment 1 is explained.

FIGS. 4A through 4D are cross sections with which a variation of the fabrication method of the semiconductor device of Embodiment 1.

FIG. 5 is a plan view illustrating a structure of an electrostatic discharge protection transistor 50a of Embodiment 2 of the present invention.

FIGS. 6A and 6B are cross sections of the electrostatic discharge protection transistor 50a whose plan view is shown in FIG. 5, wherein FIG. 6A is a cross section taken along the line Vb-Vb′ of FIG. 5, and FIG. 6B is a cross section taken along the line Vc-Vc′ of FIG. 5.

FIG. 7 is a plan view illustrating a structure of an electrostatic discharge protection transistor 50b of Embodiment 3 of the present invention.

FIG. 8 is a cross section taken along the line VIIb-VIIb′ of the electrostatic discharge protection transistor 50b whose plan view is shown in FIG. 7.

FIG. 9 is a plan view illustrating a structure of an electrostatic discharge protection transistor 50c of Embodiment 4 of the present invention.

FIG. 10 is a cross section taken along the line IXb-IXb′ of the electrostatic discharge protection transistor 50c whose plan view is shown in FIG. 9.

FIG. 11 is a plan view illustrating a structure of an electrostatic discharge protection transistor 50d of Embodiment 5 of the present invention.

FIG. 12 is a cross section taken along the line XIb-XIb′ of the electrostatic discharge protection transistor 50d whose plan view is shown in FIG. 11.

FIG. 13 is a plan view illustrating a structure of a conventional electrostatic discharge protection transistor 100.

FIGS. 14A through 14C are cross sections of the conventional electrostatic discharge protection transistor 100 whose plan view is shown in FIG. 13, wherein FIG. 14A is a cross section taken along the line XIIIa-XIIIa′ of FIG. 13, FIG. 14B is a cross section taken along the line XIIIb-XIIIb′ of FIG. 13, and FIG. 14C is a cross section taken along the line XIIIc-XIIIc′ of FIG. 13.

Claims

1. A semiconductor device comprising: a gate electrode on a semiconductor substrate;side wall spacers on side surfaces of the gate electrode;a source portion and a drain portion in the semiconductor substrate, the source portion and the drain portion being provided laterally to the side wall spacers;an on-source silicide film on the source portion;an on-drain silicide film on the drain portion;at least a pair of source contacts which are provided over the source portion such that the on-source silicide film is interposed between the source portion and the pair of source contacts and which are aligned in the gate width direction of the gate electrode; andat least a pair of drain contacts which are provided over the drain portion such that the on-drain silicide film is interposed between the drain portion and the pair of drain contacts and which are aligned in the gate width direction of the gate electrode,wherein part of the drain portion between the pair of drain contacts includes a high resistance region at least in an area between the side wall spacer and edges of the drain contacts facing the gate electrode such that the on-drain silicide film is not provided in the high resistance region.

2. A semiconductor device of claim 1, wherein the high resistance region extends into an area between the drain contacts.

3. A semiconductor device of claim 1, wherein the on-source silicide film is provided over the whole surface of the source portion.

4. A semiconductor device of claim 1, wherein part of the source portion between the pair of source contacts includes another high resistance region at least in an area between the side wall spacer and edges of the source contacts facing the gate electrode such that the on-source silicide film is not provided in said another high resistance region.

5. A semiconductor device of claim 4, wherein said another high resistance region extends into an area between the source contacts.

6. A semiconductor device of claim 1, further comprising an on-gate silicide film on the gate electrode, wherein the gate electrode includes an on-gate high resistance region in a part planarly continuing from the high resistance region such that the on-gate silicide film is not provided in the on-gate high resistance region.

7. A semiconductor device of claim 4, further comprising an on-gate silicide film on the gate electrode, wherein the gate electrode includes an on-gate high resistance region in a part planarly continuing from said another high resistance region such that the on-gate silicide film is not provided in the on-gate high resistance region.

8. A semiconductor device of claim 1, further comprising a protection film on the high resistance region.

9. A fabrication method of a semiconductor device comprising the steps of: (a) forming a gate electrode on a semiconductor substrate;(b) forming side wall spacers on side surfaces of the gate electrode;(c) forming a source portion and a drain portion in the semiconductor substrate such that the source portion and the drain portion are provided laterally to the side wall spacers;(d) forming an on-source silicide film on the source portion, and forming an on-drain silicide film on the drain portion; and(e) forming at least a pair of source contacts over the source portion such that the on-source silicide film is provided between the source portion and the pair of source contacts and that the pair of source contacts are aligned in the gate width direction of the gate electrode, and forming at least a pair of drain contacts over the drain portion such that the on-drain silicide film is provided between the drain portion and the pair of drain contacts and that the pair of drain contacts are aligned in the gate width direction of the gate electrode,wherein in step (d), in part of the drain portion between the pair of drain contacts, a high resistance region is formed at least in an area between the side wall spacer and edges of the drain contacts facing the gate electrode such that the on-drain silicide film is not provided in the high resistance region.

10. A fabrication method of claim 9, further comprising, after step (c) and before the step (d), forming a protection film on an area of the drain portion which is to be the high resistance region,wherein in step (d), the protection film prevents formation of the on-drain silicide film such that the high resistance region is formed.

11. A fabrication method of claim 10, wherein step (d) includes: forming an on-gate silicide film on the gate electrode; andforming the protection film in an area which planarly and continuously straddles from the drain portion to the gate electrode such that the high resistance region is formed in the area which planarly and continuously straddles from the drain portion to the gate electrode.

12. A fabrication method of claim 9, wherein step (d) includes: forming a metal film on the semiconductor substrate to cover the source portion and drain portion;removing the metal film in an area of the drain portion which is to be the high resistance region; andperforming a thermal treatment to form the on-source silicide film and the on-drain silicide film such that silicidation is prevented in the area which is to be the high resistance region.

13. A fabrication method of claim 12, wherein step (d) includes: forming an on-gate silicide film on the gate electrode;removing the metal film from an area which planarly and continuously straddles from the drain portion to the gate electrode such that the high resistance region is formed in the area which planarly and continuously straddles from the drain portion to the gate electrode.