Claims
- 1. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
an insulating film being formed as a first etching stopper layer to cover a surface including a gate electrode of said peripheral MOS transistor; a second etching stopper layer being formed as an upper layer on a lower layer on a capacitor section of said DRAM memory cell; said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of said capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper; at least one of such impurity diffusion layers being connected to said electrode layer at a boundary between said impurity diffusion layer and a device isolation insulating film; and depth of a bottom portion of said electrode layer formed on said device isolation insulating film from a surface of said impurity diffusion layer being shorter than one of junction depth of said impurity diffusion layer and thickness of said first etching stopper layer.
- 2. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
an insulating film being formed as a first etching stopper layer to cover a surface including a gate electrode of said peripheral MOS transistor; a second etching stopper layer being formed as an upper layer or a lower layer of said capacitor section of said DRAM memory cell; said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of said capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper; a side wall forming layer of said peripheral MOS transistor and said first etching stopper layer being stacked to form a multi-layered film on a word transistor in a region for said DRAM memory cell; said multi-layered film of said side wall forming layer of said peripheral MOS transistor and said first etching stopper layer having a thickness in the range from ¼ to ½ of the minimum distance between word transistors in said region for the DRAM memory cell.
- 3. A manufacturing method of a semiconductor having a DRAM memory cell and a peripheral MOS transistor, comprising the steps of:
making a word transistor of said DRAM memory cell and said peripheral MOS transistor on a semiconductor substrate having formed a device isolating insulating film and device forming regions; stacking an inter-layer insulating film different from said first etching stopper layer on said first etching stopper layer to smooth the entirety by burying a space between word transistors of said DRAM memory cells; forming a second etching stopper layer on said inter-layer insulating film; forming a capacitor of said DRAM memory cell on said second etching stopper layer; forming an insulating film on said capacitor; forming an aperture on said insulating film by etching, and interrupting the etching at said second etching stopper layer; removing said second etching stopper layer and said interlayer insulating film from said aperture by etching, and interrupting the etching at said first etching stopper layer; removing said first etching stopper layer from said aperture by etching, forming at least one of such apertures on a boundary between said impurity diffusion layer and said device isolation insulating film, and adjusting the depth of the bottom of said aperture from an upper surface of said device isolation insulating film smaller than the junction depth of said impurity diffusion layer; forming an electrode layer inside said aperture; and forming a metal wiring layer connected to said electrode layer.
- 4. A manufacturing method of a semiconductor having a DRAM memory cell and a peripheral MOS transistor, comprising the steps of:
making a word transistor of said DRAM memory cell and said peripheral MOS transistor on a semiconductor substrate having formed a device isolation insulating film and device forming regions; stacking an inter-layer insulating film different from said first etching stopper layer on said first etching stopper layer to smooth the entirety by burying a space between word transistors of said DRAM memory cells; forming a second etching stopper layer on said inter-layer insulating film; forming a capacitor of said DRAM memory cell on said second etching stopper layer; forming an insulating film on said capacitor; forming an aperture on said insulating film by etching, and interrupting the etching at said second etching stopper layer; removing said second etching stopper layer and said interlayer insulating film from said aperture by etching, and interrupting the etching at said first etching stopper layer; removing said first etching stopper layer from said aperture by etching, forming at least one of such apertures on a boundary between said impurity diffusion layer and said device isolation insulating film, and adjusting the depth of the bottom of said aperture from an upper surface of said device isolation insulating film smaller than a depth of said first stopper layer; forming an electrode layer inside said aperture; and forming a metal wiring layer connected to said electrode layer.
- 5. A manufacturing method of a semiconductor having a DRAM memory cell and a peripheral MOS transistor, comprising the steps of:
making a gate electrode of a word transistor of said DRAM memory cell and a gate electrode of said peripheral MOS transistor on a semiconductor substrate having formed a device isolation insulating film and device forming regions; stacking an insulating film which covers the gate electrode of the word transistor of said DRAM memory cell and the gate electrode of said peripheral MOS transistor and becomes a side wall forming layer, then conducting anisotropic of said side wall forming region on in a region for making said peripheral MOS transistor to form a side wall on a gate side wall of said peripheral MOS transistor and to maintain said side wall forming layer in a region for making said DRAM memory cell; forming an insulating film to be used as a first etching stopper layer on an impurity diffusion region and a gate electrode in said region of the peripheral MOS transistor region such that thickness of a multi-layered film of said side wall forming layer and said first etching stopper layer become a thickness in the range from ¼ to ½ of the minimum distance between word transistors of said DRAM memory cells; stacking an inter-layer insulating film different from said first etching stopper layer on said first etching stopper layer to smooth the entirety by burying a space between word transistors of said DRAM memory cell; forming a second etching stopper layer on said inter-layer insulating film; forming a capacitor of said DRAM memory cell on said second etching stopper layer; forming an insulating film on said capacitor; forming an aperture on said insulating film by etching, and interrupting the etching at said second etching stopper layer; removing said second etching stopper layer and said interlayer insulating film from said aperture by etching, and interrupting the etching at said first etching stopper layer; removing said first etching stopper layer from said aperture by etching; forming an electrode layer inside said aperture; and forming a metal wiring layer connected to said electrode layer.
- 6. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
an insulating film being formed as a first etching stopper layer to cover an impurity diffusion region and a gate electrode in a peripheral MOS transistor region; a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of said capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper; at least one of such impurity diffusion layers being connected to said electrode layer at a boundary between said impurity diffusion layer and a device isolation insulating film; and depth of a bottom portion of said electrode layer formed on said device isolation insulating film from a surface of said impurity diffusion layer being shorter than junction depth of said impurity diffusion layer.
- 7. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
an insulating film being formed as a first etching stopper layer to cover an impurity diffusion region and a gate electrode in a peripheral MOS transistor region; a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of said capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper; at least one of such impurity diffusion layers being connected to said electrode layer at a boundary between said impurity diffusion layer and a device isolation insulating film; and depth of a bottom portion of said electrode layer formed on said device isolation insulating film from a surface of said impurity diffusion layer being shorter than thickness of said first etching stopper layer.
- 8. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
an insulating film being formed as a first etching stopper layer on an impurity diffusion region and a gate electrode in a peripheral MOS transistor region; a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of said capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper, respectively; a side wall forming layer of said peripheral MOS transistor and said first etching stopper layer being stacked to form a multi-layered film on a word transistor in a region for said DRAM memory cell; said multi-layered film of said side wall forming layer of said peripheral MOS transistor and said first etching stopper layer having a thickness in the range from ¼ to ½ of the minimum distance between word transistors in said region for the DRAM memory cell.
- 9. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
an insulating film being formed as a first etching stopper layer on an impurity diffusion region and a gate electrode in a peripheral MOS transistor region; a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; a side wall forming layer of said peripheral MOS transistor and said first etching stopper layer being stacked to form a multi-layered film on a word transistor in a region for said DRAM memory cell; and said multi-layered film of said side wall forming layer of said peripheral MOS transistor and said first etching stopper layer having a thickness in the range from ¼ to ⅓ of the minimum distance between word transistors in said region for the DRAM memory cell.
- 10. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
an insulating film being formed as a first etching stopper layer on an impurity diffusion region and a gate electrode in a peripheral MOS transistor region; a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; a side wall forming layer of said peripheral MOS transistor and said first etching stopper layer being stacked to form a multi-layered film on a word transistor in a region for said DRAM memory cell; said multi-layered film of said side wall forming layer of said peripheral MOS transistor and said first etching stopper layer having a thickness in the range from ¼ to ½ of the minimum distance between word transistors in said region for the DRAM memory cell; and an oxide film which can flow when it is annealed being formed on said first etching stopper layer in said DRAM memory cell region.
- 11. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
an insulating film being formed as a first etching stopper layer on an impurity diffusion region and a gate electrode in a peripheral MOS transistor region; a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of said capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper, respectively; at least one of gate electrodes of said peripheral MOS transistor being connected to said electrode layer extending through said first etching stopper layer and said second etching stopper layer at a boundary between said gate electrode and a side wall insulating film formed on a side wall of said gate electrode; depth of a bottom portion of said electrode layer formed on said side wall insulating film from the upper surface of said device isolation insulating film being shorter than depth of a bottom portion of said device isolation insulating film.
- 12. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
an insulating film being formed as a first etching stopper layer to cover an impurity diffusion region and a gate electrode in a peripheral MOS transistor region; a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; at least one of electrode layers connected to a bit line of said DRAM memory cells through said second etching stopper layer being located on a device isolation insulating film; and depth of a bottom portion of said electrode layer from a surface of said device isolation insulating film being shorter than thickness of said device isolation insulating film.
- 13. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
an insulating film being formed as a first etching stopper layer to cover an impurity diffusion region and a gate electrode in a peripheral MOS transistor region; a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; at least one of electrode layers connected to a bit line of said DRAM memory cells through said second etching stopper layer being located on an impurity diffusion region; and depth of a bottom portion of an electrode layer reaching said impurity diffusion region through said first etching stopper layer among said electrodes placed on said impurity diffusion region from a surface of said impurity diffusion region being shorter than junction depth of said impurity diffusion region.
- 14. The semiconductor device according to claim 13 wherein said impurity diffusion layer connected to said electrode layer and a bit line of said DRAM memory cell are equal in potential.
- 15. The semiconductor device according to claim 6 wherein an insulating film is formed as a first etching stopper layer on an impurity diffusion region and a gate electrode in a peripheral MOS transistor region;
a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of said capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper, respectively; and thickness of said second etching stopper layer being thicker than thickness of said first etching stopper layer.
- 16. The semiconductor device according to claim 7 wherein an insulating film is formed as a first etching stopper layer on an impurity diffusion region and a gate electrode in a peripheral MOS transistor region;
a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of said capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper, respectively; and thickness of said second etching stopper layer being thicker than thickness of said first etching stopper layer.
- 17. The semiconductor device according to claim 8 wherein an insulating film is formed as a first etching stopper layer on an impurity diffusion region and a gate electrode in a peripheral MOS transistor region;
a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of said capacitor section of said DRAM memory cell by en electrode layer extending through said first etching stopper layer and said second etching stopper, respectively; and thickness of said second etching stopper layer being thicker than thickness of said first etching stopper layer.
- 18. The semiconductor device according to claim 9 wherein an insulating film is formed as a first etching stopper layer on an impurity diffusion region and a gate electrode in a peripheral MOS transistor region;
a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of said capacitor section of said DRAM memory cell by an electrode layer extending though said first etching stopper layer and said second etching stopper, respectively; and thickness of said second etching stopper layer being thicker than thickness of said first etching stopper layer.
- 19. The semiconductor device according to claim 10 wherein an insulating film is formed as a first etching stopper layer on an impurity diffusion region and a gate electrode in a peripheral MOS transistor region;
a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of said capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper, respectively; and thickness of said second etching stopper layer being thicker than thickness of said first etching stopper layer.
- 20. The semiconductor device according to claim 11 wherein an insulating film is formed as a first etching stopper layer on an impurity diffusion region and a gate electrode in a peripheral MOS transistor region;
a second etching stopper layer being formed in an upper level and/or a lower level of a capacitor section of said DRAM memory cell; said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of said capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper, respectively; and thickness of said second etching stopper layer being thicker than thickness of said first etching stopper layer.
- 21. The manufacturing method of a semiconductor device according to claim 5 wherein said insulating film as the first etching stopper layer is formed such that thickness of the multi-layered film made by said side wall forming layer and said first etching stopper layer becomes in the range from ¼ to ⅓ of the minimum distance between word transistors of said DRAM memory cells.
- 22. A manufacturing method of a semiconductor having a DRAM memory cell and a peripheral MOS transistor, comprising the steps of:
making a word transistor of said DRAM memory cell and said peripheral MOS transistor on a semiconductor substrate having formed a device isolation insulating film and device forming regions; stacking an inter-layer insulating film different from said first etching stopper layer on said first etching stopper layer to smooth the entirety by burying a space between word transistors of said DRAM memory cells; forming a second etching stopper layer on said inter-layer insulating film; forming a capacitor of said DRAM memory cell on said second etching stopper layer; forming an insulating film on said capacitor; forming an aperture on said insulating film by etching, and interrupting the etching at said second etching stopper layer; removing said second etching stopper layer and said interlayer insulating film from said aperture by etching, and interrupting the etching at said first etching stopper layer; removing said first etching stopper layer from said aperture by etching, forming at least one of such apertures on a boundary between said gate electrode and said side wall insulating film, and adjusting the depth of the bottom of said aperture formed on said side wall insulating film from an upper surface of said device isolation insulating film smaller than depth of said device isolation insulating film; forming an electrode layer inside said aperture; and forming a metal wiring layer connected to said electrode layer.
- 23. The manufacturing method of a semiconductor device according to claim 3 wherein said second etching stopper layer has a thickness larger than that of said first etching stopper layer,
said method further including a step of removing said second etching stopper layer and said inter-layer insulating film from said aperture by etching, thereafter once interrupting the etching at said first etching stopper layer, and thereafter removing said first etching stopper layer from said aperture.
- 24. A manufacturing method of a semiconductor having a DRAM memory cell and a peripheral MOS transistor, comprising the steps of:
making a word transistor of said DRAM memory cell and said peripheral MOS transistor on a semiconductor substrate having formed a device isolation insulating film and device forming regions; forming an insulating film to be used as a first etching stopper layer on an impurity diffusion region and a gate electrode in said region of the peripheral MOS transistor region; stacking an inter-layer insulating film different from said first etching stopper layer on said first etching stopper layer to smooth the entirety by burying a space between word transistors of said DRAM memory cell; forming a second etching stopper layer on said inter-layer insulating film; forming a capacitor of said DRAM memory cell on said second etching stopper layer; forming an insulating film on said capacitor; forming a first aperture on said insulating film to said gate electrode of said peripheral MOS transistor, and once interrupting the etching at said second etching stopper layer; removing said second etching stopper layer and said inter-insulating film from said first aperture, and once stopping the etching at said first etching stopper layer; removing said first etching stopper layer from said first aperture; forming a second aperture on said insulating film on said capacitor and on an impurity diffusion region of said peripheral MOS transistor, and once stopping the etching at said second etching stopper layer; removing said second etching stopper layer and said inter-layer insulating film from said second aperture, and once stopping the etching at said etching stopper layer; removing said first echoing stopper layer from said second aperture; forming an electrode layer in said first aperture and said second aperture; and forming a metal wiring layer connected to said electrode layer.
- 25. A manufacturing method of a semiconductor having a DRAM memory cell and a peripheral MOS transistor, comprising the steps of:
making a gate electrode of a word transistor of said DRAM memory cell and a gate electrode of said peripheral MOS transistor on a semiconductor substrate having formed a device isolation insulating film and device forming regions; forming an insulating film to be used as a first etching stopper layer on an impurity diffusion region and a gate electrode in said region of the peripheral MOS transistor region; stacking an inter-layer insulating film different from said first etching stopper layer on said first etching stopper layer to smooth the entirety by burying a space between word transistors of said DRAM memory cell; forming a second etching stopper layer on said inter-layer insulating film; forming an insulating film removable by isotropic etching on said second etching stopper layer; selectively forming an aperture in said insulating film removable by isotropic etching, and forming a capacitor lower electrode of said DRAM memory cell inside a guide aperture; removing said insulating film removable by isotropic etching, using said second etching stopper layer as a stopper of isotropic etching; forming a capacitor dielectric film and a capacitor upper electrode on said capacitor lower electrode; forming an insulating film on said capacitor upper electrode; forming an aperture on said insulating film, and once stopping the echoing at said second etching stopper layer; removing said second etching stopper layer and said interlayer insulating film from said aperture by etching, and once stopping the etching at said first echoing stopper layer; removing said first etching stopper layer from said aperture by etching; forming an electrode layer in said aperture; and forming a metal wiring layer connected to said electrode layer.
- 26. A manufacturing method of a semiconductor having a DRAM memory cell and a peripheral MOS transistor, comprising the steps of:
making a gate electrode of a word transistor of said DRAM memory cell and a gate electrode of said peripheral MOS transistor on a semiconductor substrate having formed a device isolation insulating film and device forming regions; forming an insulating film to be used as a first etching stopper layer on an impurity diffusion region and a gate electrode in said region of the peripheral MOS transistor region; stacking an inter-layer insulating film different from said first etching stopper layer on said first etching stopper layer to smooth the entirety by burying a space between word transistors of said DRAM memory cell; forming an aperture in said inter-layer insulating film formed on said DRAM memory cell, and forming an electrode layer connecting to an impurity diffusion region of said DRAM memory cell; forming an inter-layer insulating film covering said electrode layer, and forming a second etching stopper layer on said inter-insulating film; forming an aperture in a location of said second etching stopper layer on said electrode layer connecting to the impurity diffusion region of said DRAM memory cell; forming an etching mask having a smaller contact hole diameter than said aperture by forming a side wall on side walls of said aperture, and forming an aperture on said electrode layer connecting to the impurity diffusion region of said DRAM memory cell by etching using said etching mask; forming a DRAM capacitor connected to the impurity diffusion region of said DRAM memory cell through the aperture on said electrode layer; forming an insulating film on said capacitor; forming an aperture in said insulating film on said capacitor, and in that process, once stopping the etching at said second etching stopper layer; removing said second etching stopper layer and said inter-insulating film from said aperture, and once stopping the etching at said first etching stopper layer; removing said first etching stopper layer from said aperture by etching; forming an electrode layer in said aperture; and forming a metal wiring layer connected to said electrode layer.
- 27. The manufacturing method of a semiconductor device according to claim 26 further comprising the step of forming a bit line on said inter-layer insulating film covering said electrode layer,
said bit line having a line width not larger than the resolution limit of lithography by using a trimming technique.
- 28. A manufacturing method of a semiconductor having a DRAM memory cell and a peripheral MOS transistor, comprising the steps of:
making a word transistor of said DRAM memory cell and said peripheral MOS transistor on a semiconductor substrate having formed a device isolation insulating film and device forming regions; forming an insulating film to be used as a first etching stopper layer on an impurity diffusion region and a gate electrode in said region of the peripheral MOS transistor region; stacking an inter-layer insulating film different from said first etching stopper layer on said first etching stopper layer to smooth the entirety by burying a space between word transistors of said DRAM memory cell; forming an aperture in said inter-layer insulating film formed on said DRAM memory cell, and forming an electrode layer connecting to an impurity diffusion region of said DRAM memory cell; forming an inter-layer insulating film covering said electrode layer, and forming a second etching stopper layer on said inter-insulating film; forming an aperture in a location of said second etching stopper layer on said electrode layer connecting to the impurity diffusion region of said DRAM memory cell; forming an etching mask having a smaller contact hole diameter than said aperture by forming a side wall on side walls of said aperture, and forming an aperture on said electrode layer connecting to the impurity diffusion region of said DRAM memory cell by etching using said etching mask; forming a DRAM capacitor connected to the impurity diffusion region of said DRAM memory cell through the aperture on said electrode layer; forming a capacitor dielectric film and a capacitor upper electrode on a capacitor lower electrode of said DRAM memory cell, and removing at least a part of said second etching stopper layer in the etching process of said capacitor upper electrode; forming a third etching stopper layer on the capacitor lower electrode of said DRAM memory cell; forming an insulating film on said third etching stopper layer; forming an aperture on said insulating film, and once stopping the etching at said third etching stopper layer; removing said third etching stopper layer and said interlayer insulating film from said aperture, and once stopping the etching at said first etching stopper layer; removing said first etching stopper layer from said aperture; forming an electrode layer in said aperture; and forming a metal wiring layer connected to said electrode layer.
- 29. The manufacturing method of a semiconductor device according to claim 28 further comprising a step of making a bit line on said inter-insulating film covering said electrode layer,
said bit line having a line width not larger than the resolution limit of lithography by using a trimming technique.
- 30. A manufacturing method of a semiconductor having a DRAM memory cell and a peripheral MOS transistor, comprising the steps of:
making a word transistor of said DRAM memory cell and said peripheral MOS transistor on a semiconductor substrate having formed a device isolation insulating film and device forming regions; forming an insulating film to be used as a first etching stopper layer on an impurity diffusion region and a gate electrode in said region of the peripheral MOS transistor region; stacking an inter-layer insulating film different from said first etching stopper layer on said first etching stopper layer to smooth the entirety by burying a space between word transistors of said DRAM memory cell; forming a second etching stopper layer on said inter-insulating film; forming a capacitor of said DRAM memory cell on said second etching stopper layer; forming an insulating film on said capacitor; forming an aperture on said insulating film, and once stopping the etching at said second etching stopper layer; removing said second etching stopper layer and said interlayer insulating film from said aperture by etching, and once stopping the etching at said first etching stopper layer; removing said first etching stopper layer from said aperture, forming at least one of such apertures on a boundary between said impurity diffusion layer and said device isolation insulating film, and adjusting the depth of the bottom of said aperture from the upper surface of said device isolation insulating film to be shorter than the junction depth of said impurity diffusion layer; forming an electrode layer in said aperture; and forming a metal wiring layer connected to said electrode layer.
- 31. A semiconductor device comprising:
a device isolation insulating film including a unitary impurity diffusion layer; a peripheral MOS transistor having a gate electrode mounted in communication with the impurity diffusion layer; a first etching stopper layer covering the gate electrode of the peripheral MOS transistor; a DRAM memory cell having a capacitor section; a second etching stopper layer formed on the capacitor section of said DRAM memory cell; and an electrode layer connecting the unitary impurity diffusion layer and the gate electrode to a metal wiring layer formed in the capacitor section of the DRAM memory cell, said electrode layer extending through said first etching stopper layer and said second etching stopper layer, and adjoining the unitary impurity diffusion layer at a boundary between the unitary impurity diffusion layer and the device isolation insulating film; wherein a bottom portion of said electrode layer has a length shorter than at least one of a junction depth of said unitary impurity diffusion layer and a thickness of said first etching stopper layer.
- 32. A semiconductor device as set forth in claim 31 wherein the bottom portion of said electrode layer has a length shorter than the junction depth of said impurity diffusion layer.
- 33. A semiconductor device as set forth in claim 32 wherein the bottom portion of said electrode layer has a length shorter than a thickness of said device isolation insulating film.
- 34. A semiconductor device as set forth in claim 32 wherein the bottom portion of said electrode layer has a length shorter than the thickness of said first etching stopper layer.
- 35. A semiconductor device as set forth in claim 31 wherein the bottom portion of said electrode layer has a length shorter than the thickness of said first etching stopper layer.
- 36. A semiconductor device as set forth in claim 32 wherein the bottom portion of said electrode layer has a length shorter than a thickness of said device isolation insulating film.
- 37. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, said device comprising:
a device isolation insulating film including a unitary impurity diffusion layer; a first etching stopper layer covering a gate electrode of the peripheral MOS transistor; a second etching stopper layer formed in a capacitor section of said DRAM memory cell; and an electrode connecting the impurity diffusion layer and the gate electrode to a metal wiring layer in the capacitor section of the DRAM memory cell, said electrode extending through said first etching stopper layer and said second stopper layer, and adjoining the impurity diffusion layer and the device isolation insulating film; wherein a bottom portion of said electrode has a length shorter than at least one of a junction depth of said impurity diffusion layer and a thickness of said first etching stopper layer.
- 38. A semiconductor device comprising:
a device isolation insulating film including a unitary impurity diffusion layer; a peripheral MOS transistor having a gate electrode mounted in communication with the impurity diffusion layer; a first etching stopper layer covering at least the gate electrode of the peripheral MOS transistor; a DRAM memory cell having a capacitor section; a second etching stopper layer formed on the capacitor section of said DRAM memory cell; and an electrode layer connecting the unitary impurity diffusion layer and the gate electrode to a metal wiring layer formed in the capacitor section of the DRAM memory cell, said electrode layer extending through said first etching stopper layer and said second etching stopper layer, and adjoining the impurity diffusion layer at a boundary between the unitary impurity diffusion layer and the device isolation insulating film; wherein a bottom portion of said electrode layer has a length shorter than at least one of a junction depth of said unitary impurity diffusion layer and a thickness of said first etching stopper layer; and wherein the distance between said first etching stopper layer and said second stopper layer is substantially uniform above at least a portion of the impurity diffusion layer.
- 39. A semiconductor device comprising:
a device isolation insulating film including a unitary impurity diffusion layer; a peripheral MOS transistor having a gate electrode mounted in communication with the impurity diffusion layer; a first etching stopper layer covering at least the gate electrode of the peripheral MOS transistor; a DRAM memory cell having a capacitor section; a second etching stopper layer formed on the capacitor section of said DRAM memory cell; and an electrode layer connecting the unitary impurity diffusion layer and the gate electrode to a metal wiring layer formed in the capacitor section of the DRAM memory cell, said electrode layer extending through said first etching stopper layer and said second etching stopper layer, and adjoining the impurity diffusion layer at a boundary between the unitary impurity diffusion layer and the device isolation insulating film; wherein a bottom portion of said electrode layer has a length shorter than at least one of a junction depth of said unitary impurity diffusion layer and a thickness of said first etching stopper layer; and wherein the distance between said first etching stopper layer and said second stopper layer is substantially uniform above the gate electrode.
Priority Claims (2)
Number |
Date |
Country |
Kind |
P11-291066 |
Oct 1999 |
JP |
|
P2000-275912 |
Sep 2000 |
JP |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims priority of U.S. patent application Ser. No. 09/689,392 filed on Oct. 12, 2002 that claims priority of Japanese Patent Applications No. P11-291066, filed in Oct. 13, 1999, and Japanese Patent Application No.P2000-275912 filed in Sep. 12, 2000, the contents being incorporated herein by reference.
Continuations (1)
|
Number |
Date |
Country |
Parent |
09689392 |
Oct 2000 |
US |
Child |
10350420 |
Jan 2003 |
US |