Semiconductor device and its manufacturing method

Abstract

To realize miniaturization/high integration and increase in the amount of accumulated charges, and to give a memory structure having a high reliability. A 1 transistor 1 capacitor (1T1C) structure having 1 ferroelectric capacitor structure and 1 selection transistor every memory cell is adopted, and respective capacitor structures are disposed respectively in either one layer of interlayer insulating films of 2 layers having different heights from the surface of a semiconductor substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C are general cross-sectional views showing the constitution of the stack type FeRAM according to the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 2A to 2C are general cross-sectional views, subsequent to the FIGS. 1A to 1C, showing the constitution of the stack type FeRAM according to the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 3A to 3C are general cross-sectional views, subsequent to the FIGS. 2A to 2C, showing the constitution of the stack type FeRAM according to the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 4A to 4C are general cross-sectional views, subsequent to the FIGS. 3A to 3C, showing the constitution of the stack type FeRAM according to the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 5A to 5C are general cross-sectional views, subsequent to the FIGS. 4A to 4C, showing the constitution of the stack type FeRAM according to the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 6A to 6B are general cross-sectional views, subsequent to the FIGS. 5A to 5C, showing the constitution of the stack type FeRAM according to the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 7A to 7B are general cross-sectional views, subsequent to the FIGS. 6A to 6B, showing the constitution of the stack type FeRAM according to the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 8A to 8B are general plan views showing the layout in the vicinity of a ferroelectric capacitor structure of a FeRAM.

FIGS. 9A to 9C are general cross-sectional views showing the constitution of the stack type FeRAM according to the modified example 1 of the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 10A to 10B are general cross-sectional views, subsequent to the FIGS. 9A to 9C, showing the constitution of the stack type FeRAM according to the modified example 1 of the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 11A to 11B are general cross-sectional views, subsequent to the FIGS. 10A to 10B, showing the constitution of the stack type FeRAM according to the modified example 1 of the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 12A to 12C are general cross-sectional views showing the constitution of the stack type FeRAM according to the modified example 2 of the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 13A to 13C are general cross-sectional views, subsequent to FIGS. 12A to 12C, showing the constitution of the stack type FeRAM according to the modified example 2 of the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 14A to 14C are general cross-sectional views, subsequent to FIGS. 13A to 13C, showing the constitution of the stack type FeRAM according to the modified example 2 of the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 15A to 15C are general cross-sectional views, subsequent to FIGS. 14A to 14C, showing the constitution of the stack type FeRAM according to the modified example 2 of the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 16A to 16C are general cross-sectional views showing the constitution of the stack type FeRAM according to the modified example 3 of the first-embodiment along with its manufacturing method according to the order of the steps.

FIGS. 17A to 17C are general cross-sectional views, subsequent to FIGS. 16A to 16C, showing the constitution of the stack type FeRAM according to the modified example 3 of the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 18A to 18C are general cross-sectional views, subsequent to FIGS. 17A to 17C, showing the constitution of the stack type FeRAM according to the modified example 3 of the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 19A to 19C are general cross-sectional views, subsequent to FIGS. 18A to 18C, showing the constitution of the stack type FeRAM according to the modified example 3 of the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 20A to 20B are general cross-sectional views, subsequent to FIGS. 19A to 19C, showing the constitution of the stack type FeRAM according to the modified example 3 of the first embodiment along with its manufacturing method according to the order of the steps.

FIGS. 21A to 21C are general cross-sectional views showing the constitution of the planar type FeRAM according to the second embodiment along with its manufacturing method according to the order of the steps.

FIGS. 22A to 22C are general cross-sectional views, subsequent to FIGS. 21A to 21C, showing the constitution of the planar type FeRAM according to the second embodiment along with its manufacturing method according to the order of the steps.

FIGS. 23A to 23C are general cross-sectional views, subsequent to FIGS. 22A to 22C, showing the constitution of the planar type FeRAM according to the second embodiment along with its manufacturing method according to the order of the steps.

FIGS. 24A to 24C are general cross-sectional views, subsequent to FIGS. 23A to 23C, showing the constitution of the planar type FeRAM according to the second embodiment along with its manufacturing method according to the order of the steps.

FIGS. 25A to 25C are general cross-sectional views, subsequent to FIGS. 24A to 24C, showing the constitution of the planar type FeRAM according to the second embodiment along with its manufacturing method according to the order of the steps.

Claims

1. A semiconductor device comprising: a plural memory cells that respectively includesa capacitor structure formed above a semiconductor substrate and constituted by sandwiching a dielectric film with a lower electrode and an upper electrode, anda transistor for selecting the capacitor structure,wherein the capacitor structure of the respective memory cells is respectively formed in either one layer of at least two layers of interlayer insulating films having different heights from the surface of the semiconductor substrate.

2. The semiconductor device according to claim 1 comprising: a constitution wherein, as to the respective capacitor structures, the capacitor structure neighboring said capacitor structure while using the same interlayer insulating film exists.

3. The semiconductor device according to claim 1 comprising: a constitution wherein, as to the respective capacitor structures, said capacitor structure and the capacitor structure neighboring said capacitor structure exist in the different interlayer insulating films.

4. The semiconductor device according to claim 1, wherein the dielectric film is composed of a ferroelectric material having ferroelectric characteristics.

5. The semiconductor device according to claim 4, wherein a protective insulating film covering the respective capacitor structures is formed in the respective interlayer insulating films.

6. The semiconductor device according to claim 1, wherein the memory cell is a stack type one comprising respective connecting plugs to the downside of the lower electrode and the upside of the upper electrode of the respective capacitor structures.

7. The semiconductor device according to claim 1, wherein the memory cell is a planar type one comprising respective connecting plugs to the upside of the lower electrode and the upside of the upper electrode of the respective capacitor structures.

8. The semiconductor device according to claim 1, wherein, between the lower electrode and the connecting plug of the respective capacitor structure, a conductive protective base film having the same shape as said lower electrode is formed.

9. The semiconductor device according to claim 1, wherein a conductive protective base film is formed in at least one site of between the lower electrode and the connecting plug, between the upper electrode and the connecting plug, and between the upside and downside connecting plugs, as a one-layer structure sandwiched between two layers of the interlayer insulating films having been laminated adjacently.

10. The semiconductor device according to claim 6, wherein the connecting plug is composed of a conductive material comprising at least one of W, TiAlN, TiN, Al, Cu, Ru, SRO and Ir.

11. A manufacturing method of a semiconductor device comprising plural memory cells, comprising the steps of: forming a transistor above a semiconductor substrate; andforming one capacitor structure constituted by sandwiching a dielectric film with a lower electrode and an upper electrode above the transistor so as to correspond to one of the transistor,wherein the capacitor structure of the respective memory cells is formed in either one layer of at least two layers of interlayer insulating films having different heights from the surface of the semiconductor substrate.

12. The manufacturing method of a semiconductor device according to claim 11, wherein the respective capacitor structures are formed in a constitution that the capacitor structure neighboring said capacitor structure while using the same interlayer insulating film exists.

13. The manufacturing method of a semiconductor device according to claim 11, wherein the respective capacitor structures are formed in a constitution that said capacitor structure and the capacitor structure neighboring said capacitor structure exist in the different interlayer insulating films.

14. The manufacturing method of a semiconductor device according to claim 11, wherein the dielectric film is formed from a ferroelectric material having ferroelectric characteristics.

15. The manufacturing method of a semiconductor device according to claim 14 further comprising the step of: forming a protective insulating film covering the respective capacitor structures in the respective interlayer insulating films.

16. The manufacturing method of a semiconductor device according to claim 15, wherein the dielectric film is formed by an MOCVD method.

17. The manufacturing method of a semiconductor device according to claim 11, wherein the memory cell is a stack type one comprising respective connecting plugs to the downside of the lower electrode and the upside of the upper electrode of the respective capacitor structures.

18. The manufacturing method of a semiconductor device according to claim 11, wherein the memory cell is a planar type one comprising respective connecting plugs to the upside of the lower electrode and the upside of the upper electrode of the respective capacitor structures.

19. The manufacturing method of a semiconductor device according to claim 11 further comprising the steps of: forming a conductive protective base film, between the lower electrode and the connecting plug of the respective capacitor structures, having the same shape as said lower electrode.

20. The manufacturing method of a semiconductor device according to claim 11 further comprising the steps of: forming a conductive protective base film in at least one site of between the lower electrode and the connecting plug, between the upper electrode and the connecting plug, and between the upside and downside connecting plugs, as a one-layer structure sandwiched between two layers of the interlayer insulating films having been laminated adjacently.