SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

Abstract

In a semiconductor device, a body thick film transistor and a body thin film transistor having a different body film thickness are formed on the same SOI substrate (silicon support substrate, buried oxide film and silicon layer). The body film is formed to be relatively thick in the body thick film transistor, which has a recess structure where the level of the surface of the source/drain regions is lower than the level of the surface of the body region, and thus, the SOI film in the source/drain regions is formed to be as thin as the SOI film in the body thin film transistor. On the other hand, the entirety of the SOI film is formed to have a relatively thin film thickness in the body thin film transistor. In addition, the source/drain regions are formed to penetrate through the silicon layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 20 are cross sectional views showing a first aspect of a manufacturing method for a semiconductor device according to a first embodiment of the present invention;

FIGS. 21 to 44 are cross sectional views showing the second aspect of a manufacturing method for a semiconductor device according to the first embodiment;

FIGS. 45 to 63 are cross sectional views showing a third aspect of a manufacturing method for a semiconductor device according to the first embodiment;

FIGS. 64 to 67 are cross sectional views showing the first aspect of a manufacturing method for a semiconductor device according to a second embodiment of the present invention;

FIG. 68 is a cross sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention;

FIGS. 69 to 71 are cross sectional views showing a part of a manufacturing method for a semiconductor device according to the third embodiment;

FIG. 72 is a cross sectional view showing the structure of the first aspect of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 73 is a cross sectional view showing the structure of the second aspect of a semiconductor device according to the fourth embodiment;

FIG. 74 is a cross sectional view showing the structure of the third aspect of a semiconductor device according to the fourth embodiment;

FIGS. 75 to 80 are cross sectional views showing a manufacturing method for a semiconductor device according to the third aspect of the fourth embodiment;

FIGS. 81 to 94 are cross sectional views showing a manufacturing method for a semiconductor device according to a fifth embodiment;

FIG. 95 is a plan view showing the structure of a semiconductor device according to the fifth embodiment;

FIG. 96 is a cross sectional view showing the cross section along B-B of FIG. 95;

FIG. 97 is an illustration diagram showing an example of the configuration of a semiconductor integrated circuit which is formed using the semiconductor device according to the fifth embodiment;

FIG. 98 is a circuit view showing part of the internal configuration of an SRAM circuit;

FIG. 99 is a circuit view showing the internal configuration of a voltage controlled oscillation circuit;

FIG. 100 is a circuit view showing part of the internal configuration of a nonvolatile memory circuit;

FIG. 101 is an illustration diagram schematically showing the internal configuration of an ESD circuit;

FIGS. 102 to 111 are cross sectional views showing a manufacturing method for a conventional MOS transistor formed on an SOI substrate;

Claims

1. A semiconductor device, which includes insulating gate type first and second transistors formed on an SOI substrate composed of a semiconductor support substrate, a buried insulating film and a semiconductor layer, wherein said semiconductor layer includes first and second SOI regions having a first and a second film thicknesses, and said first film thickness is greater than said second film thickness,said first and second transistors are formed in the first and second SOI regions, and each comprises:a gate insulating film selectively formed on said semiconductor layer;a gate electrode formed on said gate insulating film; andsource/drain regions formed in said semiconductor layer to sandwich a body region, which is a region of said semiconductor layer beneath said gate electrode, and to penetrate through said semiconductor layer, whereinsaid source/drain regions in said first transistor have a recess structure where the level of the surface thereof is lower than the level of the surface of said body region.

2. The semiconductor device according to claim 1, wherein each of said first and second transistors further comprises:a low concentration region of the same conductivity type as said source/drain regions in the interface between said body region and said source/drain regions in a region in the vicinity of said buried insulating film.

3. The semiconductor device according to claim 1, further comprising: a third transistor formed in said first SOI region, whereinsaid third transistor comprises:a gate insulating film selectively formed on said semiconductor layer;a gate electrode formed on said gate insulating film; andsource/drain regions formed in said semiconductor layer to sandwich the body region which is a region of said semiconductor layer beneath said gate electrode and not to have said recess structure and to leave a portion of said semiconductor layer beneath without penetrating thorough said semiconductor layer.

4. The semiconductor device according to claim 3, wherein each of said first to third transistors comprises:a body contact region in which a body potential is provided; anda partial isolation region composed of an insulator formed in an upper layer part of said semiconductor layer and a partial semiconductor region in the semiconductor layer which is a layer beneath the insulator, whereinsaid body contact region is electrically connected to said body region via said partial semiconductor region in said partial isolation region.

5. The semiconductor device according to claim 1, further comprising: a complete isolation region having an insulating film which penetrates through said semiconductor layer between said first and second SOI regions.

6. The semiconductor device according to claim 3, further comprising the complete isolation region comprising the insulating film which penetrates through said first SOI region between the regions where said first and third transistors are formed.

7. A semiconductor device, which includes insulating gate type first and second transistors formed on an SOI substrate composed of a semiconductor support substrate, a buried insulating film and a semiconductor layer, wherein each of said first and second transistors comprises:a gate insulating film selectively formed on said semiconductor layer;a gate electrode formed on said gate insulating film; andsource/drain regions formed in said semiconductor layer to sandwich a body region which is a region of said semiconductor layer beneath said gate electrode, whereinsaid source/drain regions in said first transistor have a recess structure where the level of the surface thereof is lower than the level of the surface of said body region, and said source/drain regions are formed to penetrate through said semiconductor layer, andsaid source/drain regions in said second transistor do not have said recess structure and are formed to leave a portion of said semiconductor layer beneath without penetrating through said semiconductor layer.

8. A semiconductor device which includes insulating gate type transistors formed on a semiconductor substrate, wherein said transistors comprise:a gate insulating film selectively formed on said semiconductor layer;a gate electrode formed on said gate insulating film;source/drain regions formed to sandwich a body region which is a region of said semiconductor layer beneath said gate electrode, said source/drain regions having a recess structure where the level of the surface is lower than the level of the surface of said body region, in terms of the positional relationship; anda portion for forming a nitride film covering said transistors having said recess structure and including at least a nitride film.

9. The semiconductor device according to claim 8, wherein said semiconductor substrate includes an SOI substrate composed of a semiconductor support substrate, a buried insulating film and a semiconductor layer, andsaid source/drain regions include source/drain regions which penetrate through said semiconductor layer,said transistor further comprises:wall portions formed adjacent to the sides of said gate electrode.

10. The semiconductor device according to claim 8, wherein said semiconductor substrate includes a single semiconductor substrate,said source/drain regions include source/drain regions formed in an upper layer part of said semiconductor substrate, andsaid transistor further comprises:wall portions formed adjacent to the sides of said gate electrodes.

11. The semiconductor device according to claim 9, said transistor further comprises:second side wall portions formed on the sides of said side wall portions, whereinsaid source/drain regions have said recess structure in regions outside the portions beneath said second side wall portions relative to said body region.

12. The semiconductor device according to claim 8, wherein said portion for forming a nitride film includes:an oxide film formed to cover said transistors having said recess structure, andsaid nitride film formed on said oxide film.

13. The semiconductor device according to claim 8, wherein said portion for forming a nitride film includes a nitride film which is formed directly to cover said transistor having said recess structure.

14. A manufacturing method for a semiconductor device which includes insulating gate type first and second transistors, comprising the steps of: (a) preparing an SOI substrate composed of a semiconductor support substrate, a buried insulating film and a semiconductor layer;(b) providing a first SOI region having a first film thickness and a second SOI region having a second film thickness which is smaller than said first film thickness by changing the film thickness in a portion of said semiconductor layer;(c) forming a pattern for element isolation for said first and second transistors above said semiconductor layer;(d) forming an element isolation region for said first and second transistors on the basis of said pattern for element isolation; and(e) forming first and second transistors in said first and second SOI regions, wherein said step (e) comprises the steps of:(e-1) forming a gate insulating film and a gate electrode on each of said first and second SOI regions selectively and in sequence;(e-2) forming a recess outside the body region beneath said gate electrode in said first SOI region; and(e-3) forming source/drain regions in said semiconductor layer to sandwich said body region and to penetrate through said semiconductor layer in said first and second SOI regions, said source/drain regions in said first SOI region formed at least beneath said recess, whereinsaid gate insulating film, said gate electrode and said source/drain regions formed in said first and second SOI regions define said first and second transistors, respectively.

15. The manufacturing method for a semiconductor device according to claim 14, wherein said step (c) includes the step of forming a pattern for said element isolation without flattening a portion above said semiconductor layer.

16. The manufacturing method for a semiconductor device according to claim 14, further comprising a step of (f) forming a flattened layer on said semiconductor layer so that the levels at which said first and said second SOI regions are formed coincide and the surface is flattened, the step (f) being performed after said step (b) and before said step (c), whereinsaid step (c) includes the step of forming a pattern for said element isolation on said flattened layer.

17. The manufacturing method for a semiconductor device according to claim 16, wherein said flattened layer includes:a pad film; anda polysilicon film formed on said pad film, andsaid step (i) comprises the steps of:(f-1) forming said pad film and said polysilicon film in sequence; and(f-2) flattening said polysilicon film through a polishing process using said pad film as a stopper.

18. The manufacturing method for a semiconductor device according to claim 16, wherein said flattened layer includes a nitride film, andsaid step (f) comprises the steps of:(f-1) providing an opening by removing an upper layer part of said nitride film in said first SOI region; and(f-2) flattening said nitride film having said opening through a polishing process.