This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2012-178887, filed Aug. 10, 2012; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device and a manufacturing method thereof.
In the related art, semiconductor devices prepared by connecting electrodes to semiconductor layers and having them sealed off by a sealing resin body have been put into practical use. For such semiconductor devices, by reflow, the tips of the electrodes are jointed to the wiring of the assembling substrate via solder for assembling on the assembling substrate. However, due to the thermal stress generated between the semiconductor layer and the assembling substrate, the semiconductor device and the associated joint portion may be damaged.
Embodiments described herein provide a semiconductor device with high durability to thermal stress and a manufacturing method of. Embodiments are described below with reference to the drawings.
A semiconductor device according an embodiment has a semiconductor layer and an electrode coupled to a semiconductor layer. The electrode includes first and second end portions, the first end portion being closer to the semiconductor layer than the second end portion. The first end portion is formed to have crystals of a first grain size, and the second end portion is formed to have crystals of a second grain size that is larger than the first grain size.
A manufacturing method of a semiconductor device according to an embodiment includes forming a semiconductor layer, forming a first electrode portion on the semiconductor layer by a first electroplating method, and forming a second electrode portion on the first electrode portion by a second electroplating method, wherein an electroplating rate of the first electroplating method is lower than an electroplating rate of the second electroplating method.
Another manufacturing method of a semiconductor device according to an embodiment includes the following processes: forming a semiconductor layer on a first substrate, forming trenches to divide the semiconductor layer into several portions in an upper layer portion of the semiconductor layer and the first substrate, forming a wall-shaped member in an interior and upper portion of the trenches, forming a second substrate on the semiconductor layer, removing the first substrate, forming a protective film on a lower surface of the semiconductor layer, and removing the wall-shaped member.
The semiconductor device 1 according to the first embodiment is assembled on an assembling substrate 52 via solder 51 for use. In the semiconductor device 1, a semiconductor layer 11 is arranged. The semiconductor layer 11 is an LED (light emitting device) layer that contains, for example, the nitride of group III (13th group) element, such as gallium nitride (GaN), and emits blue light. In the semiconductor layer 11, an n-type layer 11n, a light emitting layer 11h, and a p-type layer 11p are laminated in order. For convenience of explanation, the side that is ahead in the direction from the semiconductor device 1 towards the assembling substrate 52 is referred to as “lower side”. However, it is irrelevant to the direction of gravity.
An n-type electrode 12 made of, for example, aluminum (Al), and a p-type electrode 13 made of, for example, silver (Ag) are arranged on the lower side of the semiconductor layer 11. The n-type electrode 12 is coupled to the lower surface of the n-type layer 11n. The p-type electrode 13 is coupled to the lower surface of the p-type layer 11p. A seed layer 14 is arranged on the lower side of each of the n-type electrode 12 and the p-type electrode 13. The seed layer 14 is, for example, a two-layer film prepared by laminating a titanium (Ti) layer and a copper layer. Here, the titanium layer is in contact with the n-type electrode 12 and the p-type electrode 13. The electrodes 15 made of, for example, copper (Cu) are arranged on the lower side of the seed layer 14. A metal film 16 is provided on the lower surface of the electrode 15. In the metal film 16, a nickel (Ni) layer 16a in contact with the electrode 15 and a gold (Au) layer 16b in contact with the nickel layer 16a are laminated in order. That is, the seed layer 14, the electrode 15 and the metal film 16 are arranged pair by pair.
Also, in the semiconductor device 1, a sealing resin body 18 is arranged to cover the semiconductor layer 11, the n-type electrode 12, the p-type electrode 13, the seed layer 14, the electrode 15 and the metal film 16. The lower surface of the gold layer 16b of the metal film 16 is exposed on the lower surface of the sealing resin body 18. The portion of the sealing resin body 18 arranged on the region right above the semiconductor layer 11 is made of a transparent resin, and a phosphor (not shown in the drawing) is dispersed in the portion.
In each electrode 15, the crystal grain size varies in the up/down direction. More specifically, the crystal grain size in an upper portion 15a of each electrode 15, that is, the crystal grain size in the portion of the electrode on the side near the semiconductor layer 11, is smaller than the crystal grain size at a lower portion 15b of the electrode 15, that is, the crystal grain size in the portion on the side opposite to the semiconductor layer 11. Here, the metal film 16 is formed on the end surface (lower surface) of the lower portion 15b of the electrode 15.
For example, the electrodes 15 may be formed by electroplating of copper on the seed layer 14.
As shown in
The operation and effects of the present embodiment are explained below.
The semiconductor device 1 is assembled on the assembling substrate 52 by joining the lower end portion of each electrode 15 on the wiring (not shown in the drawing) of the assembling substrate 52 via a metal film 16 and a solder 51. For example, tips of the electrodes 15 (e.g., a second end portion) are coupled to a wiring of the assembling substrate 52 by way of solder 51. In this case, a thermal stress takes place between the semiconductor device 1 and the assembling substrate 52. Then, the assembled semiconductor device 1 is turned on by supplying electric power from the wiring of the assembling substrate 52 to the semiconductor layer 11 via the solder 51, the metal film 16, the electrodes 15, the seed layer 14, and the p-type electrode 13 or the n-type electrode 12. In this case, in company with on/off of power supply, the temperature in the semiconductor layer 11 changes up/down, so that a thermal stress is generated between the semiconductor layer 11 and the assembling substrate 52 and inside the semiconductor device 1.
In the semiconductor device 1 of the present embodiment, the crystal grain size of the upper portion 15a of each electrode 15 is smaller, so that it is possible to absorb the generated thermal stress better than the case when the entirety of the electrode 15 has the same crystal grain size. A cause is as follows: the copper crystals that form the upper portion 15a can make relative movement within a certain range, so that the thermal stress can be relaxed. Consequently, the semiconductor device 1 according to the present embodiment has a high durability to the thermal stress.
On the other hand, for the semiconductor device 1 according to the present embodiment, the lower portion 15b of each electrode 15 is formed at a higher film forming rate, so that the crystals have a larger crystal grain size. As a result, compared with the case when the overall electrode 15 is formed at a lower film forming rate and all of the crystal grains in each electrode 15 have a smaller size, in the present case, the electrodes 15 can be formed at a higher efficiency. Consequently, it is possible to cut the manufacturing cost of the semiconductor device 1.
A test example illustrating the relationship between the crystal grain size of each electrode and the durability to thermal stress are explained below.
As the semiconductor layer 11, an LED layer that emits blue light is formed, and the n-type electrode 12 and the p-type electrode 13 are formed on the lower surface of this LED layer. Then, titanium on the lower surfaces of the n-type electrode 12 and the p-type electrode 13 is plated, and copper is plated, so that the seed layer 14 is formed. Then, on the lower surface of the seed layer 14, copper is plated to form the electrodes 15.
In this case, in the application example, after a copper film with a thickness of 10 μm is formed at a film forming rate of 1 μm/min, a copper film with a thickness of 100 μm is formed at a film forming rate of 10 μm/min. As a result, for each electrode 15, the crystal grain size in the upper portion 15a is smaller than the crystal grain size in the lower portion 15b. On the other hand, in the comparative example, a 110 μm-thick copper film is formed at a film forming rate of 10 μm/min. As a result, each electrode has nearly the same uniform crystal grain size, and the crystal grain size is almost equal to that of the lower portion of the electrodes in the application example. Here, the crystal grain size of the electrodes can be confirmed by a transmissive electron microscope or an X-ray topography.
Then, on each electrode 15, the nickel layer 16a is formed, and the gold layer 16b is formed, so that the metal film 16 is formed. Then, the semiconductor layer 11, then-type electrode 12, the p-type electrode 13, the seed layer 14, the electrode 15 and the metal film 16 are sealed off by a resin. By removing the resin from the lower surface of the metal film 16, the sealing resin body 18 is formed. As a result, the semiconductor device 1 according to the application example and a semiconductor device 21 according to the comparative example are manufactured, respectively.
Then, the semiconductor device 1 and the semiconductor device 21 manufactured above each are placed on an assembling substrate 52. In this case, the metal film 16 contacts the solder 51 arranged on the assembling substrate 52. Then, the assembling substrate having the semiconductor device placed thereon is loaded in a reflow oven. As a result, the solder is melted and then re-solidified, so that the metal film 16 is soldered on the wiring of the assembling substrate 52, and the electrodes 15 are coupled to the wiring of the assembling substrate 52 via the metal film 16 and the solder 51. As a result, the semiconductor device 1 and the semiconductor device 21 each are assembled on the assembling substrate 52. Then, for each of the samples obtained by assembling the semiconductor device on the assembling substrate 52, a thermal cycle test is carried out between temperatures at −40° C. to temperatures at +120° C. for 1000 cycles.
As shown in
(1) separation 31 between the sealing resin body 18 and the semiconductor layer 11,
(2) separation 32 between the sealing resin body 18 and the electrode 15,
(3) separation 33 between the metal film 16 and the solder 51,
(4) cracks 34 on the sealing resin body 18, and
(5) decrease in light emitting output power of the semiconductor device 21.
On the other hand, for the samples according to present embodiments, none of the above-listed problems (1) to (5) takes place.
In the first embodiment, an example of the electrodes 15 being made of copper has been shown. However, the material for making the electrodes 15 is not limited to copper. In the first embodiment, an example has also been shown in which, for each of the electrodes 15, the crystal grain sizes of the two stages, that is, the upper portion 15a and the lower portion 15b, are different from each other. However, this is merely an example, and the present disclosure is not limited to the scheme. For example, the crystal grain size of the electrode 15 may be different, for example, of more than 3 stages, or the crystal grain size may also vary continuously from the upper end to the lower end. In this case, too, the crystal grain size in the upper end portion of each electrode 15, that is, the crystal grain size in the end portion on the side near the semiconductor layer 11 is smaller than the crystal grain size in the lower end portion of each electrode 15, that is, in the end portion on the side opposite to the semiconductor layer 11.
In addition, the material for the semiconductor layer 11 is not limited to gallium nitride. For example, one may also use the nitrides of aluminum (Al), indium (In), and other group-III elements other than gallium (Ga). In addition, the layer structure of the seed layer 14 is not limited to the (Ti/Cu) two-layer structure. Any type of metal layer that can increase close contact property on the n-type electrode 12, the p-type electrode 13 and the electrode 15 and can suppress thermal diffusion of copper to the side of the semiconductor layer 11 can be used. For example, the seed layer 14 may also be a layer made of palladium (Pd), or a two-layer film prepared by laminating a titanium layer and a palladium layer.
In the following, a modified example of the first embodiment is explained.
As shown in
As shown in
Then, on the upper surface of the silicon substrate 61, a semiconductor layer 62 is formed. For example, the semiconductor layer 62 is an LED layer, such as a layer containing InxAlyGazN (x+y+z=1). In the following, according to the present embodiment, in order to facilitate explanation, the side that is ahead in the direction from the silicon substrate 61 towards the semiconductor layer 62 is referred to as “upper side”. This definition is also adopted in the third and the fourth embodiments to be explained later. This definition is opposite to that in the first embodiment and in
In the following, as shown in
Then, as shown in
In the following, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
In the following, the operation and effects of the present embodiment are explained below.
According to the present embodiment, without carrying out dicing, it is possible to manufacture multiple semiconductor devices 65 at the same time. As a result, it is possible to reduce the manufacturing cost of the semiconductor devices 65. When the trenches 62a and wall-shaped members 63 are formed, it is possible to adopt the lithographic method. Consequently, compared with the dicing method, it is possible to decrease the width of the portions to be removed from the reinforcing substrate 64 and the semiconductor layer 62. Consequently, it is possible to form more semiconductor devices 65 from a single wafer, so that it is possible to cut the manufacturing cost and material cost for each semiconductor device.
Also, according to the present embodiment, the wall-shaped members 63 can be formed en bloc and removed en bloc. Consequently, even when the semiconductor devices 65 are miniaturized, there is still no increase in the processing cost. On the other hand, when the semiconductor devices 65 are formed as individual pieces by dicing, in company with miniaturization of the semiconductor devices 65, the number of the dicing lines for each wafer increases, and the processing time becomes longer. Also, as the number of the semiconductor devices 65 for each wafer is increased, the width of the dicing portions becomes smaller, decreasing the yield. As a result, when the semiconductor devices are formed as individual pieces by dicing, various problems take place in company with miniaturization.
In addition, when the individual semiconductor devices are formed by dicing, the dicing lines should be straight lines that pass through the entirety of the wafer. On the other hand, according to the present embodiment, as the wall-shaped members 63 are formed by, for example, the lithographic method, the shape of the wall-shaped members 63 is not limited to the straight linear shape, so the degree of freedom of the layout is high. Consequently, the shape of the semiconductor devices 65 has a high degree of freedom. For example, one may also adopt a scheme in which the wall-shaped members 63 are formed in a honeycomb shape, and the semiconductor devices 65 are formed in a hexagonal shape.
In the following, a modified example of the present embodiment is explained.
According to the present modified example, instead of the process shown in
According to the second embodiment, the order of the process of grinding of the reinforcing substrate 64 shown in
In the explanation of the present embodiment, members similar to those of the second embodiment are identified with the same numerals and signs as in the second embodiment, and detailed explanation of processes similar to those in the second embodiment is omitted.
As shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Operations and effects of the present embodiment are explained below. According to the present embodiment, in the process shown in
According to the present embodiment, as an example, as the protective film 74, a film having phosphor dispersed in a transparent resin is formed. However, the present disclosure is not limited to the scheme. For example, one may also adopt a scheme in which no phosphor is contained in the protective film 74. When the semiconductor layer 62 is not an LED layer, the protective film 74 may be made of a light shielding material. In each case, the protective film 74 works as a protective film in protecting the semiconductor layer 62.
In the explanation of the present embodiment, members similar to those of the third embodiment are identified with the same numerals and signs as in the third embodiment, and detailed explanation of processes similar to those in the third embodiment are omitted.
As shown in
Then, an insulating film 85 is formed on the entire surface. Then, by selectively remove the insulating film 85, an opening portion 85a is formed on the upper surface of the n-type electrode 83, and an opening portion 85b is formed on the upper surface of the p-type electrode 84, and an opening portion 85c is formed in each prescribed region as the dividing region between the semiconductor devices. The opening portion 85c is formed to surround the prescribed region as each semiconductor device.
Then, as shown in
Then, as shown in
Then, a seed layer 86 is formed in the region including the interior of the opening portion 85a of the insulating film 85 and the region right above this interior region, the region including the interior of the opening portion 85b and the region right above this interior region, and the region including the interior of the opening portion 85c and the region right above this interior region, respectively.
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
In the semiconductor device 90 manufactured in this way, the semiconductor layer 82 is arranged by laminating the n-type layer 82n, the light emitting layer 82h and the p-type layer 82p in order, and, on the semiconductor layer 82, the n-type electrode 83 and p-type electrode 84 are arranged separated from each other. The n-type electrode 83 is coupled to the n-type layer 82n of the semiconductor layer 82, and the p-type electrode 84 is coupled to the p-type layer 82p of the semiconductor layer 82. The insulating film 85 covers the entirety of the upper surface of the semiconductor layer 82, the entirety of the side surface and a portion of the upper surface of the n-type layer 82n, the entirety of the side surface of the light emitting layer 82h, and the entirety of the side surface and a portion of the upper surface of the p-type layer 82p. The electrodes 87 are arranged on the n-type electrode 83 and the p-type electrode 84, respectively, and are coupled to the n-type electrode 83 and p-type electrode 84, respectively. On the periphery and between the electrodes 87, the reinforcing substrate 64 made of a resin material is arranged. The upper surface of the electrodes 87 is exposed on the upper surface of the reinforcing substrate 64. On the other hand, the protective film 88 is arranged on the lower surface of the semiconductor layer 82. As the protective film 88, phosphor is dispersed in a transparent resin.
In the following, the operation and effects of the present embodiment are explained below.
According to the present embodiment, in the process shown in
According to the present embodiment, the crystal grain size in the portion of the electrodes 87 near the side of the semiconductor layer 82 is made smaller, and the crystal grain size in the portion on the side opposite to the semiconductor layer 82 is made larger. As a result, just as the first embodiment, it is possible to guarantee a high productivity of the semiconductor device 90, and it is possible to improve the durability to the thermal stress. The remaining features of the manufacturing method as well as the operation and effects of the present embodiment are the same as those in the third embodiment.
According to the embodiment, it is possible to realize a semiconductor device with a high durability to the thermal stress and a manufacturing method of the same.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
---|---|---|---|
2012-178887 | Aug 2012 | JP | national |