Patent Application
20230335596
The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including an electrode structure and a manufacturing method thereof.
In semiconductor technology, group III-V compound semiconductor such as gallium nitride (GaN) have the material characteristics of low on-resistance and high breakdown voltage. A high electron mobility transistor (HEMT) made of group III-V compound semiconductor can be used to construct various integrated circuit (IC) devices, such as high-power field effect transistors or high-frequency transistors. A HEMT includes compound semiconductor layers with different energy band gaps, such as a high energy band gap semiconductor layer and a low energy band gap semiconductor layer, which are stacked on each other and thus generate a heterojunction between the semiconductor layers. This heterojunction with discontinuous energy band causes two-dimensional electron gas (2-DEG) to be formed near the heterojunction, and the 2-DEG can be used to transport carriers in the HEMT. Compared with conventional MOSFETs, HEMTs have many attractive characteristics, such as high electron mobility and the ability to transmit signals at high-frequency, because HEMTs use 2-DEG instead of a doped region as the carrier channel of MOSFETs.
For conventional HEMTs, an electrode structure is used to be electrically connected to a semiconductor layer below the electrode structure, so that current can flow between the electrode structure and the semiconductor layer. However, power loss often occurs when current flows through the electrode structure and the semiconductor layer, which reduces the performance in electrical characteristic of the device.
In view of this, it is necessary to provide an improved semiconductor device to improve the defects of conventional semiconductor devices.
According to some embodiments of the present disclosure, a semiconductor device is disclosed, which includes a semiconductor stack, an insulating structure, an electrode structure, and a protective layer. The insulating structure is disposed on the semiconductor stack and includes a first portion. The first portion includes a first opening exposing an inner sidewall of the insulating structure. The protective layer is disposed between the inner sidewall and the electrode structure, and includes a second opening. The electrode structure is disposed in the first opening and in contact with the protective layer, and the electrode structure is electrically connected to the semiconductor stack through the second opening. The electrode structure includes a metal material, the insulating structure includes a first material, and the protective layer includes a second material.
According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device is disclosed, which includes the following steps. A semiconductor stack is provided. Then, a first insulating layer is disposed on the semiconductor stack, wherein the first insulating layer includes a first opening exposing an inner sidewall of the first insulating layer. A protective layer is filled into the first opening to cover the inner sidewall. Subsequently, the protective layer is etched to remove a portion of the protective layer in the first opening to form a second opening. Then, an electrode structure is disposed so that the protective layer is sandwiched between the electrode structure and the inner sidewall. A heat treatment process is then performed at a treatment temperature. The first insulating layer includes a first material, the protective layer includes a second material, and the electrode structure includes a metal material.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “over,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” and/or “beneath” other elements or features would then be oriented “above” and/or “over” the other elements or features. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
It is understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer and/or section discussed below could be termed a second element, component, region, layer and/or section without departing from the teachings of the embodiments.
As disclosed herein, the term “about” or “substantial” generally means within 20%, 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. Unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages disclosed herein should be understood as modified in all instances by the term “about” or “substantial”. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired.
In the present disclosure, a “group III-V semiconductor” refers to a compound semiconductor that includes at least one group III element and at least one group V element, where group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and group V element may be nitrogen (N), phosphorous (P), arsenic (As), or antimony (Sb). Furthermore, the group III-V semiconductor may refer to binary semiconductor, ternary semiconductor, quaternary semiconductor, compound semiconductor beyond quaternary semiconductor, or a combination thereof, but not limited thereto. For example, the group III-V semiconductor is binary semiconductor, such as aluminum nitride (AlN), gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), or gallium arsenide (GaAs), ternary semiconductor, such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium aluminum arsenide (InAlAs), or indium gallium arsenide (InGaAs), or quaternary semiconductor such as indium aluminum gallium nitride (InAlGaN). Besides, based on different requirements, group III-V semiconductor may contain dopants to become semiconductor with specific conductivity type, such as n-type or p-type.
Although the disclosure is described with respect to specific embodiments, the principles of the invention, as defined by the claims appended herein, can obviously be applied beyond the specifically described embodiments of the invention described herein. Moreover, in the description of the present disclosure, certain details have been left out in order to not obscure the inventive aspects of the disclosure. The details left out are within the knowledge of a person of ordinary skill in the art.
According to some embodiments of the present disclosure, the protective layer 120 is disposed between the electrode structure 130 and the first portion 116 of the insulating structure 114, and the second material of the protective layer 120 is selected from the material whose reaction temperature with the metal material of the electrode structure 130 is higher than the reaction temperature between the first material of the insulating structure 114 and the metal material of the electrode structure 130. The protective layer 120 made of the above selected material can prevent the electrode structure 130 from directly contacting the first portion 116 of the insulating structure 114, thus avoiding unnecessary chemical reactions (such as oxidation reactions) between the electrode structure 130 and the insulating structure 114. In this way, the increase in contact resistance between the electrode structure 130 and the underlying semiconductor layer can be avoided, which is caused by the chemical reactions between the electrode structure 130 and the insulating structure 114.
In addition to the above components and layers, the semiconductor device 100 may further include other optional components and layers. The components and layers of the semiconductor device 100 are further described below.
Referring to
The semiconductor stack 104 is disposed on the substrate 102 and includes a plurality of group III-V semiconductor layers. For example, the semiconductor stack 104 includes a buffer layer 106, a channel layer 108, and a barrier layer 110 stacked in sequence from bottom to top. The buffer layer 106 can be used to reduce the degree of stress or lattice mismatch between the substrate 102 and the semiconductor stack 104. The buffer layer 106 can include a plurality of group III-V sub-semiconductors, which can form a composition ratio gradient layer or a super lattice structure, wherein the composition ratio gradient layer means that the composition ratio of the semiconductor sub-layers adjacent to each other can continuously change along a certain direction, such as aluminum gallium nitride (AlxGa(1-x)N) with a gradually changed composition ratio, and the value of x decreases in a continuous or stepwise manner along the direction away from the substrate 102. The super lattice structure includes alternately stacked semiconductor sub-layers with slightly different composition ratios, and these semiconductor sub-layers are adjacent to each other and appear in pairs (for example, paired Alx1Ga(1-x1)N and Alx2Ga(1-x2)N, 0≤X1≤0.2, 0.2≤X2≤0.5) as the smallest repeating unit in the super lattice structure.
The channel layer 108 is disposed on the substrate 102, for example, disposed on the buffer layer 106. The channel layer 108 may include one or more group III-V semiconductor layers, and the compositions of the group III-V semiconductor layers may be GaN, AlGaN, InGaN or InAlGaN, but not limited thereto. For example, the channel layer 108 is an undoped group III-V semiconductor, such as undoped-GaN (u-GaN).
The barrier layer 110 is disposed on the channel layer 108. The barrier layer 110 may include one or more group III-V semiconductor layers, and the composition of the group III-V semiconductor layers of the barrier layer 110 may be different from that of the channel layer 108. For example, the material of the barrier layer 110 may include a material with a larger energy band gap than an energy band gap of the material of the channel layer 108, such as AlN, AlxGa(1-x)N (0 < x < 1), or a combination thereof. According to one embodiment of the present disclosure, the barrier layer 110 may be an n-type group III-V semiconductor, such as an intrinsic n-type AlGaN layer, but not limited thereto.
Because there is an energy band gap discontinuity between the channel layer 108 and the barrier layer 110, a potential well can be formed in the channel layer 108 near the heterojunction between the channel layer 108 and the barrier layer 110 by stacking the channel layer 108 and the barrier layer 110 with each other. Electrons can be accumulated in the potential well due to the piezoelectric effect, thus producing a sheet with high electron mobility, i.e., two-dimensional electron gas (2-DEG) region 109.
According to different requirements, the semiconductor stack 104 may include other semiconductor layers such as group III-V semiconductor layers, which are disposed between the substrate 102 and the buffer layer 106 or between the buffer layer 106 and the barrier layer 110. For example, the semiconductor stack 104 may further include a nucleation layer (not shown) or a high resistance layer (not shown), wherein the nucleation layer is a group III-V semiconductor layer, such as AlN or other nitride semiconductor layer, which can make the semiconductor layers disposed above the nucleation layer have better crystal quality. The high-resistance layer such as carbon-doped gallium nitride (c-GaN) is disposed on the buffer layer 106, and the electrical resistivity of the high-resistance layer is higher than the electrical resistivity of other layers, thus preventing the current leakage between the semiconductor layers disposed above the high-resistance layer and the substrate 102.
The cap layer 112 is disposed on the semiconductor stack 104 and between the insulating structure 114 and the semiconductor stack 104. The cap layer 112 can be used to eliminate or reduce the surface defects existing on the surface of the barrier layer 110, thereby improving the electron mobility of the two-dimensional electron gas region 109. The cap layer 112 can also be used to protect the underlying semiconductor stack 104 from the damages caused during an etching process, such as an etching process for forming a contact opening. Referring to the enlarged diagram of a partial region at the bottom of
The insulating structure 114 is disposed on the cap layer 112. In addition to the first portion 116, the insulating structure 114 further includes a second portion 118 disposed on the first portion 116. Referring to the enlarged diagram of a partial region at the bottom of
6 The protective layer 120 is disposed on the first portion 116 of the insulating structure 114, so that a portion of the protective layer 120 fills the first opening 170 of the first portion 116 and conformally covers the inner sidewall 162 of the first portion 116. In certain embodiments, other portions of the protective layer 120 can extend out of the first opening 170 and conformally cover a portion of the top surface 164 of the first portion 116. Two opposite protective layers 120 define a second opening 172, and the bottom of the second opening 172 has a second width W2. Although the protective layers 120 shown in
Electrode structures 130, such as a drain electrode 132 and a source electrode 134, are disposed on the cap layer 112. The electrode structures 130 fill not only the second opening 172 but also a recess 174 in the cap layer 104, so as to be electrically connected to the underlying semiconductor layers, such as the channel layer 108 and the barrier layer 110. The electrode structures 130 can be ohmic contact with the underlying cap layer 112 and some layers (such as the channel layer 108) in the semiconductor stack 104. The material of the electrode structure 130 may be a low-impedance metal, such as aluminum, but not limited thereto.
The arrangement of the cap layer 112, the insulating structure 114 (including the first portion 116 and the second portion 118), the protective layer 120, and the electrode structure 130 is further described as follows. Referring to the enlarged diagram of the partial region at the bottom of
Regarding the material of the first portion 116 of the insulating structure 114, the material of the protective layer 120, and the material of the electrode structure 130, in one embodiment, when the material of the electrode structure 130 is easily oxidized (e.g., metal with a work function from 4.0 eV to 4.4 eV), the electrode structure 130 is prone to react, such as chemical reactions (e.g., oxidation reactions), with nonmetallic element in the material of the first portion 116, resulting in products with low conductivity (e.g., metal oxides). In order to avoid the product with low conductivity, the protective layer 120 is disposed between the electrode structure 130 and the first portion 116. The second material of the protective layer 120 has a characterize which is more difficult to react with the metal material of the electrode structure 130 than that of the first material of the insulating structure 114. The reaction temperature between the second material of the protective layer 120 and the electrode structure 130 is higher than the reaction temperature between the first material of the insulating structure 114 and the electrode structure 130. So the protective layer 120 can avoid the electrode structure 130 from directly contacting the first portion 116 of the insulating structure 114 and reacting with the insulating structure 114. In this case, the chemical reaction between the electrode structure 130 and the first portion 116 of the adjacent insulating structure 114 can be avoided, thereby preventing the electrical resistivity of the electrode structure 130 to increase. In some embodiments, the reaction temperature between the second material of the protective layer 120 and the electrode structure 130 is high enough to the extent that no reaction occurs between the second material of the protective layer 120 and the metal material of the electrode structure 130. In this case, a chemical reaction between the electrode structure 130 directly contacting the first portion 116 of the insulating structure 114 can be avoided.
The semiconductor device 100 may include an additional conductive layer such as a gate electrode 136 disposed on one side of the electrode structure 130, for example, between two electrode structures 130. The gate electrode 136 is disposed on the cap layer 112 and filled into the contact opening in the insulating structure 114, so that a portion of the gate electrode 136 penetrates through the first portion 116 and the second portion 118 of the insulating structure 114. Furthermore, the gate electrode 136 is an asymmetric structure and extends toward the drain electrode 132. The extended portion and the corresponding end of the gate electrode 136 cover the first portion 116 and the second portion 118 of the insulating structure 114 and can serve as a field plate of the semiconductor device 100 to control the electric field distribution and/or the peak value of the electric field in the underlying semiconductor stack 104.
According to some embodiments of the present disclosure, the gate electrode 136, the cap layer 112 located directly below the gate electrode 136, and the channel layer 108 located below the gate electrode 136 can constitute a metal-insulator-semiconductor (MIS) capacitor structure. In this case, during the operation of the semiconductor device 100, the current can be blocked by the cap layer 112 and does not flow between the gate electrode 136 and the channel layer 108. In addition, according to some embodiments of the present disclosure, the gate electrode 136 can penetrate through the cap layer 112 and directly contact the barrier layer 110 to form a Schottky contact structure with the barrier layer 110. In this case, the current does not easily flow through the Schottky contact junction between the gate electrode 136 and the barrier layer 110 during the operation of the semiconductor device 100.
A third insulating layer, such as a dielectric interlayer 140, is disposed on the insulating structure 114 and the gate electrode 136. The dielectric interlayer 140 includes contact openings to expose the underlying drain electrode 132 and source electrode 134, respectively.
At least two bond pad structures 150 are disposed in the contact openings in the dielectric interlayer 140 to be electrically connected to the drain electrode 132 and the source electrode 134, respectively. The top surfaces of the bond pad structures 150 are exposed from the dielectric interlayer 140 to serve as regions through which the semiconductor device 100 and external devices are electrically connected. The semiconductor device 100 may also include another bond pad structure (not shown) electrically connected to an electrode structure (such as the gate electrode 136). The material of the dielectric interlayer 140 includes insulating materials, such as Si3N4, AlN, or other insulating nitride materials, Al2O3, SiO2 or other insulating oxide materials, or SiON as an insulating oxide material or an insulating nitride material, but not limited thereto.
In addition to the above embodiments, the semiconductor device of the present disclosure may include other embodiments and is not limited to the foregoing embodiments. In the following paragraphs, various modifications and variations about semiconductor devices are disclosed and the description below is mainly focused on differences among these embodiments. In addition, the present disclosure may repeat reference numerals and/or letters in the various modifications and variations. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
In order to enable one of ordinary skill in the art to implement the disclosed invention, the method of manufacturing the semiconductor device is further described in detail below.
Next, in step 404 of the manufacturing method 400, a first insulating layer is disposed on the semiconductor stack, where the first insulating layer includes a first opening, and the first opening exposes the inner sidewall of the first insulating structure. Referring to the cross-sectional view 302 of
Then, in step 406 of the manufacturing method 400, a protective layer is filled into the first opening to cover the inner sidewall. Referring to the cross-sectional view 304 of
Next, in step 408 of the manufacturing method 400, the protective layer is etched to remove the protective layer located in the first opening. Referring to a cross-sectional view 306 of
Next, in step 410 of the manufacturing method 400, the electrode structure is disposed so that the protective layer is sandwiched between the electrode structure and the inner sidewall. Referring to the cross-sectional view 308 of
Then, in step 412 of the manufacturing method 400, a heat treatment process is performed, where the temperature of the heat treatment process is higher than the first reaction temperature and lower than the second reaction temperature. Referring to cross-sectional view 308 of
After the stage of the manufacturing process shown in
Then, by performing deposition and patterning processes, a conductive layer such as a gate electrode 136 is formed on the second portion 118, and the gate electrode 136 can fill up the first contact opening 182 and the second contact opening 184. The gate electrode 136 can extend outward from the second contact opening 184 and has an asymmetric cross-section. The material of the gate electrode 136 may include metal, alloy, semiconductor, or stacked layers thereof. For example, the gate electrode 136 may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), other suitable conductive materials, or a combination thereof.
After the stage of manufacturing process shown in
Then, at least two bond pad structures (not shown), which are disposed in the third contact openings 186 of the dielectric interlayer 140, are formed and electrically connected to the drain electrode 132 and the source electrode 134, respectively. The top surfaces of the bond pad structures are exposed from the dielectric interlayer 140 and serve as regions through which the semiconductor device 100 and external devices are electrically connected. Another bond pad structure (not shown) may also be formed to be electrically connected to the gate electrode 136. Thus, the semiconductor device 100 shown in
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210412049.2 | Apr 2022 | CN | national |
