Patent Application
20150008507
The disclosure of Japanese Patent Application No. 2013-141637 filed on Jul. 5, 2013 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a manufacturing method of a semiconductor device having a MONOS flash memory including a plurality of gates.
Conceivable examples of a semiconductor device having an embedded flash memory or CPU (Central Processing Unit) include a microcomputer. For example, for a flash memory, a nonvolatile memory which is an element in which recorded information remains even when the power supply thereof is turned off is preferably used. By embedding the nonvolatile memory and a logic semiconductor device over the same semiconductor substrate, a microcomputer having a high function can be formed. The microcomputer in which the nonvolatile memory and the logic semiconductor device are placed is used widely in industrial machinery, home electric appliances, automobile-mounted devices, and the like.
In general, in a nonvolatile memory included in a microcomputer, a program needed by the microcomputer is stored and read as necessary to be used. Accordingly, a microcomputer in which a nonvolatile memory and a logic semiconductor device are embedded is used preferably. Examples of a nonvolatile memory appropriate for such embedment with a logic semiconductor device include a flash memory having a split-gate structure in which a control MIS (Metal Insulator Semiconductor) transistor and a storage MIS transistor are integrally formed.
As the flash memory having the split-gate structure, e.g., a MONOS flash memory using MONOS (Metal Oxide Nitride Oxide Silicon) for the storage MIS transistor is used. In the MONOS flash memory, a memory gate electrode as the gate electrode of the storage transistor containing an n-type impurity is typically used. The flash memory including the n-type memory gate electrode is capable of a high-speed operation and has high reliability. The flash memory including the n-type memory gate is used widely for an application in a high-end region, such as, e.g., a vehicle-mounted MCU (Micro Controller Unit).
To apply the MONOS flash memory to a low-end region and a middle-end region, it is requested to develop a device at cost lower than that of a related-art MONOS flash memory. To respond to the request, the development of a memory gate electrode containing a p-type impurity has been promoted. A flash memory including a p-type memory gate electrode is disclosed in, e.g., Japanese Unexamined Patent Publication No. 2012-114269 (Patent Document 1).
In the MONOS flash memory including the n-type memory gate electrode, during each of a data write operation and a data erase operation, electrons or holes need to be moved so as to pass through the one of a plurality of stacked layers of insulating films located on the semiconductor substrate side (underside) of the memory gate electrode which is closest to the semiconductor substrate (lowermost layer). This may degrade the lifetime of the lowermost-layer insulating film and reduce the number of times a re-write operation can be performed to the MONOS flash memory.
On the other hand, in the MONOS flash memory including the p-type memory gate electrode, electrons are moved so as to pass through the foregoing lowermost-layer insulating film during a data write operation but, during a data erase operation, holes are moved so as to pass through the one of the plurality of stacked layers of insulating films located on the semiconductor substrate side (underside) of the memory gate electrode which is closest to the memory gate electrode (uppermost layer). This gives no damage to the foregoing lowermost-layer insulating film. Accordingly, it is possible to increase the number of times a data write operation and a data erase operation can be repeatedly performed to the foregoing insulating film.
Japanese Unexamined Patent Publication No. 2012-114269
In Patent Document 1, the p-type memory gate electrode is formed first, and then n-type source/drain regions are formed. In this case, if the source/drain regions are formed by, e.g., implanting an n-type impurity into the semiconductor substrate using the memory gate electrode as a mask, the n-type impurity is implanted into the p-type memory gate electrode to offset the concentration of the p-type impurity implanted in the memory gate electrode. This significantly reduces the concentration of the p-type impurity in the memory gate electrode and may possibly impair the function of the memory gate electrode. It may also be possible that a part of the n-type impurity implanted in the memory gate electrode passes through the memory gate electrode to enter the semiconductor substrate located thereunder. This is because the memory gate electrode has a thickness smaller than that of the control gate electrode as the gate electrode of the control transistor so that the distance the impurity needs to travel to pass through the memory gate electrode is shorter.
The memory gate has not only a small thickness but also a shape in which the uppermost surface thereof is inclined. Accordingly, it is difficult to form, e.g., a photoresist having the same end surface as that of the memory gate electrode into a pattern with high accuracy. Therefore, it is difficult to implant the n-type impurity for the source region into a region in the semiconductor substrate which is located externally of the memory gate electrode in a state where the memory gate electrode is covered with the photoresist.
For the reason described above, in Patent Document 1, the source region in the semiconductor substrate which is located externally of the memory gate electrode is formed only of a low-concentration impurity diffusion layer.
In the MONOS flush memory thus having only the source region which is the low-concentration impurity diffusion layer, an electric characteristic (e.g., so-called I-V characteristic) is degraded and the electric resistance is high so that I is unlikely to increase in proportion to the magnitude of V. When the I-V characteristic is degraded to reduce a current value, the drive speed of the MONOS flash memory decreases to reduce a data rewrite speed. This may degrade the performance of the MONOS flash memory.
There is a concern that, in the source region in Patent Document 1, the intensity of an electric field increases in the low-concentration impurity diffusion layer to increase a leakage current (junction leakage) in the junction portion between the source region and the semiconductor substrate. When the junction leakage is increased, a current during a data write (rewrite) operation to the MONOS flash memory undergoes a loss, which may possibly reduce a data write speed.
Other problems and novel features of the present invention will become apparent from a statement in the present specification and the accompanying drawings.
A semiconductor device according to an embodiment includes a semiconductor substrate, a first gate electrode, a second gate electrode, an insulating film, and a pair of source/drain regions. The first gate electrode is formed of a semiconductor layer containing an impurity of a first conductivity type. The second gate electrode is formed of a semiconductor layer containing an impurity of a second conductivity type. Each of the source/drain regions contains an impurity of the first conductivity type. The source region includes a first source region, and a second source region having a concentration of the first-conductivity-type impurity higher than that of the first source region.
In a method of manufacturing the semiconductor device according to the embodiment, the semiconductor substrate is provided first and, over a main surface thereof, the first gate electrode and a dummy gate electrode are formed. Using the foregoing dummy gate electrode as a mask, the source region is formed in the main surface. After the foregoing dummy gate electrode is removed, the second gate electrode is formed. In a state where the foregoing second gate electrode is covered, the drain region is formed in the main surface. Into a semiconductor film intended to serve as the first gate electrode, the impurity of the first conductivity type is introduced and, into a semiconductor film intended to serve as the second gate electrode, the impurity of the second conductivity type is introduced. When the foregoing source and drain regions are formed, the impurity of the first conductivity type is implanted into the semiconductor substrate. When the foregoing source region is formed, the first source region and the second source region having the concentration of the impurity of the first conductivity type higher than that of the first source region are formed.
The semiconductor device of the embodiment and the manufacturing method thereof allow a semiconductor device to be provided in which a data re-write operation can be performed a larger number of times and a data re-write operation is performed at a higher speed.
An embodiment will be described below on the basis of the drawings. First, a description will be given of a configuration of a semiconductor device of the embodiment.
Referring to
In the memory cell region MCR, e.g., a flash memory is formed as a nonvolatile memory. The flash memory is a MONOS flash memory which has a split-gate structure and in which two transistors, i.e., a control transistor having a control gate electrode CG as the gate electrode thereof and a storage transistor having a memory gate electrode MG as the gate electrode thereof are coupled to each other.
Each of the memory cells has a control gate insulating film GI formed over the main surface S1 of the semiconductor substrate SUB and the control gate electrode CG. The control gate insulating film GI and the control gate electrode CG form the control transistor. Each of the memory cells also has a memory gate insulating film ONI formed over the main surface S1 of the semiconductor substrate SUB and the memory gate electrode MG. The memory gate insulating film ONI and the memory gate electrode MG form the storage transistor. Each of the memory cells also has sidewall insulating films SW formed over the main surface S1 so as to cover the side surfaces of the control gate electrode CG and the memory gate electrode MG.
Note that the two memory cells in
Each of the control gate insulating films GI is formed of the same material as that of a gate insulating film in a typical MOS (Metal Oxide Semiconductor) transistor, such as a silicon oxide film. The control gate insulating film GI is formed so as to enhance the adhesion between the semiconductor substrate SUB and the control gate electrode CG and suppress interface states.
Each of the control gate electrodes CG as a first gate electrode performs read/write/erase operations and is formed of a thin film of polysilicon (semiconductor layer) containing a generally known n-type impurity (impurity of a first conductivity type).
Each of the memory gate electrodes MG as a second gate electrode performs write/erase flash operations and is located so as to be adjacent to the control gate electrode CG in the memory cell. The memory gate electrode MG is formed of a thin film of polysilicon (semiconductor layer) containing a generally known p-type impurity (impurity of a second conductivity type).
The control gate electrode CG is formed such that the uppermost surface thereof most distant from the semiconductor substrate SUB extends in a direction generally along the main surface S1 of the semiconductor substrate SUB. Accordingly, the thickness of the control gate electrode CG in the thickness direction of the semiconductor substrate SUB is substantially constant irrespective of the position at which the control gate electrode CG is formed. On the other hand, the uppermost surface of the memory gate electrode MG most distant from the semiconductor substrate SUB may extend in a direction along the main surface S1 of the semiconductor substrate SUB or may also have a cross-sectional shape which is inclined with distance from the control gate electrode CG toward the semiconductor substrate SUB, as shown in
The memory gate insulating film ONI (insulating film) extends from a region interposed between the memory gate electrode MG and the semiconductor substrate SUB in continuous relation to a region interposed between the control gate electrode CG and the memory gate electrode MG. That is, the memory gate insulating film ONI is bent such that the extending direction thereof changes (e.g., about) 90° between the region interposed between the memory gate electrode MG and the semiconductor substrate SUB and the region interposed between the control gate electrode CG and the memory gate electrode MG.
The pair of source region MS and the drain region MD are formed such that at least a channel region (in the semiconductor substrate SUB, i.e., in the p-type well region PW1) immediately under the control gate electrode CG (and the control gate insulating film GI) is interposed therebetween. That is, the control gate electrode CG on the left-hand side of
Sidewall insulating films SW include the drain-side sidewall insulating films SW each formed on the side of the control gate electrodes CG where the drain regions MD are located so as to cover the side surfaces of the control gate electrodes CG (so as to be adjacent to the control gate electrodes CG) and the source-side sidewall insulating films SW each formed on the side of the memory gate electrodes MG where the source regions MS are located so as to cover the side surfaces of the memory gate electrodes MG (so as to be adjacent to the memory gate electrodes MG). Each of the sidewall insulating films SW is preferably formed of, e.g., a silicon nitride film, but may also have a laminate structure including a silicon oxide film and a silicon nitride film.
The source region MS is formed on the side of the two memory cells where the memory gate electrodes MG facing each other are located and includes lower-concentration source regions MS1 each as a first source region and a higher-concentration source region MS2 as a second source region. The lower-concentration source regions MS1 and the higher-concentration source region MS2 are impurity diffusion regions each formed in the p-type well region PW1 and containing a first-conductivity-type, i.e., n-type impurity.
The lower-concentration source regions MS1 are located generally immediately under the source-side sidewall insulating films SW. The higher-concentration source region MS2 is formed in the region adjacent to the lower-concentration source regions MS1 in a direction generally along the main surface S1 of the semiconductor substrate SUB. In other words, the higher-concentration source region MS2 is located externally of the source-side sidewall insulating films SW. That is to say, the higher-concentration source region MS2 is formed in the region generally interposed between the two lower-concentration source regions MS1 and in the p-type well region PW1 immediately under the region generally interposed between the two source-side sidewall insulating films SW facing each other. In the present embodiment, the source region MS and the drain regions MD are formed such that the channel regions immediately under the control gate electrodes CG and the memory gate electrodes MG are interposed therebetween.
The higher-concentration source region MS2 includes an upper source region MS2a and a lower source region MS2b. The upper source region 2a is formed between the two lower-concentration source regions MS1. The depth of the upper source region MS2a in the thickness direction (vertical direction in
That is, the lower source region MS2b is formed at a position more distant (in the downward direction in the drawing) from the main surface S1 of the semiconductor substrate SUB than that of the upper source region MS2a. In general, the thickness (in the vertical direction in the drawing) of the lower source region MS2b is preferably larger than the thickness of the upper source region MS2a, but it is not limited thereto. Since the higher-concentration source region MS2 has the configuration in which the two source regions MS2a and MS2b are thus stacked in the vertical direction in the drawing, the higher-concentration source region MS2 is formed thicker (deeper) in the vertical direction in the drawing than the lower-concentration source regions MS1.
Each of the drain regions MD is formed on the side of each of the memory cells where the control gate electrode CG is located and has a lower-concentration drain region MD1 as a first drain region and a higher-concentration drain region MD2 as a second drain region. The lower-concentration drain region MD1 and the higher-concentration drain region MD2 are impurity diffusion regions each formed in the p-type well PW1 and containing an impurity of n-type as a first conductivity type.
The lower-concentration drain regions MD1 are formed in the p-type well region PW1 generally immediately under the drain-side sidewall insulating films SW. The higher-concentration drain regions MD2 are formed in the regions adjacent to the lower-concentration drain regions MD1 in a direction generally along the main surface S1 of the semiconductor substrate SUB. In other words, the higher-concentration drain regions MD2 are located externally of the drain-side sidewall insulating films SW.
Each of the higher-concentration drain regions MD2 has an upper drain region MD2a and a lower drain region MD2b. The upper drain region MD2 is formed in the region adjacent to the lower-concentration drain region MD1 in the direction along the main surface S1 of the semiconductor substrate SUB. The depth of the upper drain region MD2a in the thickness direction (vertical direction in
That is, the lower drain region MD2b is formed at a position more distant (in the downward direction in the drawing) from the main surface S1 of the semiconductor substrate SUB than that of the upper drain region MD2a. In general, the thickness (in the vertical direction in the drawing) of the lower drain region MD2b is preferably larger than the thickness of the upper drain region MD2a, but it is not limited thereto. Since the higher-concentration drain region MD2 has the configuration in which the two drain regions MD2a and MD2b are thus stacked in the vertical direction in the drawing, the higher-concentration drain region MD2 is formed thicker (deeper) in the vertical direction in the drawing than the lower-concentration drain region MD1.
On the other hand, in the peripheral circuit region PPR, a peripheral circuit for driving a nonvolatile memory (MONOS flash memory) is formed and n-channel MISFETs (Metal Insulator Semiconductor Field Effect Transistors) or the like are formed.
On the left and right sides of each of the MISFETs in the peripheral circuit region PPR, an isolation insulating film not shown is formed to provide electrical insulation between the plurality of MISFETs. Each of the MISFETs has the source region MS and the drain region MD which are formed in the main surface S1 of the semiconductor substrate SUB to be spaced apart from each other and further has the gate insulating film GI formed over the main surface S1 of the semiconductor substrate SUB, a gate electrode GE, and the sidewall insulating films SW. The gate electrode GE is formed over the main surface S1 of the semiconductor substrate SUB interposed between the source region MS and the drain region MD with the gate insulating film GI being interposed therebetween.
The source region MS and the drain region MD are impurity diffusion regions each formed in the p-type well region PW2 of the semiconductor substrate SUB and containing an impurity of the first conductivity type, i.e., n-type. The source region MS includes the lower-concentration source region MS1 and the higher-concentration source region MS2. The drain region MD includes the lower-concentration drain region MD1 and the higher-concentration drain region MD2.
The lower-concentration source region MS1 and the lower-concentration drain region MD1 are formed generally immediately under the sidewall insulating films SW. The higher-concentration source region MS2 and the higher-concentration drain region MD2 are formed externally of the sidewall insulating films SW so as to be respectively adjacent to the lower-concentration source region MS1 and the lower-concentration drain region MD1.
In each of the MISFETs in the peripheral circuit also, in the same manner as in the memory cells, the higher-concentration source region M2 includes the upper source region MS2a and the lower source region MS2b, which are arranged basically similarly to the upper source region MS2a and the like in the memory cells. In each of the MISFETs in the peripheral circuit also, in the same manner as in the memory cells, the higher-concentration drain region MD2 includes the upper drain region MD2a and the lower drain region MD2, which are arranged basically similarly to the upper drain region MD2a and the like in the memory cells.
Referring to
The first insulating film O1 preferably includes, e.g., a silicon oxide film. The second insulating film NI preferably includes, e.g., a silicon nitride film. The third insulating film ON2 preferably includes, e.g., a silicon oxide film, or more preferably is a so-called silicon oxynitride film as a silicon oxide film containing nitrogen.
Referring to
It is considered that, in
Note that, similarly to the source region MS, the drain region MD in the present embodiment also has a configuration including two regions having different impurity concentrations which are the lower-concentration drain region MD1 (first drain region) and the higher-concentration drain region MD2 (second drain region) having the first-conductivity-type (n-type) impurity concentration higher than that of the lower-concentration drain region MD1 in the lateral direction along the main surface S1 of the semiconductor substrate SUB, though not shown in such graphs as in
In the vertical direction crossing the main surface S1 of the drain region MD also, similarly to the source region MS, the drain region MD has a configuration including two regions having different impurity concentrations which are the lower drain region MD2b and the upper drain region MD2a having the first-conductivity-type (n-type) impurity concentration higher than that of the lower drain region MD2b. That is, it is considered that the upper drain region MD2a formed externally of the control gate electrode CG is the foregoing second drain region (region having the impurity concentration higher than that of the first drain region) and the lower drain region MD2b located so as to come in contact with the lower surface of the upper drain region MD2a is the foregoing first drain region (region having the impurity concentration lower than that of the second drain region). Due to such consideration, it can be said that, in the foregoing vertical direction of the drain region also, the second drain region has the n-type impurity concentration higher than that of the first drain region.
Next, referring to
Referring to
In the memory cell region MCR where the memory cells are to be formed eventually, over the p-type well region PW1, an insulating film made of a silicon oxide film is formed by a typical thermal oxidation method. Then, a thin film of polysilicon containing an n-type impurity (e.g., arsenic or phosphorus) is formed to a thickness of not less than 100 nm and not more than 300 nm by a typical CVD (Chemical Vapor Deposition) method so as to cover the upper surface of the insulating film. Then, by a typical photoengraving technique and etching, the foregoing thin film of polysilicon and the insulating film immediately thereunder are patterned to form the control gate electrodes CG and the gate insulating films GI immediately thereunder.
Note that, here, in the case of introducing an n-type impurity into the thin film of polysilicon to be deposited, when, e.g., the thin film CG of polysilicon which is a semiconductor film intended to serve as the control gate electrodes CG is formed, the first-conductivity-type (n-type) impurity is ion-implanted in the thin film. However, by causing a gas for deposition to include a doping gas (gas for adding the n-type impurity), the thin film of polysilicon containing the n-type impurity can be formed. It may also be possible that, during the formation of the thin film, a thin film of amorphous silicon is deposited first and then subjected to heat treatment to be crystallized. That is, here, using an ion implantation technique or a method other than the ion implantation technique, when the thin film CG of polysilicon which is the semiconductor film intended to serve as the control gate electrodes CG is formed, the first-conductivity-type (n-type) impurity can be introduced into the thin film.
In the peripheral circuit region PPR where the MISFETs each as the peripheral circuit are to be formed eventually also, in the same manner as in the memory cell region MCR, over the p-type well region PW2, the insulating film GI and the thin film CG of polysilicon are formed, but need not necessarily be patterned herein.
Next, using the control gate electrodes CG in the memory cell region MCR as a mask, an impurity region MV is formed in the main surface of the semiconductor substrate SUB except for the portions thereof located immediately under the control gate electrodes CG in accordance with a self-alignment technique using a typical ion implantation technique. Here, the impurity region MV having a relatively low impurity concentration is preferably formed through the implantation of an n-type impurity. The impurity region MV is formed so as to adjust threshold voltages/currents in the regions located immediately under the memory gate electrodes MG formed later. However, since the impurity region MV need not necessarily be formed, the illustration of the impurity region MV is omitted in each of the subsequent drawings.
Referring to
In the peripheral circuit region PPR, the foregoing first insulating film O1, second insulating film NI, and dummy insulating film D2 are formed so as to cover the upper surface of the thin film CG of polysilicon.
Note that the foregoing first insulating film O1 is preferably formed to have a thickness of not less than 3 nm and not more than 6 nm, the second insulating film NI is preferably formed to have a thickness of not less than 5 nm and not more than 10 nm, and the dummy insulating film D2 is preferably formed to have a thickness of not less than 4 nm and not more than 7 nm.
Referring to
Referring to
With reference to
The n-type impurity in the lower-concentration source region MS1 formed herein preferably has a concentration approximately equal to that of the n-type impurity implanted to form the impurity region MV. The lower-concentration source region MS1 also preferably has a junction depth approximately equal to that of the impurity region MV.
Referring to
Using the dummy-source-side sidewall insulating films DSW which are the dummy sidewall insulating films on the side where the source region MS is to be formed eventually as a mask, an n-type impurity is ion-implanted again. Note that, at this time, at the same position as in the step of
Specifically, the photoresist PHR is formed into a pattern using a typical photoengraving technique so as to expose the region where the source region is to be formed. Then, into the main surface of the semiconductor substrate SUB not covered with the pattern of the photoresist PHR, an n-type impurity is ion-implanted to form the higher-concentration source region MS2.
The n-type impurity ion-implanted herein has an impurity concentration higher than that of the n-type impurity ion-implanted to form the lower-concentration source region MS1 mentioned above and a junction depth deeper than that thereof. Accordingly, in the upper region (close to the main surface S1) of the higher-concentration source region MS2, the upper source region MS2a is formed in the main surface S1 such that the higher-concentration source region MS2 overlaps the lower-concentration source region MS1 and the lower source region MS2b is formed so as to come in contact with the lower surface of the upper source region MS2a. Thus, the higher-concentration source region MS2 which is a combination of the source regions MS2a and MS2b is formed.
When viewed in the vertical direction, the lower source region MS2b as the first source region and the upper source region MS2a as the second source region in contact with the upper surface thereof are each formed using the dummy-source-side sidewall insulating films DSW as a mask. The upper source region MS2a as the second source region has an n-type impurity concentration higher than that of the lower source region MS2b as the first source region since the n-type impurity concentration of the originally existing lower-concentration source region MS1 is added to the concentration of the n-type impurity implanted in the step of
When viewed in the lateral direction, the regions (regions close to the dummy gate electrodes DMG) in the both end portions of the lower-concentration source region MS1 in which the impurity is not additionally implanted in the step of
Thus, the source region MS is formed which includes the lower-concentration source regions MS1 and the higher-concentration source region MS2 (including the upper source region MS2a and the lower source region MS2b).
Note that the lower-concentration source regions MS1 formed using the dummy gate electrodes DMG as a mask form only a part of the source region. In forming the higher-concentration source region MS2 as the other region forming the source region, the dummy gate electrodes DMG need not necessarily be used. However, it is considered here that, as long as at least a part of the source region, such as the foregoing regions MS1, is formed using the dummy gate electrodes DMG as a mask, requirements on the configuration (source region is formed using the dummy gate electrodes DMG as a mask) in the embodiment are met.
Referring to
Referring to
The third insulating film ON2 includes the silicon oxide film and is formed by, e.g., a typical CVD method. However, the third insulating film ON2 is more preferably formed as a silicon oxynitride film containing nitrogen. The third insulating film ON2 is preferably formed by so-called ISSG (In Situ Steam Generation) oxidation to have a thickness of, e.g., not less than 4 nm and not more than 7 nm. Thus, the laminate structure ONI intended to serve as the memory gate insulating film is formed which has a configuration in which the first insulating film O1, the second insulating film NI, and the third insulating film ON2 are stacked.
Referring again to
Referring to
In the case of using an ion implantation technique when the foregoing p-type impurity is introduced, a conductive impurity is implanted in a direction shown by the arrow in
Referring to
Referring to
Referring to
In the peripheral circuit region PPR, by typical etching using the pattern of the photoresist PHR, the thin film CG is formed as the gate electrode GE and the insulating film GI located immediately thereunder is formed as the gate insulating film GI. The thin film CG and the insulating film GI in the region other than that described above are entirely removed and the insulating film ONI over the thin film CG is also removed.
Referring to
In the process, in accordance with a self-alignment technique using the control gate electrodes CG as a mask, the impurity region MV becomes the drain regions MD formed in the main surface S1. Note that the ion implantation performed herein may also be performed in a direction oblique to the main surface S1 of the semiconductor substrate SUB.
Note that, in the peripheral circuit region PPR, an n-type impurity is implanted into the main surface S1 of the semiconductor substrate SUB on both sides of the gate electrode GE using a typical ion implantation technique. By the self-alignment technique using the gate electrode GE as a mask, the source region MS1 and the drain region MD1 are formed at the positions shown in the drawing.
Referring to
The sidewall insulating films SW have shapes which are thinner with distance from the electrodes CG and MG. Here, for the sake of convenience, the sidewall insulating films SW formed so as to be adjacent to the control gate electrodes CG (on the side where the drain regions MD are to be formed eventually) are referred to as the drain-side sidewall insulating films and the sidewall insulating films SW formed to be adjacent to the memory gate electrodes MG (on the side where the source region MS is located) are referred to as the source-side sidewall insulating films.
Next, in the memory cell region MCR, the photoresist PHR is formed into a pattern again at the same position as in the step of
At this time, in accordance with a self-alignment technique using the drain-side sidewall insulating films SW as a mask, the impurity is additionally implanted into the region of the main surface S1 located externally of the drain regions MD formed in the step of
Note that, here, an n-type impurity is implanted so as to form an impurity region having an impurity concentration higher than that of the impurity region formed in the step of
That is, when viewed in a lateral direction, the regions in the both end portions (regions close to the control gate electrodes CG) of the impurity region MV into which the impurity is not additionally implanted in the step of
When viewed in a longitudinal direction, in the step of
Each of the upper drain regions MD2a as the second drain region has an n-type impurity concentration higher than that of each of the lower drain regions MD2b as the first drain region since the n-type impurity concentration of the originally existing impurity region MV is added to the concentration of the n-type impurity implanted in the step of
Thus, the drain regions MD are formed which include the lower-concentration drain regions MD1 and the higher-concentration drain regions MD2 (including the upper drain regions MD2a and the lower drain regions MD2b).
In the peripheral circuit region PPR, in the same manner as in the memory cell region MCR, the higher-concentration source region MS2 and the higher-concentration drain region MD2 are formed in accordance with a self-alignment technique using a typical ion implantation technique using the sidewall insulating films SW formed so as to cover the side surfaces of the gate electrode GE as a mask. Of the higher-concentration source region MS2 and the higher-concentration drain region MD2, the regions overlapping the source region MS1 and the drain region MD1 each formed in the step of
After the foregoing individual steps, the pattern of the photoresist PHR is removed by ashing or the like and generally known post-processing such as the formation of interlayer insulating films is performed, whereby the semiconductor device having the MONOS flash memory is formed.
Next, a description will be given of the function/effect of the embodiment. First, referring to the configuration of a comparative example of
Referring to
During a data write operation to the MONOS flash memory of the comparative example, a voltage +Vcg1A is applied to the control gate electrode CG, a voltage +Vmg1A is applied to the n-type memory gate electrode NMG, a voltage +Vd1A is applied to the drain region MD, and a voltage +Vs1A is applied to the source region MS. Each of the voltages has a positive value and +Vs1A is higher than +Vd1A.
At this time, the electron supplied from the drain region MD into the semiconductor substrate SUB (shown by the encircled “−”) passes through the first insulating film O1 immediately under the n-type memory gate electrode NMG from the semiconductor substrate SUB side to be injected into the second insulating film NI. The electron injected into the second insulating film NI is trapped by a trap level in the second insulating film NI. As a result, the threshold voltage of the storage transistor increases.
Referring to
Thus, in such an n-type MONOS flash memory including the n-type memory gate electrode NMG as that of the comparative example, during each of a data write operation and a data erase operation, an electron or a hole passes through the first insulating film O1 under the memory gate electrode NMG. As a result, when the number of times a rewrite operation is performed increases, the degradation of the first insulating film O1 may become obvious to possibly affect a rewrite property and reliability (the function of the second insulating film NI to hold charges).
Also in the n-type MONOS flash memory of the comparative example, when data is to be written, a positive voltage is applied to the n-type memory gate electrode NMG while, when data is to be erased, a negative voltage is applied to the n-type memory gate electrode NMG. Accordingly, two types of power supply circuits are needed as peripheral circuits to increase the area occupied by the power supply circuits in the entire semiconductor device. This causes the need to accordingly reduce the area occupied by a flash module including the flash memory and the like or reduce the area occupied by the elements forming other peripheral circuits.
Referring to
When data is written to the MONOS flash memory of the embodiment, in the same manner as in the MONOS flash memory of the comparative example, the voltage +Vcg1A is applied to the control gate electrode CG, the voltage +Vmg1A is applied to the p-type memory gate electrode PMG, the voltage +Vd1A is applied to the drain region MD, and the voltage +Vs1A is applied to the source region MS. These values are the same as the individual values shown in
Referring to
At this time, the hole generated from the p-type memory gate electrode MG passes through the third insulating film immediately thereunder to be injected into the second insulating film NI. Thus, during a data erase operation, each of the electron and the hole is injected into the second insulating film NI without passing through the first insulating film O1. Accordingly, in the embodiment, it is possible to reduce the number of times the electron or hole passes through the first insulating film O1 compared to that in the foregoing comparative example and suppress the degradation of the first insulating film O1. This can improve the rewrite property (the number of times a rewrite operation can be performed) and reliability.
Also, in the embodiment, during each of a data write operation and a data erase operation, a positive voltage (+Vmg1A or +Vmg2B) is applied to the p-type memory gate electrode PMG. Accordingly, it is possible to eliminate a power supply circuit for applying a negative voltage from the peripheral circuits and save a space in the semiconductor device such as the area occupied by each of the elements.
As shown next in
Referring to
Referring to
The third insulating film ON2 as the silicon oxynitride film mentioned above is formed by so-called ISSG oxidation which is a type of a CVD method. The third insulating film ON2 thus formed has insulation performance inferior to that of a silicon oxide film (not containing nitrogen) formed by, e.g., a thermal oxidation method, but can be formed at lower cost than that of the thermal oxide film. Unlike, e.g., the third insulating film O2 in the comparative example, the third insulating film ON2 in the embodiment is not required to have a high insulating property comparable to that of the third insulating film O2 in the comparative example since the hole passes therethrough. Therefore, by forming the silicon oxynitride film containing nitrogen by the foregoing method, it is possible to form a memory gate insulating film which satisfies an operational need at low cost.
Also in the embodiment, the source region includes the lower-concentration source regions MS1 each as the first source region and the higher-concentration source region MS2 as the second source region having an n-type impurity concentration higher than that of each of the lower-concentration source regions MS1. Accordingly, compared to the case where only the lower-concentration source region MS1 is provided as the source region, the electric resistance of the whole source region can be reduced and, consequently, the source-drain electric resistance can also be reduced. In addition, since the higher-concentration source region MS2 is formed in a region located between the source region and the drain region and relatively close to the main surface S1 through which an electron or the like laterally passes, the electron or the like is allowed to more easily pass therethrough. Thus, the drive capability of the MONOS flash memory can be enhanced.
The lower-concentration source regions MS1 each as the first source region are located immediately under the source-side sidewall insulating films SW and the higher-concentration source region MS2 as the second source region is located externally of the source-side sidewall insulating films SW. Accordingly, the source region MS is formed such that, in the lateral direction along the main surface of the semiconductor substrate SUB, the impurity concentration is higher and the electric resistance is lower in the middle portion of the source region MS than in the both end portions thereof. This allows the effect of reducing the electric field in the source region to be obtained. In addition, the electric resistance in such a region as the source region and a region between the source region and the drain region can be reduced to allow the drive capability of the MONOS flash memory to be enhanced.
In the method of manufacturing the semiconductor device of the present embodiment, after the source region MS is formed using the dummy gate electrodes DMG and the dummy gate electrodes DMG are removed, the authentic memory gate electrodes MG are formed and the drain regions MD are formed in a state where the memory gate electrodes MG are covered. As a result, it is possible to form the source region MS having a high impurity concentration without impairing the high p-type impurity concentration of each of the memory gate electrodes MG.
In the present embodiment, after the lower-concentration source regions MS1 each as the first source region is formed using the dummy gate electrodes DMG as a mask, the dummy-source-side sidewall insulating films DSW are formed on the side of the dummy gate electrodes DMG where the source region is located so as to be adjacent to the dummy gate electrodes DMG. Then, using the dummy-source-side sidewall insulating films DSW as a mask, the higher-concentration source region MS2 as the second source region is formed. Accordingly, the source region MS is formed such that, in the lateral direction along the main surface of the semiconductor substrate SUB, the impurity concentration is higher and the electric resistance is lower in the middle portion of the source region MS than in the both end portions thereof. This allows the effect of reducing the electric field in the source region to be obtained.
Note that, in the foregoing description, when the higher-concentration source region MS2 having a lateral width smaller than that of each of the lower-concentration source regions MS1 is formed, the dummy-source-side sidewall insulating films DSW are formed as a mask for a self-alignment technique. However, if ion implantation is performed obliquely to implant ions into desired regions as in the step of, e.g.,
Also in the embodiment, each of the drain regions includes the lower-concentration drain region MD1 as the first drain region and the higher-concentration drain region MD2 as the second drain region having an n-type impurity concentration higher than that of the lower-concentration drain region MD1. Accordingly, compared to the case where only the lower-concentration drain region MD1 is provided as the drain region, the electric resistance of the whole drain region can be reduced and, consequently, the source-drain electric resistance can also be reduced. In addition, since the higher-concentration drain region MD2 is formed in the region located between the source region and the drain region and relatively close to the main surface S1 through which an electron or the like laterally passes, the electron or the like is allowed to more easily pass therethrough. Thus, the drive capability of the MONOS flash memory can be enhanced.
The lower-concentration drain region MD1 as the first drain region is located immediately under the drain-side sidewall insulating film SW and the higher-concentration drain region MD2 as the second drain region is located externally of the drain-side sidewall insulating film SW. Accordingly, the drain region MD is formed such that, in the lateral direction along the main surface of the semiconductor substrate SUB, the impurity concentration is higher and the electric resistance is lower in the middle portion of the drain region MD than in the both end portions thereof. This allows the effect of reducing the electric field in the drain region to be obtained.
In a vertical direction crossing the main surface of the semiconductor substrate SUB also, the source region MS includes the lower source region MS2b as the first source region and the upper source region MS2a as the second source region which is in contact with the upper surface of the lower source region MS2b and has an n-type impurity concentration higher than that of the lower source region MS2b. Each of the drain regions MD also includes the lower drain region MD2b as the first drain region and the upper drain region MD2b as the second drain region which is in contact with the upper surface of the lower drain region MD2b and has an n-type impurity concentration higher than that of the lower drain region MD2b. Therefore, in the vertical direction also, the impurity concentration can be increased to allow a reduction in the electric resistance of the whole source region and allow an increase in the drive capability of the MONOS flash memory.
The lower source region MS2b and the upper source region MS2a as the first source region and the second source region in the vertical direction are formed using the dummy-source-side sidewall insulating films DSW as a mask. On the other hand, the lower-concentration source regions MS1 each as the third source region are formed using the dummy gate electrodes DMG as a mask. Therefore, in the vertical direction also, the impurity concentration can be increased to allow a reduction in the electric resistance of the entire source region and allow an increase in the drive capability of the MONOS flash memory.
It is difficult to form the source region including the two impurity regions having different concentrations described above after, e.g., the memory gate electrodes MG each having a p-type impurity are formed. A description will be given below thereof.
For example, when the source region on the side where the memory gate electrodes MG are located is formed after the formation of the p-type memory gates MG such that the source region has a concentration gradient, a higher-concentration n-type impurity region for the source region is introduced using a typical ion implantation technique. At this time, if ion implantation is performed without forming the photoresist PHR or the like and covering the p-type memory gate electrodes MG therewith, an n-type impurity is implanted in a large amount in each of the p-type memory gate electrodes MG to result in the problem of a reduction in the p-type impurity concentration of the memory gate electrode MG. Moreover, since the memory gate electrode MG is extremely thin, the impurity may be unintentionally implanted to pass through the memory gate electrodes MG during the ion implantation and reach the interior of the semiconductor substrate SUB.
However, when the n-type impurity for the source region is implanted into the regions adjacent to (located externally of) the memory gate electrodes MG, even though it is attempted to form the photoresist PHR into a pattern so as to cover the memory gate electrodes MG therewith, it is difficult to form the photoresist PHR into a pattern such that the end portions thereof substantially coincide with the end portions of the memory gate electrodes MG. This is because the uppermost surface of each of the memory gate electrodes MG is inclined such that the thickness thereof is smaller in the outer portion thereof than in the inner portion thereof.
Accordingly, when the photoresist PHR is formed into a pattern covering the upper surfaces of the memory gate electrodes MG, the photoresist PHR needs to be formed into the pattern such that the end portions thereof are located at positions laterally away from the outer end portions of the memory gate electrodes MG (the end portions thereof are not located immediately over the memory gate electrodes MG). In this case, it is difficult to form an impurity region by implantation at a position externally adjacent to each of the memory gate electrodes MG using such a pattern of the photoresist PHR.
For each of the reasons given above, in the embodiment, the dummy gate electrodes DMG are formed first each as a dummy memory gate electrode and, in accordance with a self-alignment technique using the dummy gate electrodes DMG, the source region MS (e.g., the source region MS2 as at least a part thereof) is formed. After the formation of the source region MS, the dummy gate electrodes DMG are removed and the memory gate electrodes MG are formed. In a state where the memory gate electrodes MG (also the region where the source region MS is formed) are covered with the pattern of the photoresist PHR, the drain region MD is formed.
Consequently, when the source region MS is formed, the dummy gate electrodes DMG are used and the memory gate electrodes have not been formed yet. Therefore, it is possible to form the higher-concentration source region MS without being concerned about the implantation of an n-type impurity into the p-type memory gate electrodes. When the drain regions MD are formed, the memory gate electrodes MG are formed. However, processing is performed in a state where the memory gate electrodes MG are covered with the pattern of the photoresist PHR (such that the source region MS is included therein, i.e., the end portions of the photoresist PHR do not coincide with the end portions of the memory gate electrodes MG). This can reduce the possibility of impurity implantation into the memory gate electrodes MG.
The manufacturing method in which the source region MS is formed using the dummy gate electrodes DMG (before the formation of the memory gate electrodes MG) is useful as a method for forming the MONOS flash memory of the embodiment.
In the description given above, the memory gate electrodes MG are each formed as a thin film (semiconductor layer) of polysilicon containing a p-type impurity, but the memory gate electrodes MG are not limited thereto. The same effect can be achieved with a flash memory having the memory gate electrodes MG each formed as a thin film of polysilicon containing an n-type impurity or as a thin film of polysilicon containing neither an n-type impurity nor a p-type impurity.
While the invention achieved by the present inventors has been specifically described heretofore based on the embodiments thereof, the present invention is not limited to the foregoing embodiments. It will be appreciated that various changes and modifications can be made in the invention within the scope not departing from the gist thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2013-141637 | Jul 2013 | JP | national |
