Patent Application
20050151259
The present application claims priority from Japanese Patent Application No. 2004-004509, filed on Jan. 9, 2004, the content of which is hereby incorporated by reference into this application.
The present invention relates in general to techniques to be performed on semiconductor devices and to methods of manufacture thereof. More specifically, it relates to techniques which give better control over etching of dielectric films arranged over a semiconductor substrate.
Japanese Unexamined Patent Publication No. 2001-332510 (patent document 1) discloses a technique for reducing damage and erosion inflicted upon a semiconductor substrate by reducing overetching of the semiconductor substrate even in the case of a contact hole having a large aspect ratio. Such a contact hole typically is formed by dry-etching a dielectric film that is formed over the semiconductor substrate, to thereby expose the semiconductor substrate.
In the manufacture of a semiconductor device according to this technique, a thin Si-rich dielectric film and a thick interlayer dielectric film comprising boron-doped phospho-silicate glass (BPSG) are sequentially formed on a semiconductor substrate bearing a diffusion layer, a photoresist film is formed as a mask, and the interlayer dielectric film and the Si-rich dielectric film are dry-etched using the photoresist film as a mask. A contact hole extending to the diffusion layer is thus formed. In this procedure, etching is once stopped at the surface of the Si-rich dielectric film by controlling the composition of the etching gas. The Si-rich dielectric film is then etched using another etching gas having a different composition.
The Si-rich dielectric film is a dielectric film having a silicon content (SiO, wherein 1≦x≦2) larger than that of a regular silicon oxide film, and it is prepared, for example, by plasma chemical vapor deposition (plasma CVD) using a 2:1 gaseous mixture of SiH4 and O2.
Japanese Unexamined Patent Publication No. 2001-85523 (patent document 2) discloses a technique for reducing extra process steps in the formation of a dual damascene structure on a semiconductor substrate.
The process for forming a dual damascene structure as disclosed in the patent document 2 comprises the steps of (a) forming a stacked layer comprising a first dielectric layer, a second dielectric layer and an etch-stop layer, (b) forming a first opening in one of the fist dielectric layer and the second dielectric layer, and (c) forming a second opening in at least two of the first dielectric layer, the second dielectric layer and the etch-stop layer, which second opening is smaller than the first opening and is formed at least at part of the base.
The first dielectric layer and the second dielectric layer each comprise a silicon oxide dielectric film, such as a boron-doped phospho-silicate glass (BPSG) film and a spin-on-glass (SOG) film. The etch-stop layer comprises a material exhibiting an etching resistance greater than that of the second dielectric layer with respect to selective etching. Examples of the material are Ta (tantalum), TaN (tantalum nitride), silicon nitride, silicon-rich oxide and multi-layer silicon oxide dielectrics.
Japanese Unexamined Patent Publication No. 2000-260871 (patent document 3) discloses a technique for solving problems in the formation of contact holes having different depths over a semiconductor substrate.
The method of manufacturing a semiconductor device as disclosed in patent document 3 comprises the steps of forming a first dielectric film over an underlayer circuit pattern having steps and being arranged on a semiconductor substrate, forming a second dielectric film on the first dielectric film, planarizing a surface of the second dielectric film, and forming plural contact holes having different depths and extending through the first and second dielectric films to the underlayer circuit pattern. The first dielectric film and the second dielectric film have different etching rates under the same etching condition. The first dielectric film serves as a stopper film against chemical and mechanical polishing (CMP) for planarizing the surface of the second dielectric film.
In semiconductor memory devices, such as flash memories and DRAMs, a failed memory cell is switched to a redundant memory cell in order to avoid or remedy a defect. The switching is carried out by forming a fuse in part of a circuit and blowing the fuse, typically by the action of laser light.
Such a fuse is generally formed simultaneously with the formation of wiring arranged over a memory element on a semiconductor substrate. Upon completion of a wafer process, the top of a wiring layer, such as the fuse, is covered by a dielectric film. After intensive investigations, however, the present inventors have found for the first time that the following problems are inherent in the conventional techniques.
Specifically, if the dielectric film covering the fuse is excessively thick, the fuse cannot be blown due to insufficient energy, even when laser light is applied to the fuse from above. In general, therefore, to solve this problem, the surface protective film (dielectric film) lying over the fuse is also etched to reduce the thickness of the dielectric film lying over the fuse in a final step of the wafer process, in which the surface protective film (dielectric film) covering an uppermost-level wiring is etched to expose part of the uppermost-level of wiring to form a bonding pad. In contrast, an excessively thin dielectric film lying over the fuse may invite corrosion of the fuse, since such a thin dielectric film may allow water and other contaminants to penetrate the dielectric film lying over the fuse and reach the fuse. Thus, the control of the thickness of the dielectric film covering the fuse is a key factor affecting the yield and reliability of the resulting semiconductor device.
In the formation of a through hole for connecting upper-level and lower-level wirings by etching an interlayer dielectric film, misregistration in relative positions of the lower wiring and the through hole may occur due to misregistration of a photomask. This misregistration problem is becoming increasingly serious, since the wiring dimensions are being reduced more and more with an increase in the packing densities of semiconductor devices.
More specifically, a dielectric film covering a wiring lying under the lower-level wiring, the semiconductor element and the semiconductor substrate also will be overetched if the interlayer dielectric film is etched while the lower-level wiring and the through hole stay relatively misregistered. This may cause a shorting of a metal plug embedded in the through hole with the semiconductor element and/or the semiconductor substrate.
Accordingly, an object of the present invention is to provide a technique for optimizing the thickness of a dielectric film lying over a fuse by providing better control over etching of the dielectric film arranged over a semiconductor substrate.
Another object of the present invention is to provide a technique for preventing overetching of a dielectric film lying under a lower-level wiring even when a through hole for connecting upper-level and lower-level wirings is formed by etching an interlayer dielectric film while the lower-level wiring and the through hole stay relatively misregistered.
The present invention typically provides the following features and advantages.
The present invention provides, in a first aspect, a semiconductor device including a semiconductor substrate and multi-level wirings arranged over the semiconductor substrate with the interposition of an interlayer dielectric film, in which a first dielectric film comprising at least a silicon oxide film and a silicon-rich oxide film is arranged over an uppermost-level wiring, a bonding pad is arranged in place of part of the first dielectric film, and a fuse is arranged in a wiring layer lying under the uppermost level of wiring.
The present invention provides, in a second aspect, a semiconductor device including a semiconductor substrate, a first dielectric film arranged over the semiconductor substrate, a silicon-rich oxide film arranged over the semiconductor substrate via the first dielectric film, a first wiring arranged over the silicon-rich oxide film, an interlayer dielectric film arranged over the first wiring and comprising a silicon oxide film, and a second wiring arranged over the interlayer dielectric film, in which the first wiring and the second wiring are electrically connected with each other via a through hole arranged in the interlayer dielectric film.
The present invention further provides, in a third aspect, a method of manufacturing a semiconductor device, including the steps of:
In addition and advantageously, the present invention provides, in a fourth aspect, a method of manufacturing a semiconductor device, including the steps of:
Typical advantages of the present invention are as follows.
The present invention can give better control over the etching of dielectric films arranged over a semiconductor substrate. In addition, the present invention can improve the yield and reliability of semiconductor devices.
The present invention will be described in further detail with reference to several embodiments, as illustrated in the attached drawings. In the drawings, the same members are indicated by the same reference numerals, and a repetitive description thereof will be omitted.
A method of manufacturing a semiconductor device will be sequentially described, step by step with reference to FIGS. 1 to 11. In the method, an opening is formed in a dielectric film arranged over a fuse. The left-hand parts in individual sectional views each represent a fuse-forming region and the right-hand parts thereof represent a bonding pad (hereinafter referred to as a “pad”) forming region.
With reference to
The memory cells Qs, serving as the flash memory, each comprise, for example, an n-type semiconductor region 8 that is arranged in the p-type well 3, and three gates, i.e., a floating gate 7, a control gate 10 and a selector gate 11. The floating gate 7 is arranged between two adjacent selector gates 11. The floating gate 7 and the p-type well 3 are isolated from each other by the action of a dielectric film, such as a first gate oxide film 4a. Likewise, the floating gate 7 and the selector gate 11 are isolated from each other by the action of an interlayer dielectric film, such as a silicon oxide film 9, and the floating gate 7 and the control gate 10 are isolated from each other by the action of a dielectric film, such as a second gate oxide film 4b. The control gate 10 extends in a longitudinal direction (line-writing direction; lateral direction in the figure) and constitutes a word line. The selector gate 11 extends column-wise, i.e., in a transverse direction perpendicular to the word line. The n-type semiconductor region 8 extends column-wise, i.e., in a transverse direction perpendicular to the word line and serves as a local bit line.
The n-channel MISFET Qn constituting the peripheral circuit of the flash memory comprises a gate oxide film 4, an n-type semiconductor region 6 and a gate electrode 5. The peripheral circuit comprises the n-channel MISFET Qn and a p-channel MISFET (not shown).
The surface of the silicon oxide film 13 covering the memory cells Qs and the n-channel MISFET Qn is planarized by chemical mechanical polishing (CMP). The first-level wiring 14 is electrically connected to the n-channel MISFET Qn, and the first-level wiring 15 is electrically connected to the memory cells Qs. The first-level wirings 14 and 15 each comprise a metal film or metal nitride film, such as a tungsten (W) film, titanium (Ti) film, titanium nitride (TiN) film, an aluminum alloy film, or a multilayer film comprising a Ti film and a TiN film.
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The SRO film 28 herein may be formed, for example, by plasma CVD using a silane gas. The plasma CVD apparatus used for this purpose may be, for example, a parallel plate reactor. As a treatment gas, for example, a gaseous mixture containing a silane gas, such as monosilane (SiH4), oxygen gas (O2 gas) and a diluent gas, such as argon (Ar) gas, may be used. Another silane gas, such as disilane (Si2H6) gas or tetraethoxysilane (TEOS) gas, can be used instead of the monosilane gas. An oxygen-containing gas, such as nitrous oxide (N2O) gas or ozone (O3) gas, can be used instead of the oxygen gas. A time period between t0 and t1 is an idling time; a time period between t2 and t5 represents a film-forming time of the SRO film 28; and a time period between t5 and t8 represents a film-forming time of the silicon oxide film 29. Heating of the wafer 1W and supply of argon and oxygen to a reaction chamber start at the time t1. The supply of monosilane starts at the time t2. For forming the SRO film 28 as a silicon-rich film, the flow rate of monosilane in the film-forming of the SRO film 28 is set to be greater than that of the silicon oxide film 29. The flow rates of the monosilane gas, oxygen gas and argon gas in film-formation of the SRO film 28 are set, for example, at about 77 sccm (i.e., 77 cm3/min), about 97 sccm and about 90 sccm, respectively. The flow rates of the monosilane gas, oxygen gas and argon gas in film-formation of the silicon oxide film 29 are set, for example, at about 70 sccm, about 90 sccm, and about 90 sccm, respectively.
When the underlying SRO film 28 is formed as a silicon oxide film that is richer in silicon than the overlying silicon oxide film 29, the SRO film 28 and the silicon oxide film 29 can be formed in a reaction chamber of one plasma CVD apparatus so that the former has a silicon content higher than that of the latter. This shortens the film-forming time period. In addition, the SRO film 28 and the silicon oxide film 29 can be formed continuously and stably with less contamination by foreign matter. This improves the reliability of the film-forming process.
When such a thick dielectric film, comprising the silicon oxide film 29 and the silicon nitride film 30, is formed over the SRO film 28, the thickness of the dielectric film varies between a region over the third-level wiring 27 and a region under which the third-level wiring 27 is not formed, such as a region over the fuse 21. Specifically, the dielectric film lying over the fuse 21 comprises at least a silicon oxide film and an SRO film. In addition, the SRO film is formed as the lowermost layer of the dielectric film lying over the fuse 21 and can thereby serve as an etching stopper during etching of the silicon oxide film.
With reference to
The opening 31 is formed by dry-etching the dielectric film comprising the silicon oxide film 29 and the silicon nitride film 30 in a region over the fuse 21 using a photoresist film (not shown) as a mask. In this procedure, the dielectric film comprising the silicon oxide film 29 and the silicon nitride film 30 in a region over the third-level wiring 27 is also dry etched in order to expose part of the third-level wiring 27 to thereby form the pad.
The SRO film 28 serves as an etching stopper during dry etching of the silicon oxide film 29, subsequent to etching of the silicon nitride film 30, since the silicon oxide film 29 and the underlying SRO film 28 have different etching rates. Specifically, the etching is stopped at the surface of the SRO film 28 in regions over the third-level wiring 27 and over the fuse 21, even if the thickness of the dielectric film comprising the silicon oxide film 29 and the silicon nitride film 30 varies between regions over the third-level wiring 27 and over the fuse 21.
Next, as seen with reference to
According to the present embodiment (First Embodiment), the SRO film 28, serving as an etch stopper, is arranged under the silicon oxide film 29. Then, the thick dielectric film comprising the silicon oxide film 29 and the silicon nitride film 30 is formed over the third-level wiring 27, serving as the uppermost-level wiring, and the dielectric film is dry-etched to thereby form the opening 31 and the pad 27p. This gives better control over the etching amount of the silicon oxide film 29 even if the dielectric film comprising the silicon oxide film 29 and the silicon nitride film 30 has a varying thickness between a region over the third-level wiring 27 and a region over the fuse 21. The fuse herein serves as the second-level wiring. Thus, overetching of the underlying dielectric films can be prevented upon formation of the opening 31, and the thickness of the dielectric film lying over the fuse 21 can be optimized. This improves the yield and the reliability of semiconductor devices such as flash memories.
The SRO film 28 is arranged under the silicon oxide film 29 in the present embodiment, but it may be arranged adjacent to the silicon oxide film 29, i.e., between the silicon oxide film 29 and the silicon nitride film 30. Alternatively, the SRO film 28 may be arranged inside the silicon oxide film 29 to constitute a multilayer structure comprising the silicon oxide film 29, the SRO film 28 and the silicon oxide film 29 in this order. In any case, the same advantages as the case where the SRO film 28 is formed below the silicon oxide film 29 can be obtained.
Another method of manufacturing a semiconductor device will be described with reference to FIGS. 12 to 16. In this method, a through hole is formed in a dielectric film over wirings.
Initially, as seen with reference to
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The present embodiment can avoid defects caused by the relative misregistration between the wiring and a through hole and improve the yield and reliability of the semiconductor device. In addition, the wiring dimensions and, in turn, the chip area can be reduced.
Typical advantages of the present invention will be briefly described below.
Dielectric films arranged on a semiconductor substrate can be etched more precisely by using a silicon-rich oxide film as an etching stopper during etching of the silicon oxide films (dielectric films). This gives better control over the etching amount of the silicon oxide films arranged over the semiconductor substrate, which in turn optimizes the thickness of the dielectric film lying over the fuse.
The use of a silicon-rich oxide film as an etching stopper during etching of the silicon oxide film gives better control over the etching amount of the silicon oxide films arranged over the semiconductor substrate. This prevents dielectric films lying under the lower-level wiring during etching of the interlayer dielectric film to form a through hole which connects the upper-level wiring with the lower-level wiring.
In the above-mentioned embodiments, the SRO film 28 is arranged under the first-level wiring 14. It is also acceptable if the SRO film 28 and the silicon oxide films 16 and 17 are formed over the first-level wiring 14, the SRO film 28 is allowed to serve as an etching stopper during dry etching of the silicon oxide films 16 and 17, and then the SRO film 28 is dry-etched to expose the first-level wiring 14. In this case, the etching of the silicon oxide film 13 can be surely prevented by setting the thickness of the SRO film 28 in a region in contact with a side wall of the first-level wiring 14 (thickness in a direction in parallel with the principal plane of the substrate 1) greater than the maximum misregistration of the photomask.
The SRO film 28 may be arranged inside the silicon oxide film 16, between the silicon oxide film 16 and the silicon oxide film 17, or inside the silicon oxide film 17, and it is preferably arranged near to the first-level wiring 14.
In the above-mentioned embodiments, the second-level wiring 20 and the first-level wiring 14 are connected via the metal plug 19 embedded inside the through hole 18. It is also acceptable if the second-level wiring 20 is arranged over the silicon oxide film 17 and inside the through hole 18 to thereby directly connect the second-level wiring 20 and the first-level wiring 14.
Although the invention made by the present inventors has been described above in specific terms with reference to preferred embodiments thereof, the invention is not confined to the disclosed embodiments, but can be modified in various ways without deviating from its true spirit and scope.
The SRO film having a silicon content greater than a regular silicon oxide film is used as an etching stopper upon etching of the silicon oxide films. Similar advantages can also be obtained by using a dielectric film having a modified etching rate as the etching stopper. The etching rate of such a silicon oxide film can be modified by adding at least one of nitrogen, fluorine and carbon atoms to a regular silicon oxide film.
The present invention can be applied to semiconductor devices of the type which use a fuse for remedying defects by switching a failed memory cell to a redundant memory cell.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-004509 | Jan 2004 | JP | national |
