Patent Grant
12225716
The present invention relates to a semiconductor device and a manufacturing method thereof.
In order to improve the integration of dynamic random access memories to speed up the operation of elements and to meet the needs of consumers for miniaturized electronic devices, buried wordline dynamic random access memories have been developed in recent years to meet the above requirements.
According to some embodiments, the present invention provides a manufacturing method of a semiconductor device, including:
providing a semiconductor substrate having a shallow trench isolation (STI) structure and a plurality of active regions disposed in parallel;
forming a first wordline trench structure in the semiconductor substrate;
forming a first sacrificial layer at the bottom of the first wordline trench structure;
filling the first wordline trench structure located in the active regions by epitaxial growth;
forming a first insulation layer covering the top of the semiconductor substrate and the first wordline trench structure in the STI structure and sealing the first wordline trench structure;
forming a second wordline trench structure and a fin-type structure in the active regions, a depth of the second wordline trench structure being less than that of the first wordline trench structure, and a projection of the second wordline trench structure in a vertical direction completely overlapping with a projection of the first sacrificial layer in the vertical direction;
removing the first sacrificial layer to form a wordline tunnel in the semiconductor substrate connected with the first wordline trench structure; and
filling the first wordline trench structure, the second wordline trench structure and the wordline tunnel to form an buried wordline structure surrounding the fin-type structure.
According to some embodiments, the present invention further provides a semiconductor device, including:
a semiconductor substrate having a STI structure and a plurality of active regions disposed in parallel;
an buried wordline structure located in the semiconductor substrate, extending along a first direction, and crossing the STI structure and the plurality of active regions; and
a fin-type structure located in a region where the active regions intersect with the buried wordline structure, the buried wordline structure wrapping around the fin-type structure.
Details of one or more embodiments of the present application are set forth in the following accompanying drawings and descriptions. Other features and advantages of the present application become obvious with reference to the specification, the accompanying drawings, and the claims.
In order to more clearly illustrate the technical solutions in embodiments of the present application or the conventional technology, the accompanying drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. It is apparent that, the accompanying drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those of ordinary skill in the art from the provided drawings without creative efforts.
With an increase in the integration of memories, an area of an active region is often affected by process limitations of a random access memory due to its small size, which limits a control capability of a gate and a channel width, thus leading to a higher turn-on voltage, a slower turn-on speed and a lower operating current of the semiconductor device and then affecting its performance.
In order to make the above objectives, features and advantages of the present invention more comprehensible, specific implementations of the present invention are described in detail below with reference to the accompanying drawings. Many specific details are described below for full understanding of the present invention. However, the present invention may be implemented in other manners different from those described herein. It may be appreciated by those of ordinary person skilled in the art that similar improvement may be made without departing from the idea of the present invention. The present invention is thus not limited by specific embodiments disclosed below.
Referring to
In step S110, a semiconductor substrate 100 having a STI structure and a plurality of active regions AA disposed in parallel is provided, referring to
In step S120, a first wordline trench structure G1 is formed in the semiconductor substrate 100, referring to
In step S130, a first sacrificial layer 200 is formed at the bottom of the first wordline trench structure G1, referring to
In step S140, the first wordline trench structure G1 located in the active regions AA is filled by epitaxial growth, referring to
In step S150, a first insulation layer 300 covering the top of the semiconductor substrate 100 and the first wordline trench structure G1 in the STI structure and sealing the first wordline trench structure G1 is formed, referring to
In step S160, a second wordline trench structure G2 and a fin-type structure 400 are formed in the active regions AA, a depth of the second wordline trench structure G2 is less than that of the first wordline trench structure G1, and a projection of the second wordline trench structure G2 in a vertical direction completely overlaps with a projection of the first sacrificial layer 200 in the vertical direction, referring to
In step S170, the first sacrificial layer 200 is removed to form a wordline tunnel G3 in the semiconductor substrate 100 connected with the first wordline trench structure G1, referring to
In step S180, the first wordline trench structure G1, the second wordline trench structure G2 and the wordline tunnel G3 are filled to form an buried wordline structure 500 surrounding the fin-type structure 400, referring to
In the present embodiment, firstly, the first wordline trench structure G1 is formed; then, the first sacrificial layer 200 is formed at the bottom of the first wordline trench structure G1, the first wordline trench structure G1 located in the active regions AA is filled by epitaxial growth, and the second wordline trench structure G2 is formed by etching; next, the first sacrificial layer 200 is etched to form the wordline tunnel G3 connected with the first wordline trench structure G1; and finally, the first wordline trench structure G1, the second wordline trench structure G2 and the wordline tunnel G3 are filled with a metal conductive material with low resistance such as aluminum, tungsten, copper or a titanium aluminum alloy to form the buried wordline structure 500 surrounding the fin-type structure 400. Since the fin-type structure 400 is surrounded by the buried wordline structure 500, the switching efficiency can be improved, a threshold voltage thereof can be reduced, and an operating current thereof can be increased, which is conducive to improving the refresh efficiency.
In one embodiment, the semiconductor substrate 100 is a silicon-on-insulator (SOI) substrate, including a silicon material layer 110, a back substrate 130 and an oxide material layer 120 sandwiched between the silicon material layer 110 and the back substrate 130.
It may be understood that, in the present embodiment, the SOI substrate is used, and the oxide material layer 120 may be used as an etch stop layer in the process of etching the first wordline trench structure G1, to facilitate the control over the depth of the first wordline trench structure G1. Moreover, the oxide material layer 120 may eliminate the influence of a leakage current in a semiconductor substrate and further improve the performance of the semiconductor device. The silicon material layer 110 may be either an undoped silicon material layer 110 or a doped silicon material layer 110. The doped silicon material layer 110 may be an N-type or P-type doped silicon material layer 110.
In one embodiment, the step of forming a first wordline trench structure G1 in the semiconductor substrate 100 includes:
forming a photoresist layer on the semiconductor substrate 100;
forming, in the photoresist layer, a target pattern matching the first wordline trench structure G1;
etching the silicon material layer 110 by using the patterned photoresist layer as a mask layer and the oxide material layer 120 as an etch stop layer, to form the first wordline trench structure G1; and
removing the remaining photoresist layer.
In the present embodiment, the photoresist layer is formed by applying a layer of photoresist to a surface of the silicon material layer 110 by spin coating, and the photoresist layer is irradiated by a laser through a mask to cause a chemical reaction of a photoresist in an exposed region. Then, the photoresist in the exposed region or an unexposed region is dissolved and removed using a developing technology (the former is referred to as a positive photoresist and the latter as a negative photoresist), and a pattern on the mask is transferred to the photoresist layer to form a target pattern. Then, the silicon material layer 110 is etched by using the patterned photoresist layer as the mask layer and the oxide material layer 120 as the etch stop layer, to form the first wordline trench structure G1. Finally, the remaining photoresist layer is removed to form the first wordline trench structure G1.
In one embodiment, the first wordline trench structure G1 has a width ranging from 10 nm to 25 nm.
It may be understood that, the first sacrificial layer 200 is required to be formed subsequently in the first wordline trench structure G1, an aspect ratio of the first wordline trench structure G1 should be taken into account to avoid advanced sealing during filling of a material forming the first sacrificial layer 200, thus forming a cavity. The aspect ratio of the first wordline trench structure G1 should be controlled within a reasonable range. In the present embodiment, the depth of the first wordline trench structure G1 is equal to the thickness of the silicon material layer 110, which generally ranges from 100 nm to 200 nm. Thus, the width of the first wordline trench structure G1 may be set within a range of 10 nm to 25 nm and then the aspect ratio thereof is controlled within a range of 4 to 20, avoiding generation of a cavity in the first sacrificial layer 200. In the present embodiment, the first wordline trench structure G1 has a width ranging from 21 nm to 23 nm.
In one embodiment, the first sacrificial layer 200 is formed by a material having an etching selectivity greater than 1 relative to the silicon material layer 110 and the oxide material layer 120.
It may be understood that, when the first sacrificial layer 200 is formed by the material having an etching selectivity greater than 1 relative to the silicon material layer 110 and the oxide material layer 120, the material forming the first sacrificial layer 200 may be rapidly etched by dry etching by selecting suitable etch gas, and the silicon material layer 110 and the STI structure are slowly etched. The silicon material layer 110 and the STI structure are almost unetched. In the present embodiment, the first sacrificial layer 200 is formed by silicon nitride. In addition, other insulating materials with an etching ratio greater than 1 to Si and SiO may also be used instead of the silicon nitride.
In one embodiment, the step of forming a first sacrificial layer 200 at the bottom of the first wordline trench structure G1 includes:
depositing a silicon nitride material by using an atomic layer deposition technology on the semiconductor substrate 100 where the metal barrier layer is formed, to form a silicon nitride material layer 110 filling the first wordline trench structure G1 and covering the semiconductor substrate 100; and
etching back the silicon nitride material layer 110, and controlling a thickness of the remaining silicon nitride material layer to be 20 nm to 80 nm, to form the first sacrificial layer 200.
In the present embodiment, the silicon nitride material is deposited by using the atomic layer deposition technology to form the silicon nitride material layer 110 filling the first wordline trench structure G1 and covering the semiconductor substrate 100. Then, silicon nitride on a top surface of the semiconductor substrate 100 is etched away, and silicon nitride in the first wordline trench structure G1 is etched to a preset height range, to form the first sacrificial layer 200. In addition, the silicon nitride material layer 110 may also be formed in other deposition manners, such as chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma-enhanced CVD (PECVD) and atomic layer deposition (ALD).
In one embodiment, the first sacrificial layer 200 has a height H1 ranging from 20 nm to 80 nm.
In a specific design scheme, the first sacrificial layer 200 has a height ranging from 20 nm to 80 nm. Since the thickness of the first sacrificial layer 200 determines the lowest high end of the fin-type structure 400 and determines a position of a conductive channel, it should not be too small in general so as to prevent occurrence of a gap during subsequent filling of a metal material. Therefore, in the present embodiment, the height of the first sacrificial layer 200 is limited to a range of 20 nm to 80 nm. In some embodiments, the first sacrificial layer 200 has a height H1 ranging from 50 nm to 70 nm. Specifically, the first sacrificial layer 200 has a height of 50 nm, 55 nm, 60 nm, 65 nm or 70 nm.
When the first wordline trench structure G1 is filled by epitaxial growth after the first sacrificial layer 200 is formed, only a monocrystalline silicon material is fixedly grown on a sidewall of the silicon material layer 110, so as to achieve the purpose of filling the first wordline trench structure G1 located in the active regions AA. At the same time, the grown monocrystalline silicon material may have the same characteristics as the silicon material layer 110, and may also have different conductivity from the silicon material layer 110. Next, under a condition of 400° C. to 500° C., the silicon oxide material is deposited at a rate of 15 nm/s to 20 nm/s by a deposition process, and the first wordline trench structure G1 is sealed to form the first insulation layer. In general, the insulation layer on the surface of the semiconductor substrate 100 has a thickness ranging from 50 nm to 150 nm. In the present embodiment, the thickness of the insulation layer is set in a range of 50 nm to 150 nm. Then, the insulation layer and the semiconductor substrate 100 are etched to form the second wordline trench structure G2. In the present embodiment, the insulation layer and the semiconductor substrate 100 are etched by a dry etching process. Due to the geometric effect of the sidewall of the silicon material layer 110, the silicon oxide material forming the STI structure on the sidewall of the silicon material layer 110 may not be etched away.
In one embodiment, the first sacrificial layer 200 is removed by a wet etching process.
In the present embodiment, the first sacrificial layer 200 is made of a silicon nitride material. Since part of the silicon nitride material is located below the fin-type structure 400 and dry etching cannot be used, the silicon nitride material is removed by hot phosphoric acid at a temperature ranging from 80° C. to 120° C., or by high-temperature phosphoric acid at a temperature ranging from 150° C. to 200° C.
In one embodiment, the step of filling the first wordline trench structure G1, the second wordline trench structure G2 and the wordline tunnel G3 to form an buried wordline structure 500, as shown in
forming a gate oxide layer 510 on a sidewall and the bottom of the second wordline trench structure G2 and a sidewall and the top of the wordline tunnel G3;
forming a metal barrier layer 520 on the semiconductor substrate 100 where the gate oxide layer 510 is formed, the metal barrier layer 520 covering the gate oxide layer 510, the first insulation layer 300 and the STI structure;
filling a metal conductive material in the first wordline trench structure G1, the second wordline trench structure G2 and the wordline tunnel G3 to form a metal conductive layer 530; and
etching back the metal barrier layer 520 and the metal conductive material in the first wordline trench structure G1 and the second wordline trench structure G2 to a preset height to form the buried wordline structure 500.
In the present embodiment, the buried wordline structure 500 includes the gate oxide layer 510, the metal barrier layer 520 and the metal conductive layer 530. The metal conductive layer 530 is a tungsten material layer. In addition, a metal material with low resistance such as aluminum, copper or a titanium aluminum alloy may be used instead. The metal barrier layer 520 is made of a TiN material. A combination of a TiN material layer and the gate oxide layer 510, compared with the gate oxide layer 510 alone, is conducive to increasing a dielectric constant, reducing a gate length, increasing a driving current and reducing a threshold voltage. The gate oxide layer 510 is grown using an in-situ steam generation (ISSG) technology. In addition, the gate oxide layer 510 may also be grown by ALD or other thermal oxidation methods.
Referring to
forming a second insulation layer 600 on the semiconductor substrate 100 where the buried wordline structure 500 is formed, the second insulation layer 600 covering the first insulation layer 300 and the buried wordline structure 500.
In the present embodiment, a silicon nitride material is deposited by a deposition process on the semiconductor substrate 100 where the buried wordline structure 500 is formed, the first wordline trench structure G1 and the second wordline trench structure G2 are filled, and the first insulation layer 300 is covered. Above the first insulation layer 300, the second insulating layer 600 has a thickness ranging from 20 nm to 50 nm. In some embodiments, the second insulating layer 600 has a thickness of 40 nm, 45 nm or 50 nm. The silicon nitride material has good insulation performance, so in addition to preventing leakage by increasing the thickness of the insulation layer, the silicon nitride material is usually selected to manufacture the second insulation layer 600. In addition, the second insulation layer 600 may also be made of silicon nitride, silicon nitride carbide or other suitable insulating materials, but is not limited thereto.
Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor device. Still referring to
The semiconductor substrate 100 has STI structure and a plurality of active regions AA disposed in parallel.
The buried wordline structure 500 is located in the semiconductor substrate 100, extends along a first direction, and crosses the STI structure and the plurality of active regions AA.
The fin-type structure 400 is located in a region where the active regions AA intersect with the buried wordline structure 500, and the buried wordline structure 500 wraps around the fin-type structure 400.
The semiconductor device of the present invention includes the buried wordline structure 500 provided with the fin-type structure and surrounding the fin-type structure 400. Since the fin-type structure 400 is surrounded by the buried wordline structure 500, the switching efficiency can be improved, a threshold voltage thereof can be reduced, and an operating current thereof can be increased, which is conducive to improving the refresh efficiency.
In one embodiment, the semiconductor substrate 100 is an SOI substrate, including a silicon material layer 110, a back substrate 130 and an oxide material layer 120 sandwiched between the silicon material layer 110 and the back substrate 130.
It may be understood that, in the present embodiment, the SOI substrate is used, and the oxide material layer 120 may be used as an etch stop layer in the process of etching the first wordline trench structure G1, to facilitate the control over the depth of the first wordline trench structure G1. Moreover, the oxide material layer 120 may eliminate the influence of a leakage current in the semiconductor substrate and further improve the performance of the semiconductor device. The silicon material layer 110 may be either an undoped silicon material layer 110 or a doped silicon material layer 110. The doped silicon material layer 110 may be an N-type or P-type doped silicon material layer 110.
In one embodiment, the buried wordline structure 500 located below the fin-type structure 400 has a height ranging from 20 nm to 80 nm.
In a specific design scheme, the first sacrificial layer 200 has a height ranging from 20 nm to 80 nm. Since the thickness of the first sacrificial layer 200 determines the lowest height of the fin-type structure 400 and determines the position of the conductive channel, it should not be too small in general so as to prevent occurrence of a gap during subsequent filling of a metal material. Therefore, in the present embodiment, the height of the first sacrificial layer 200 is limited to a range of 20 nm to 80 nm. In some embodiments, the first sacrificial layer 200 has a height H1 ranging from 50 nm to 70 nm. Specifically, the first sacrificial layer 200 has a height of 50 nm, 55 nm, 60 nm, 65 nm or 70 nm.
In one embodiment, the buried wordline structure located above the fin-type structure has a height ranging from 10 nm to 100 nm.
In general, the formed second trench structure has a depth ranging from 50 nm to 150 nm. After the second trench structure is filled and etched back, an etch-back height in the second trench structure generally ranges from 50 nm to 100 nm, and the buried wordline structure located above the fin-type structure has a height ranging from 10 nm to 100 nm. A specific depth should be designed as required. In some embodiments, in a specific manufacturing process, the second trench structure formed in the silicon substrate has a depth ranging from 90 nm to 110 nm. After the second trench structure is filled and etched back, an etch-back height in the second trench structure generally ranges from 64 nm to 75 nm, and the buried wordline structure located above the fin-type structure has a height ranging from 30 nm to 45 nm. In some embodiments, the buried wordline structure located above the fin-type structure has a height of 30 nm, 35 nm, 40 nm or 45 nm. The position of the conductive channel can be determined by controlling the depth of the second trench structure, and the resistance value of the buried wordline structure can be adjusted by controlling the etch-back height in the second trench structure.
In one embodiment, the buried wordline structure 500 includes a metal conductive layer 530. The metal conductive layer 530 is insulated from the fin-type structure 400 and wraps around the fin-type structure 400. In the present embodiment, the metal conductive layer 530 is a tungsten material layer. In addition, a metal material with low resistance such as aluminum, copper or a titanium aluminum alloy may be used instead.
In one embodiment, the buried wordline structure 500 further includes:
a gate oxide layer 510 disposed on a surface of the semiconductor substrate facing the metal conductive layer 530 and wrapping the buried wordline structure 500; and
a metal barrier layer 520 disposed between the gate oxide layer 510 and the metal conductive layer 530.
In the present embodiment, the metal barrier layer 520 is made of a TiN material. A combination of a TiN material layer and the gate oxide layer 510, compared with the gate oxide layer 510 alone, is conducive to increasing a dielectric constant, reducing a gate length, increasing a driving current and reducing a threshold voltage. The gate oxide layer 510 is grown using an ISSG technology. In addition, the gate oxide layer 510 may also be grown by ALD or other thermal oxidation methods.
In one embodiment, the buried wordline structure 500 has a height ranging from 10 nm to 25 nm.
It may be understood that, the first sacrificial layer 200 is required to be formed subsequently in the first wordline trench structure G1, an aspect ratio of the first wordline trench structure G1 should be taken into account to avoid advanced sealing when a material forming the first sacrificial layer 200 is filled, thus forming a cavity. The aspect ratio of the first wordline trench structure G1 should be controlled within a reasonable range. In the present embodiment, the depth of the first wordline trench structure G1 is equal to the thickness of the silicon material layer 110, which generally ranges from 100 nm to 200 nm. Thus, the width of the first wordline trench structure G1 may be set within a range of 10 nm to 25 nm and then the aspect ratio thereof is controlled within a range of 4 to 20, avoiding generation of a cavity in the first sacrificial layer 200. In the present embodiment, the first wordline trench structure G1 has a width ranging from 21 nm to 23 nm.
In one embodiment, the semiconductor device further includes an insulation layer (300, 600) including a first insulation layer 300 and a second insulation layer 600. The second insulation layer 600 covers the first insulation layer 300 and the buried wordline structure 500.
In the present embodiment, above the first insulation layer 300, the second insulating layer 600 has a thickness ranging from 20 nm to 50 nm. In some other embodiments, the second insulating layer 600 has a thickness of 40 nm, 45 nm or 50 nm. The silicon nitride material has good insulation performance, so in addition to preventing leakage by increasing the thickness of the insulation layer, the silicon nitride material is usually selected to manufacture the second insulation layer 600. In addition, the second insulation layer 600 may also be made of silicon nitride, silicon nitride carbide or other suitable insulating materials, but is not limited thereto.
Technical features of the above embodiments may be combined randomly. To make descriptions brief, not all possible combinations of the technical features in the embodiments are described. Therefore, as long as there is no contradiction between the combinations of the technical features, they should all be considered as scopes disclosed in the specification.
The above embodiments only describe several implementations of the present invention, which are described specifically and in detail, and therefore cannot be construed as a limitation on the patent scope of the present invention. It should be pointed out that those of ordinary skill in the art may make various changes and improvements without departing from the ideas of the present invention, which shall all fall within the protection scope of the present invention. Therefore, the patent protection scope of the present invention shall be subject to the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202010092525.8 | Feb 2020 | CN | national |
This application is a continuation application of International Patent Application No. PCT/CN2021/076304, filed on Feb. 9, 2021, which claims priority to Chinese Patent Application No. 202010092525.8, filed with the Chinese Patent Office on Feb. 14, 2020 and entitled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”. International Patent Application No. PCT/CN2021/076304 and Chinese Patent Application No. 202010092525.8 are incorporated herein by reference in their entireties.
| Number | Name | Date | Kind |
|---|---|---|---|
| 7291533 | Von Schwerin | Nov 2007 | B2 |
| 7312114 | Kudelka | Dec 2007 | B2 |
| 20190043864 | Takesako | Feb 2019 | A1 |
| 20190131445 | Liu | May 2019 | A1 |
| Number | Date | Country |
|---|---|---|
| 102034761 | Apr 2011 | CN |
| 109216433 | Jan 2019 | CN |
| 109390339 | Feb 2019 | CN |
| 211789011 | Oct 2020 | CN |
| Entry |
|---|
| Written Opinion cited in PCT/CN2021/076304, mailed on May 14, 2021, 8 pages. |
| International Search Report as cited in PCT Application No. PCT/CN2021/076304 mailed May 14, 2021, 10 pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20220077289 A1 | Mar 2022 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2021/076304 | Feb 2021 | WO |
| Child | 17455691 | US |
