1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
In the field of semiconductor devices having a chip scale package (CSP) structure, a semiconductor device is manufactured such that after the manufacturing process has been accomplished, a resultant wafer is completed and then singulated as individual semiconductor chips.
A conventional CSP semiconductor device includes a passivation layer, a first insulation layer, a second insulation layer, and a solder ball. The passivation layer is formed at the outer periphery of a bond pad of a semiconductor die. The first insulation layer is formed on the passivation layer and the second insulation layer is formed on a redistribution layer electrically connected to the bond pad. The second insulation layer is a photosensitive material that is patterned to form an opening therein. The solder ball is electrically connected to the redistribution layer through the opening of the second insulation layer.
A semiconductor device and a manufacturing method thereof are disclosed. A first insulation layer is formed on a semiconductor die, a redistribution layer electrically connected to a bond pad is formed on the first insulation layer, and a second insulation layer covers the redistribution layer. The second insulation layer is made of a cheap, non-photosensitive material. Accordingly, the manufacturing cost of the semiconductor device can be reduced.
The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements.
Referring to
As illustrated in
The semiconductor die 110 is generally made of silicon, and includes a first surface ill, and a second surface 112 that is substantially planar and opposite to the first surface 111. The semiconductor die 110 also includes at least one bond pad 113 formed on the first surface 111. The bond pad 113 is a portion through which an electrical signal is input/output to/from the semiconductor die 110. Although the bond pad 113 is made of aluminum in the illustrated embodiment, a material of the bond pad 113 is not limited thereto. The semiconductor die 110 further includes a passivation layer 114 formed on a portion of the first surface 111 excluding the bond pad 113, that is, an outer periphery of the bond pad 113. The passivation layer 114 may be made of any one selected from an oxide layer (SiO2), a nitride layer (Si3N4), equivalents thereof, but aspects of the present invention are not limited thereto.
The first insulation layer 120 is formed on the passivation layer 114 corresponding to the outer periphery of the bond pad 113 to a certain thickness. That is to say, the first insulation layer 120 only covers the passivation layer 114 without covering the bond pad 113, i.e., the first insulation layer 120 has an opening formed therein through which the bond pad 113 is exposed. The first insulation layer 120 allows the semiconductor die 110 to be electrically insulated at areas other than the bond pad 113. The first insulation layer 120 may be made of at least one selected from the group consisting of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimidetriazine (BT), phenolic resin, and equivalents thereof, but aspects of the present invention are not limited thereto.
One end of the redistribution layer 130 is formed over the bond pad 113 and the other end thereof is formed to extend to an upper portion of the first insulation layer 120 by a certain length and generally to extend on the first surface 111 of the semiconductor die. The redistribution layer 130 serves to distribute an electric route of the semiconductor die 110. That is to say, the redistribution layer 130 relocates the electric route, so that the solder ball 150 may be adaptively connected to a pattern of the external circuit, irrespective of the location of the bond pad 113. The redistribution layer 130 may be made of at least one selected from the group consisting of copper (Cu), and equivalents thereof, but aspects of the present invention are not limited thereto.
The redistribution seed layer 140 may be formed between the redistribution layer 130 and the bond pad 113 and between the redistribution layer 130 and the first insulation layer 120. Generally, the redistribution seed layer 140 is between the redistribution layer 130 and the first surface 111 of the semiconductor die 110. The redistribution seed layer 140 may be formed by sequentially depositing titanium (Ti) and copper (Cu) or by sequentially depositing titanium tungsten (TiW) and copper (Cu), but aspects of the present invention may not be limited thereto. The redistribution seed layer 140 allows the redistribution layer 130 to be easily plated and firmly attached to the first insulation layer 120.
The solder ball 150 is fusibly attached onto the redistribution layer 130 in a substantially spherical shape. The solder ball 150 transfers electrical signals between the semiconductor die 110 and external circuits. The solder ball 150 may be made of at least one selected from the group consisting of Sn—Pb, Sn—Pb—Ag, Sn—Pb—Bi, Sn—Cu, Sn—Ag, Sn—Bi, Sn—Ag—Cu, Sn—Ag—Bi, Sn—Zn, and equivalents thereof, but aspects of the present invention are not limited thereto.
In order to securely bond the solder ball 150 with the redistribution layer 130, an under bumped metallurgy (UBM) layer (not illustrated) may further be provided between the solder ball 150 and the redistribution layer 130. The UBM layer may have at least one structure selected from the group consisting of multi-layered structures, including, but not limited to, chrome/chrome-copper alloy/copper (Cr/Cr—Cu/Cu), titanium-tungsten alloy/copper (Ti—W/Cu), aluminum/nickel/copper (Al/Ni/Cu), and equivalents thereof.
The second insulation layer 160 is formed directly on the redistribution layer 130 and on the first insulation layer 120 without the redistribution layer 130 to a predetermined thickness. Here, the second insulation layer 160 is formed such that the solder ball 150 is exposed upward. The second insulation layer 160 covers the redistribution layer 130, thereby preventing oxidation and contamination of the redistribution layer 130. The second insulation layer 160 may be made of at least one non-photosensitive material selected from the group consisting of epoxy molding compound (EMC), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimidetriazine (BT), phenolic resin, and equivalents thereof, but aspects of the present invention are not limited thereto. The non-photosensitive material for use in the second insulation layer 160 is cheaper than a photosensitive material for use in the first insulation layer 120. Here, since the solder ball 150 is first formed and the second insulation layer 160 is then formed, a photolithography process is not necessarily performed to form the second insulation layer 160. Therefore, the second insulation layer 160 may be made of a cheap, non-photosensitive material. That is to say, in a case where the solder ball 150 is formed before forming the second insulation layer 160, it is not necessary to perform a photolithography process for forming openings to distribute the solder ball 150 in the second insulation layer 160.
As described above, in the semiconductor device 100 according to an embodiment of the present invention, the second insulation layer 160 is made of a cheap, non-photosensitive material. Accordingly, the manufacturing cost is reduced, compared to a case where both the first insulation layer and the second insulation layer are made of costly, photosensitive materials. A board level reliability in a stackable semiconductor device can also be improved.
Next, a semiconductor device 200 according to another embodiment of the present invention will be described.
Referring to
As illustrated in
The semiconductor device 200 has substantially the same configuration and operation as the semiconductor device 100 according to the previous embodiment, except for the configuration of the second insulation layer 260. Accordingly, components each having the same configuration and operation for describing the previous embodiment are respectively identified by the same reference numerals, and their repetitive description will not be given. In the following, an explanation will be given with special reference to the second insulation layer 260.
The second insulation layer 260 has substantially the same configuration and operation with the second insulation layer 160. However, the second insulation layer 260 according to the present embodiment is formed by attaching an insulative dry film, i.e., non-photosensitive material, on the redistribution layer 130 and the first insulation layer 120 without the redistribution layer 130.
As described above, in the semiconductor device 200 according to another embodiment of the present invention, the second insulation layer 260 is made of a cheap, non-photosensitive material, such as an insulative dry film, compared to a case where both the first insulation layer and the second insulation layer are made of costly, photosensitive materials. Accordingly, the manufacturing process can be simplified and the manufacturing cost is also reduced.
Next, a semiconductor device 300 according to still another embodiment of the present invention will be described.
Referring to
As illustrated in
The semiconductor device 300 has substantially the same configuration and operation as the semiconductor device 100 illustrated in
The second insulation layer 360 has substantially the same configuration and operation with the second insulation layer 160. However, the second insulation layer 360 according to the present embodiment is made of epoxy, i.e, a non-photosensitive material.
As described above, in the semiconductor device 300 according to still another embodiment of the present invention, the second insulation layer 360 is made of a cheap, non-photosensitive material such as epoxy, thereby reducing the manufacturing cost, compared to a case where both the first insulation layer and the second insulation layer are made of costly, photosensitive materials.
Next, a semiconductor device 400 according to still another embodiment of the present invention will be described.
Referring to
As illustrated in
The semiconductor device 400 has substantially the same configuration and operation with the semiconductor device 100 illustrated in
The redistribution layer 430 has substantially the same configuration and operation with the redistribution layer 130 illustrated in
In a specific embodiment, as illustrated in
The redistribution seed layer 440 is made of the same material as that of the redistribution seed layer 140 illustrated in
The solder ball 450 is fusibly attached onto the redistribution layer 430 in a substantially spherical shape, and is made of the same material as the solder ball 150 illustrated in
The insulation layer 460 is made of the same material as the second insulation layer 160 illustrated in
As described above, in the semiconductor device 400 according to still another embodiment of the present invention, the insulation layer 460 covering the redistribution layer 430 and the passivation layer 114, is made of a cheap, non-photosensitive material, instead of using a costly, photosensitive insulation layer. Accordingly, the manufacturing cost can be reduced. A board level reliability (BRL) in a stackable semiconductor device can also be improved.
Next, a semiconductor device 500 according to still another embodiment of the present invention will be described.
Referring to
As illustrated in
The semiconductor device 500 has substantially the same configuration and operation as the semiconductor device 400 illustrated in
The insulation layer 560 has substantially the same configuration and operation with the insulation layer 460. However, the insulation layer 560 according to the present embodiment is formed by attaching an insulative dry film made of a non-photosensitive material on the redistribution layer 430 and the passivation layer 114 without the redistribution layer 530.
As described above, in the semiconductor device 500 according to still another embodiment of the present invention, the insulation layer 560 covering the redistribution layer 430 and the passivation layer 114 is made of a cheap, non-photosensitive material, such as an insulative dry film, instead of using a costly, photosensitive insulation layer. Accordingly, the manufacturing process is simplified.
Next, a semiconductor device 600 according to still another embodiment of the present invention will be described.
Referring to
As illustrated in
The semiconductor device 600 has substantially the same configuration and operation as the semiconductor device 400 illustrated in
The insulation layer 660 has substantially the same configuration and operation with the insulation layer 460, except that the insulation layer 660 according to the present embodiment is made of epoxy, i.e., is made of a non-photosensitive material. As illustrated in
As described above, in the semiconductor device 600 according to still another embodiment of the present invention, the insulation layer 660 covering the redistribution layer 430 and the passivation layer 114 is formed using a cheap, non-photosensitive material, such as epoxy, instead of forming a costly, photosensitive insulation layer, thereby reducing the manufacturing cost.
Alternatively, in the semiconductor device 600 according to still another embodiment of the present invention, the insulation layer 660 may be formed only on a portion of the redistribution layer 430, so that the redistribution layer 430 may not be disposed in a sawing line area during a wafer sawing process performed for singulation of the semiconductor device. Accordingly, the semiconductor device 600 according to still another embodiment of the present invention can reduce an amount of material required for forming the insulation layer 660, protect the redistribution layer 430 with a minimum amount of the insulation layer 660, and easily perform a sawing process. In addition, since the insulation layer 660 is partially formed on the semiconductor die, the insulation layer 660 is prevented from being peeled off or separated from the sawing line portion in a subsequent process following the sawing process.
Next, a semiconductor device 700 according to still another embodiment of the present invention will be described.
Referring to
As illustrated in
The semiconductor device 700 has substantially the same configuration and operation as the semiconductor device 400 illustrated in
The insulation layer 760 is made of the same material as that of the insulation layer 660 illustrated in
As described above, in the semiconductor device 700 according to still another embodiment of the present invention, the insulation layer 760 covering the redistribution layer 430 between the redistribution layer 430 and the passivation layer 114 is formed using a cheap, non-photosensitive material, such as epoxy, instead of forming a costly, photosensitive insulating layer. Accordingly, the manufacturing cost can be reduced and the redistribution layer 430 can be sufficiently protected from external impacts.
Next, a semiconductor device 800 according to still another embodiment of the present invention will be described.
Referring to
As illustrated in
The semiconductor device 800 has substantially the same configuration and operation as the semiconductor device 400 illustrated in
The redistribution layer 830 according to the present embodiment is made of the same material as that of the redistribution layer 430 illustrated in
The redistribution seed layer 840 according to the present embodiment is made of the same material as that of the redistribution seed layer 440 illustrated in
The solder ball 850 is fusibly attached onto a portion of the redistribution layer 830 in a substantially spherical shape, the portion vertically conforming to the bond pad 113, and is made of the same material as the solder ball 450 illustrated in
The insulation layer 860 is made of the same material as the second insulation layer 160 illustrated in
As described above, in the semiconductor device 800 according to still another embodiment of the present invention, the insulation layer 860 covering the passivation layer 114 is formed using a cheap, non-photosensitive material, instead of forming a costly, photosensitive insulation layer. Accordingly, the manufacturing cost can be reduced and a board level reliability in a stackable semiconductor device can also be improved.
Hereinafter, a manufacturing method of the semiconductor device 100 according to an embodiment of the present invention will be described.
Referring to
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
Meanwhile, in the forming of the second insulation layer of the semiconductor device 200 according to another embodiment of the present invention, an insulative dry film made of a non-photosensitive material, is attached onto the redistribution layer 130 and the first insulation layer 120 by laminating, thereby forming the second insulation layer 260 of
In the manufacturing method of the semiconductor device 300 according to still another embodiment of the present invention, epoxy flux in a liquid phase is coated on the first redistribution layer 130 and the first insulation layer 120 by printing and then positioned the solder ball 150 on the first redistribution layer 130, followed by curing, thereby forming the second insulation layer 360 of
Next, a manufacturing method of the semiconductor device 400 according to still another embodiment of the present invention will be described.
Referring to
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
Meanwhile in the manufacturing method of the semiconductor device 500 according to still another embodiment of the present invention, an insulative dry film, which is a non-photosensitive material, is attached onto the redistribution layer 430 and the passivation layer 114 by laminating, thereby forming the insulation layer 560 of
Further, in the manufacturing methods of the semiconductor devices 600 and 700 according to other embodiments of the present invention, in order to form insulating layers 660 of
In the manufacturing method of the semiconductor device 800 according to still another embodiment of the present invention, the forming of the insulation layer 860 includes forming the insulation layer 860 having a predetermined thickness on the passivation layer 114 so as to expose upward the solder ball 850 attached to the redistribution layer 830 vertically conforming to the bond pad 113. In an exemplary embodiment, a non-photosensitive material, that is, at least one selected from the group consisting of an epoxy molding compound (EMC), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimidetriazine (BT), phenolic resin, and equivalents thereof, is applied to the passivation layer 114 by molding, printing, spin coating, or dispensing, followed by curing, thereby acquiring the insulation layer 860 having a predetermined thickness.
This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process, may be implemented by one skilled in the art in view of this disclosure.
This application is a continuation of Paek et al., U.S. patent application Ser. No. 12/728,119, filed on Mar. 19, 2010, entitled “Semiconductor Device and Manufacturing Method Thereof”, which is herein incorporated by reference in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
5892179 | Rinne et al. | Apr 1999 | A |
6011314 | Leibovitz et al. | Jan 2000 | A |
6187615 | Kim | Feb 2001 | B1 |
6329608 | Rinne et al. | Dec 2001 | B1 |
6388203 | Rinne et al. | May 2002 | B1 |
6389691 | Rinne et al. | May 2002 | B1 |
6392163 | Rinne et al. | May 2002 | B1 |
6410414 | Lee | Jun 2002 | B1 |
6455408 | Hwang et al. | Sep 2002 | B1 |
6620633 | Hembree et al. | Sep 2003 | B2 |
6835595 | Suzuki et al. | Dec 2004 | B1 |
6841874 | Paek et al. | Jan 2005 | B1 |
6987319 | Paek et al. | Jan 2006 | B1 |
7023088 | Suzuki et al. | Apr 2006 | B2 |
7045893 | Paek et al. | May 2006 | B1 |
7096581 | Thomas et al. | Aug 2006 | B2 |
7157363 | Suzuki et al. | Jan 2007 | B2 |
7183645 | Kurosawa et al. | Feb 2007 | B2 |
7205660 | Park et al. | Apr 2007 | B2 |
7312143 | Park et al. | Dec 2007 | B2 |
7335986 | Paek et al. | Feb 2008 | B1 |
7545027 | Chung et al. | Jun 2009 | B2 |
7547623 | Mis et al. | Jun 2009 | B2 |
7566650 | Lin et al. | Jul 2009 | B2 |
7776655 | Do et al. | Aug 2010 | B2 |
7808105 | Paek | Oct 2010 | B1 |
7839000 | Mis et al. | Nov 2010 | B2 |
7901956 | Kuan et al. | Mar 2011 | B2 |
7932615 | Rinne | Apr 2011 | B2 |
7944048 | Jiang | May 2011 | B2 |
7977783 | Park et al. | Jul 2011 | B1 |
7977789 | Park | Jul 2011 | B2 |
7993976 | Do et al. | Aug 2011 | B2 |
8058726 | Jin et al. | Nov 2011 | B1 |
20020076913 | Lee | Jun 2002 | A1 |
20030214038 | Nemoto | Nov 2003 | A1 |
20050012225 | Choi et al. | Jan 2005 | A1 |
20060030139 | Mis et al. | Feb 2006 | A1 |
20060038291 | Chung et al. | Feb 2006 | A1 |
20060055037 | Park et al. | Mar 2006 | A1 |
20060214293 | Park et al. | Sep 2006 | A1 |
20070069346 | Lin et al. | Mar 2007 | A1 |
20070108573 | Chung et al. | May 2007 | A1 |
20070164431 | Lee et al. | Jul 2007 | A1 |
20070176290 | Park et al. | Aug 2007 | A1 |
20070182004 | Rinne | Aug 2007 | A1 |
20070184643 | Rinne | Aug 2007 | A1 |
20070252275 | Huang et al. | Nov 2007 | A1 |
20080012124 | Stapleton et al. | Jan 2008 | A1 |
20080042275 | Kuan et al. | Feb 2008 | A1 |
20080128905 | Lee et al. | Jun 2008 | A1 |
20080160682 | Song et al. | Jul 2008 | A1 |
20090166859 | Yuan et al. | Jul 2009 | A1 |
20090212427 | Mis et al. | Aug 2009 | A1 |
20090250813 | Lin et al. | Oct 2009 | A1 |
20090283903 | Park | Nov 2009 | A1 |
20100320624 | Kang et al. | Dec 2010 | A1 |
20110068427 | Paek et al. | Mar 2011 | A1 |
20110104888 | Kim et al. | May 2011 | A1 |
20110121295 | Kuan et al. | May 2011 | A1 |
20110229822 | Stapleton | Sep 2011 | A1 |
20110240912 | Kang et al. | Oct 2011 | A1 |
20110272819 | Park et al. | Nov 2011 | A1 |
20110278707 | Chi et al. | Nov 2011 | A1 |
Number | Date | Country |
---|---|---|
2008-218629 | Sep 2008 | JP |
Entry |
---|
Paek et al., “Semiconductor Device and Manufacturing Method Thereof,” U.S. Appl. No. 12/728,119, filed Mar. 19, 2010. |
Jin et al., “Semiconductor Device and Manufacturing Method Thereof,” U.S. Appl. No. 13/274,877, filed Oct. 17, 2011. |
Nangalia et al., “Electronic Component Package Fabrication Method and Structure,” U.S. Appl. No. 13/327,440, filed Dec. 15, 2011. |
Nangalia et al., “Electronic Component Package Fabrication Method and Structure,” U.S. Appl. No. 13/447,650, filed Apr. 16, 2012. |
Anderson et al., “Advances in WLCSP Technologies for Growing Market Needs,” Proceedings of SMTA's 6th Annual International Wafer Level Packaging Conference, Oct. 27-30, 2009, 6 pages, Santa Clara, CA. |
Stapleton et al., “Reliability of 400 μm Pitch WLCSP Assemblies with Solder Supporting Material,” IWLPC Conference Proceedings, Oct. 30, 2009, pp. 168-171. |
Stapleton, “Wafer Level Packaging: A Materials Roadmap,” IMAPS Chandler, Aug. 2009, 21 pages. |
No author provided, “Fujikura Wafer Level Chip Sized Package (WLCSP) Design Guide”, May 16, 2001, Rev. 1.4e, 14 pages. |
No author provided, “Wafer-Applied Underfill, LORD Scientist Featured by IMAPS,” LORD Corporation News Center, 1 page [online], Retrieved on Nov. 3, 2011 from the Internet: <URL:http://www.lord.com/news-center/news-stories/wafer-applied-underfill-lord-scientist-featured-by-imaps.xml>. |
No author provided, “LORD Corporation's Stapleton to Speak at International Wafer-Level Packaging Conference,” LORD Corporation News Center, 1 page [online], Retrieved on Nov. 3, 2011 from the Internet: <URL:http://www.lord.com/news-center/press-releases/lord-corporations-stapleton-to-speak-at-international-wafer-level-packaging-conference.xml>. |
Number | Date | Country | |
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Parent | 12728119 | Mar 2010 | US |
Child | 13738669 | US |