Patent Application
20240162340
The present application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2022-182496 filed on Nov. 15, 2022, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.
The disclosure discussed herein relates to a semiconductor device and a manufacturing method.
High electron mobility transistors (HEMTs) have been used extensively in amplifiers for frequency bands such as microwaves or millimeter waves, and signal processing circuits in optical communications. In HEMTs used in high frequency bands, the effect of the electrical resistance of the gate electrode on the high frequency signal is likely to be significant. Therefore, a HEMT with a lower gate electrode and an upper gate electrode has been proposed for the purpose of achieving both high frequency characteristics and mechanical strength (Patent Document 1).
According to an aspect of the present disclosure, a semiconductor device includes
The object and advantages of the embodiment will be realized and attained by means of the elements and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
The HEMT described in Patent Document 1 requires an opening with a large aspect ratio for the upper gate electrode in order to reduce parasitic capacitances between the upper gate electrode and the source and drain electrodes. It may be extremely difficult to manufacture such an opening with a large aspect ratio with high precision in practice. In particular, in HEMTs used in the sub-terahertz band, it may be particularly difficult to form an opening with a large aspect ratio because the gate length is as small as 100 nm or less to reduce parasitic capacitance and the distance between the source and drain electrodes is also small.
Thus, it is desirable to provide a semiconductor device capable of reducing the adverse effect of the electrical resistance of the gate electrode on the high-frequency signals, and a method of manufacturing such a semiconductor device.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the present specification and drawings, components having substantially identical functional configurations may be omitted from duplicate descriptions by assigning identical symbols. In the present specification and drawings, an X1-X2 direction, an Y1-Y2 direction, and a Z1-Z2 direction are mutually orthogonal. The plane including the X1-X2 direction and the Y1-Y2 direction is defined as an XY plane, the plane including the Y1-Y2 direction and the Z1-Z2 direction is defined as a YZ plane, and the plane including the Z1-Z2 direction and the X1-X2 direction is defined as a ZX plane. For convenience, the Z1 direction is defined as the upward direction and the Z2 direction is defined as the downward direction. In addition, in the present disclosure, the term “plan view” refers to viewing an object from the Z1 side.
A first embodiment will be described. The first embodiment relates to a semiconductor device including a high electron mobility transistor (HEMT).
As illustrated in
The substrate 101 is, for example, a SiC substrate, a Si substrate, a sapphire substrate, a GaN substrate, an AlN substrate or a diamond substrate. The initial layer 102 is, for example, an AlN layer, a GaN layer, or an AlGaN layer. The initial layer 102 may have a stacked structure containing two or more types of AlN, GaN, or AlGaN layers. The electron transit layer 103 is, for example, a non-doped GaN layer that is not intentionally doped. The spacer layer 104 is, for example, an AlN layer, or an AlGaN layer. The electron supply layer 105 is, for example, an AlGaN layer, an InAlN layer, an InAlGaN layer, an AlN layer, or a ScAlN layer.
The semiconductor layer 109 includes an active region 161 and an inactive region 162 surrounding the active region 161 in plan view. As illustrated in
A source electrode 112 and a drain electrode 113 are formed on the semiconductor layer 109 in the active region 161. The source electrode 112 and the drain electrode 113 extend parallel to the Y1-Y2 direction and are aligned in the X1-X2 direction. The source electrode 112 and the drain electrode 113 include, for example, a Ti film with a thickness of 2 nm to 50 nm and an Al film with a thickness of 100 nm to 300 nm above the Ti film, and are in ohmic contact with the semiconductor layer 109. A portion of the source electrode 112 and a portion of the drain electrode 113 may be on the semiconductor layer 109 in an inactive region 162.
On the electron supply layer 105, a passivation film 121 is formed covering the source electrode 112 and the drain electrode 113. The passivation film 121 contains, for example, oxides, nitrides, or oxynitrides of Si, Al, Hf, Zr, or Ta. The passivation film 121 is preferably a SiN film. The passivation film 121 may have a stacked structure containing multiple insulating films of these materials. The thickness of the passivation film 121 is, for example, 2 nm to 100 nm, and preferably approximately 50 nm.
In the passivation film 121, a gate opening 121G is formed between the source electrode 112 and the drain electrode 113 in plan view. A gate electrode 111 is formed on the passivation film 121. The gate electrode 111 extends parallel to the Y1-Y2 direction and is located between the source electrode 112 and the drain electrode 113 in plan view. The gate electrode 111 contacts the electron supply layer 105 through the gate opening 121G. The gate electrode 111 includes, for example, a Ni film with a thickness of 5 nm to 30 nm and an Au film with a thickness of 100 nm to 300 nm above the Ni film.
In plan view, the gate electrode 111 includes a first region 171 overlapping the active region 161, and two second regions 172 having the first region 171 interposed between the two second regions 172 and both overlapping the inactive region 162. In the longitudinal direction (parallel to the Y1-Y2 direction) of the gate electrode 111, the first region 171 is between the two second regions 172. In the direction parallel to the X1-X2 direction, that is, in the direction in which the source electrode 112 and the drain electrode 113 are aligned, the dimension of the first region 171 is smaller than that of the second region 172. The dimension of the second region 172 in the direction parallel to the X1-X2 direction is preferably 2 μm or more. The dimension of the lowest part of the first region 171 in the direction parallel to the X1-X2 direction, i.e., the gate length, is, for example, 100 nm or less.
The gate electrode 111 includes a first surface 111S that contacts the upper surface of the passivation film 121 at a position closer to the source electrode 112 than is the gate opening 121G, and a second surface 111D that contacts the upper surface of the passivation film 121 at a position closer to the drain electrode 113 than is the gate opening 121G. In plan view, the end of the second surface 111D closer to the drain electrode 113 side is farther from the gate opening 121G than the end of the first surface 111S closer to the source electrode 112 side.
An insulating film 122 covering the gate electrode 111 is formed on the passivation film 121. The insulating film 122 contains, for example, oxides, nitrides, or oxynitrides of Si, Al, Hf, Zr, or Ta. The insulating film 122 is preferably a SiN film. The insulating film 122 may have a stacked structure including multiple insulating films of these materials. The thickness of the insulating film 122 is, for example, 2 nm to 100 nm, and preferably approximately 50 nm.
A low permittivity film 123 is formed on the insulating film 122. The low permittivity film 123 is an insulating film whose relative permittivity is 3.0 or less. The material of the low permittivity film 123 is, for example, benzocyclobutene (BCB) or methylsilsesquioxane (MSQ). The relative permittivity of the low permittivity film 123 is preferably 2.5 or less. The thickness of the low permittivity film 123 is, for example, 1500 nm to 2000 nm, and preferably approximately 1900 nm.
A cavity 125 is formed between the insulating film 122 and the low permittivity film 123. The cavity 125 surrounds the gate electrode 111. More specifically, the upper surface of the insulating film 122 faces the cavity 125 around the gate electrode 111. The upper surface of a portion of the insulating film 122 directly contacting the gate electrode 111 is away from the low permittivity film 123. The height of the cavity 125 is between 500 nm and 1000 nm at the greatest extent, and preferably approximately 700 nm.
An insulating film 124 is formed on the low permittivity film 123. The insulating film 124 contains, for example, oxides, nitrides, or oxynitrides of Si, Al, Hf, Zr, or Ta. The insulating film 124 is preferably a SiN film. The insulating film 124 may have a stacked structure including multiple insulating films of these materials. The thickness of the insulating film 124 is, for example, 200 nm to 500 nm, and is preferably approximately 300 nm.
A multilayer insulating film 129 includes the passivation film 121, the insulating film 122, the low permittivity film 123, and the insulating film 124. An opening 129S reaching the source electrode 112, an opening 129D reaching the drain electrode 113, and an opening 129G reaching the gate electrode 111 are formed in the multilayer insulating film 129. The opening 129G reaches the two second regions 172 of the gate electrode 111.
Metal films 131, 132, and 133 are formed on the insulating film 124. The metal film 131 is in direct contact with the gate electrode 111 through the opening 129G. The metal film 131 is in direct contact with the two second regions 172. The metal film 132 is in direct contact with the source electrode 112 through the opening 129S. The metal film 133 is in direct contact with the drain electrode 113 through the opening 129D. The metal films 131, 132, and 133 include, for example, a seed layer and a plating layer on the seed layer. The seed layer includes, for example, a Ti layer, an Au layer, or a Cu layer. The plating layer includes, for example, an Au layer, or a Cu layer. In the cross section perpendicular to the longitudinal direction of the first region 171, the cross-sectional area of the metal film 131 is larger than that of the first region 171 of the gate electrode 111. Also, the electrical resistance of the metal film 131 is lower than that of the first region 171.
The metal film 131 is connected to a gate pad (not illustrated), the metal film 132 is connected to a source pad (not illustrated), and the metal film 133 is connected to a drain pad (not illustrated).
Next, a method of manufacturing the semiconductor device 100 according to the first embodiment will be described.
First, as illustrated in
Then, as illustrated in
Then, as illustrated in
Subsequently, a passivation film 121 is formed on the electron supply layer 105 as illustrated in
Then, as illustrated in
Then, as illustrated in
Subsequently, a sacrificial layer 128 is formed to form the cavity 125, as illustrated in
Then, as illustrated in
Subsequently, a resist pattern 181 is formed on the insulating film 124 as illustrated in
Then, as illustrated in
Then, as illustrated in
Subsequently, metal films 131, 132, and 133 are formed as illustrated in
In this manner, the semiconductor device 100 according to the first embodiment may be manufactured.
In the semiconductor device 100, the region where the 2DEG 150 exists functions as a channel, and the potential of the channel is controlled by the gate electrode 111. A control signal (high-frequency signal) is input from the gate pad to the gate electrode 111 through the metal film 131. In this embodiment, the gate electrode 111 includes two second regions 172 having the first region 171 interposed between the two second regions 172, and the metal film 131 is in contact with the two second regions 172. Therefore, high-frequency signals are input to the first region 171 from its both ends. Therefore, the phase shift of the high-frequency signal in the gate electrode 111 is reduced, and the adverse effect of the electrical resistance of the gate electrode 111 on the high-frequency signal can be reduced. That is, according to the first embodiment, excellent high-frequency characteristics can be obtained. For example, the maximum oscillation frequency can be improved. For example, the gain and efficiency can be improved for high-frequency signals in the sub-terahertz band with a frequency of 100 GHz or more.
Since the second region 172 is provided above the inactive region 162, the second region 172 is away from the source electrode 112 and the drain electrode 113. Therefore, even when the second region 172 is formed widely, the parasitic capacitance between the gate electrode 111 and the metal film 131 and the source electrode 112 and the drain electrode 113 can be kept low. Since the second region 172 is wide, the aspect ratio of the opening 129G can be kept small, and the opening 129G can be formed with high precision.
Furthermore, the metal film 131 is supported mainly by the low permittivity film 123, and the insulating film 124. Therefore, good mechanical strength can be ensured.
The gate opening 121G may be formed on the active region 161, and the inactive region 162 of the semiconductor layer 109 may be covered by the passivation film 121. That is, the second region 172 of the gate electrode 111 need not be in contact with the inactive region 162, but may be formed on the passivation film 121.
A second embodiment will be described. The second embodiment differs from the first embodiment mainly in the layout of active and inactive regions.
In the semiconductor device 200 according to the second embodiment, as illustrated in
Other configurations are the same as in the first embodiment.
In the second embodiment, as in the first embodiment, the adverse effect of the electrical resistance of the gate electrode 111 on the high-frequency signal can be reduced, and excellent high-frequency characteristics can be obtained. In addition, the opening 129G can be formed with high precision.
Semiconductor devices can be used, for example, in base stations for cellular communication, communication devices for radio astronomy, and communication devices for satellite communication.
Although the preferred embodiments have been described in detail above, the present invention is not limited to the above described embodiments, and various modifications and substitutions can be made to the above described embodiments without deviating from the scope of claims.
According to the present disclosure, it is possible to reduce an adverse effect of the electrical resistance of a gate electrode on the high-frequency signals.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiment(s) of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-182496 | Nov 2022 | JP | national |
