Patent Application
20250194230
The present disclosure relates to the field of semiconductor devices, and more particularly, to a bonded semiconductor device and a method for fabricating the same.
A three-dimensional integrated circuit (3D IC) refers to a three-dimensional stack of chips formed by using wafer-level bonding and through silicon via (TSV) technologies. In comparison with conventional two-dimensional chips, the 3D IC may have the advantages of using the space more effectively, shorter signal transmission distances between chips, and lower interconnecting resistances. As a result, 3D IC have gradually become the mainstream technology of power converters, low noise amplifiers, radio frequency (RF) or millimeter wave (MMW) components. Therefore, how to improve the properties of 3D IC, such as the electrical performance of 3D IC, has become a goal of relevant industries.
According to one aspect of the present disclosure, a semiconductor device includes a first wafer, a second wafer, a dielectric layer and a first metal structure. The first wafer includes a first substrate and a first interconnection layer disposed on the first substrate. The second wafer includes a second substrate and a second interconnection layer. The second substrate includes a buried oxide layer and a semiconductor layer disposed on the buried oxide layer. The second interconnection layer is disposed on the semiconductor layer, in which the second interconnection layer is bonded with the first interconnection layer. The dielectric layer is disposed on the buried oxide layer. The first metal structure is disposed through the dielectric layer, in which an end of the first metal structure physically contacts the buried oxide layer, and the buried oxide layer is grounded through the first metal structure.
According to another aspect of the present disclosure, a method for fabricating a semiconductor device includes steps as follows. A first wafer is provided, in which the first wafer includes a first substrate and a first interconnection layer disposed on the first substrate. A second wafer is provided, in which the second wafer includes a second substrate and a second interconnection layer, the second substrate includes a buried oxide layer and a semiconductor layer disposed on the buried oxide layer, and the second interconnection layer is disposed on the semiconductor layer. The second interconnection layer is bonded the with first interconnection layer. A dielectric layer is formed on the buried oxide layer. A first metal structure is formed through the dielectric layer, in which an end of the first metal structure physically contacts the buried oxide layer, and the buried oxide layer is grounded through the first metal structure.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In the following detailed description of the embodiments, reference is made to the accompanying drawings which form a part thereof, and in which is shown by way of illustration specific embodiments in which the disclosure may be practiced. In this regard, directional terminology, such as up, down, left, right, front, back, bottom or top is used with reference to the orientation of the Figure(s) being described. The elements of the present disclosure can be positioned in a number of different orientations. As such, the directional terminology is used for purposes of illustration and is in no way limiting. In addition, identical numeral references or similar numeral references are used for identical elements or similar elements in the following embodiments.
Hereinafter, for the description of “the first feature is formed on or above the second feature”, it may refer that “the first feature is in contact with the second feature directly”, or it may refer that “there is another feature between the first feature and the second feature”, such that the first feature is not in contact with the second feature directly.
It is understood that, although the terms first, second, etc. may be used herein to describe various elements, regions, layers and/or sections, these elements, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, region, layer and/or section from another element, region, layer and/or section. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, region, layer and/or section discussed below could be termed a second element, region, layer and/or section without departing from the teachings of the embodiments. The terms used in the claims may not be identical with the terms used in the specification, but may be used according to the order of the elements claimed in the claims.
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For example, the first wafer 10 may be fabricated as follows. First, the first substrate 110 may be provided first. The first substrate 110, for example, may be a silicon on insulator (SOI) substrate, which mainly includes a semiconductor layer (not shown, also called bottom semiconductor layer below for the convenience of explanation), a buried oxide layer 112 disposed on the bottom semiconductor layer, and another semiconductor layer 114 (also called top semiconductor layer) disposed on the buried oxide layer 112. The materials of the aforementioned bottom semiconductor layer (not shown) and the semiconductor layer 114 may be the same or different, and may independently include silicon, germanium, silicon germanium or a combination thereof, and the material of the buried oxide layer 112 may include silicon dioxide, but not limited thereto.
Next, a portion of the semiconductor layer 114 may be removed to form a shallow trench isolation (STI) 80 surrounding an active region (not labeled). The active region surrounded by the shallow trench isolation 80 may be configured to disposed active elements, such as a first transistor 160.
Next, the first transistor 160 is formed in the first substrate 110. In the embodiment, the first transistor 160 is exemplarily an N-type metal oxide semiconductor (NMOS) transistor for explanation, but the present disclosure is not limited thereto. The first transistor 160 includes a well region 164 disposed in the semiconductor layer 114 surrounded by the shallow trench isolation 80, a gate structure 162 disposed on the semiconductor layer 114 surrounded by the shallow trench isolation 80 and located above the well region 164, a spacer 163 disposed on the sidewall of the gate structure 162, and two source/drain regions 166 disposed in the semiconductor layer 114 at two sides of the spacer 163. The conductivity types of the two source/drain regions 166 are the same with each other and are different from the conductivity type of the well region 164. Herein, because the first transistor 160 is exemplarily an NMOS transistor, the well region 164 is a P-type well region which may be doped with P-type dopants, such as boron, indium, etc., and the source/drain regions 166 are N-type source/drain regions which may be doped with N-type dopants, such as arsenic, phosphorus, etc.
The gate structure 162 may include a gate dielectric layer (not shown) and a gate material layer (not shown) from bottom to top. The material of the gate dielectric layer may include silicon dioxide, silicon nitride or a high dielectric constant (high-k) material. The material of the gate material layer may include a conductive material, such as doped polycrystalline silicon, doped amorphous silicon, metal or metal compounds. However, the present disclosure is not limited thereto. The gate structure 162 may include other material layers depending on actual needs. For example, the gate structure 162 may optionally include one or more work function metal layers and/or barrier layers disposed between the gate dielectric layer and the gate material layer. The spacer 163 may be a single material layer or a stack of material layers. The material of the spacer 163 may include an oxide and/or a nitride, such as silicon dioxide, silicon nitride, silicon oxynitride or silicon carbonitride.
Next, a dielectric layer 120 is formed on the first substrate 110 to cover the first transistor 160. Before forming the dielectric layer 120, a contact etch stop layer (CESL) (not shown) may be optionally formed on the first substrate 110 to cover the first transistor 160. The material of the dielectric layer 120 may exemplarily include oxide, such as an silicon dioxide, borophosphosilicate glass (BPSG), tetraethoxysilane (TEOS), spin-on glass (SOG), undoped silicate glass (USG) or fluorinated silicate glass (FSG), and the material of the CESL may exemplarily include silicon nitride, but not limited thereto.
Next, semiconductor processes, such as lithography and etching processes, may be performed to remove a portion of the dielectric layer 120 and a portion of the CESL to form a plurality of contact holes 167 to expose the gate structure 162 and the two source/drain regions 166 of the first transistor 160. Next, a contact plug process is performed. For example, a conductive layer (not shown) may be firstly formed to fill the contact holes 167 completely, and then a planarization process such as a chemical mechanical polishing (CMP) process may be performed to remove a portion of the conductive layer, so as to form a plurality of contact plugs 168 in the dielectric layer 120 to be electrically connected with the gate structure 162 and the two source/drain regions 166. The top surface of the contact plug 168 may be aligned with the top surface of the dielectric layer 120.
Next, semiconductor processes, such as lithography and etching processes, may be performed to remove a portion of the dielectric layer 120, a portion of the CESL, a portion of the semiconductor layer 114 (or the shallow trench isolation 80 disposed in the semiconductor layer 114) and a portion of the buried oxide layer 112 to form the contact holes 169. Next, another contact plug process may be performed. For example, a conductive layer (not shown) may be firstly formed to fill the contact hole 169 completely, and then a planarization process such as a CMP process may be performed to remove a portion of the conductive layer, so as to form a third metal structure 66 disposed through the dielectric layer 120, and the semiconductor layer 114 (or the shallow trench isolation 80 disposed in the semiconductor layer 114) and the buried oxide layer 112 of the first substrate 110. That is, the third metal structure 66 is a through silicon via (TSV).
The materials of the conductive layers forming the contact plugs 168 and the third metal structure 66 may be the same or different, and may independently include a barrier layer (not shown) and a metal layer (not shown). The material of the barrier layer may include titanium, tantalum, titanium nitride, tantalum nitride, nitrogen or a combination thereof, and the material of the metal layer may include aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper or a combination thereof, but not limited thereto.
Afterward, a metal interconnection process may be performed to form the first interconnection layer 130 on the dielectric layer 120. For example, a stop layer (not shown) and an inter-metal dielectric layer 132 may be formed sequentially on the surface of the dielectric layer 120, and then one or more lithography and etching processes may be performed to remove a portion of the inter-metal dielectric layer 132 and a portion of the stop layer to form contact holes (not labeled). Next, a conductive material is completely filled into each of the contact holes and a planarization process such as a CMP process is performed to form metal interconnections 134 to connect the contact plugs 168 and the third metal structure 66 below. The above process may be repeated to form the first interconnection layer 130 including a plurality of layers with the inter-metal dielectric layers 132 and the metal interconnections 134 on the dielectric layer 120 according to process requirements, so as to complete the back-end-of-the-line (BEOL) process. The material of metal interconnections 134 may be the same as that of the third metal structure 66, and are not repeated herein. Next, the bottom semiconductor layer of the first substrate 110 may be completely removed by a CMP process to expose the bottom of the third metal structure 66.
It is noted that of the first wafer 10 according to the present disclosure may be optionally formed with a trap rich layer 140 and a supporting substrate 150 on the back side of the first substrate 110. For example, the trap rich layer 140 may be firstly formed on the supporting substrate 150, and then an oxide layer (not shown) for bonding with the buried oxide layer 112 may be formed on the trap rich layer 140. Next, the first substrate 110 is thinned to remove the bottom semiconductor layer of the first substrate 110. Next, the thinned first substrate 110 is bonded with the supporting substrate 150 formed with the trap rich layer 140. The supporting substrate 150 may be, for example, a high-resistance silicon substrate with an extremely low doping amount. The trap rich layer 140 may be formed, for example, by depositing a high-resistance material on the supporting substrate 150. The high-resistance material may be a polycrystalline semiconductor material or an amorphous semiconductor material, such as polycrystalline silicon or amorphous silicon. Alternatively, the trap rich layer 140 may be formed by an ion implantation process to bombard and destroy the surface of the supporting substrate 150 with high-energy particles. The oxide layer may be a superficial oxide layer, and the material of the oxide layer may be the same as the buried oxide layer 112 to provide better interface performance, but not limited thereto. With the trap rich layer 140, it is beneficial to reduce nonlinear parasitic capacitance and parasitic surface conduction. Accordingly, it is beneficial to reduce noises. Thereby, the fabrication of the first wafer 10 is completed. Furthermore, in other embodiments of the present disclosure, a SOI substrate which already has the trap rich layer 140 may be directly used as the first substrate 110, and then the aforementioned structures, such as the first transistor 160, the third metal structure 66 and the metal interconnections 134, are sequentially formed thereon.
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Next, a portion of the semiconductor layer 214 may be removed to form a shallow trench isolation 80 surrounding an active region (not labeled). The active region surrounded by the shallow trench isolation 80 may be configured to disposed active elements, such as a second transistor 260.
Next, the second transistor 260 and a diode 70 are formed in the second substrate 210. In the embodiment, the second transistor 260 is exemplarily an NMOS transistor for explanation, but the present disclosure is not limited thereto. The second transistor 260 includes a well region 264 disposed in the semiconductor layer 214 surrounded by the shallow trench isolation 80, a gate structure 262 disposed on the semiconductor layer 214 surrounded by the shallow trench isolation 80 and located above the well region 264, a spacer 263 disposed on the sidewall of the gate structure 262 and two source/drain regions 266 disposed in the semiconductor layer 214 at two sides of the spacer 263. For details of the second transistor 260, references may be made to the above description relating to the first transistor 160 and are not repeated herein. The diode 70 includes an N-type doped region 710 and a P-type doped region 720, and a doping concentration of the P-type doped region 720 may be higher than that of the N-type doped region 710. The N-type doped region 710 may be doped with N-type dopants, such as arsenic, phosphorus, etc. The P-type doped region 720 may be doped with P-type dopants, such as boron, indium, etc.
Next, a dielectric layer 220 is formed on the second substrate 210 to cover the second transistor 260. Before forming the dielectric layer 220, a CESL (not shown) may be optionally formed on the second substrate 210 to cover the second transistor 260. Next, semiconductor processes, such as lithography and etching processes, may be used to remove a portion of the dielectric layer 220 and a portion of the CESL to form a plurality of contact holes 267 to expose the gate structure 262 and the two source/drain regions 266 of the second transistor 260 and the P-type doped region 720 of the diode 70. Next, a contact plug process is performed, so as to form a plurality of contact plugs 268 in the dielectric layer 220 to be electrically connected with the gate structure 262, the two source/drain regions 266 and the P-type doped region 720. The top surface of the contact plug 268 may be aligned with the top surface of the dielectric layer 220. For details of the dielectric layer 220 and the contact plugs 268, references may be made to the above description relating to the dielectric layer 120 and the contact plugs 168, and are not repeated herein.
Afterward, a metal interconnection process may be performed to form the second interconnection layer 230 on the dielectric layer 220. For example, a stop layer (not shown) and an inter-metal dielectric layer 232 may be formed sequentially on the surface of the dielectric layer 220, and then one or more lithography and etching processes may be performed to remove a portion of the inter-metal dielectric layer 232 and a portion of the stop layer to form contact holes (not shown). Next, a conductive material is filled into each of the contact holes completely and a planarization process such as a CMP process is performed to form metal interconnections 234 to connect the contact plugs 268 below and the first metal structure 62 (see
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The first wafer 10 includes the first substrate 110 and the first interconnection layer 130 disposed on the first substrate 110. The second wafer 20 includes the second substrate 210 and the second interconnection layer 230. The second substrate 210 includes the buried oxide layer 212 and the semiconductor layer 214 disposed on the buried oxide layer 212. The second interconnection layer 230 is disposed on the semiconductor layer 214. The second interconnection layer 230 is bonded with the first interconnection layer 130. The dielectric layer 30 is disposed on the buried oxide layer 212 of the second substrate 210. The first metal structure 62 is disposed through the dielectric layer 30, in which the end 621 of the first metal structure 62 physically contacts the buried oxide layer 212, and the buried oxide layer 212 is grounded through the first metal structure 62. Herein, the end 621 of the first metal structure 62 physically contacts the buried oxide layer 212, and the other end 622 of the first metal structure 62 is connected with the first metal pad 410. That is, the buried oxide layer 212 can be grounded through the first metal structure 62 and the first metal pad 410.
As mentioned above, during the process of removing the semiconductor layer 216, charges may be accumulated in the buried oxide layer 212. In the present disclosure, at least one charge release path may be formed by the first metal structure 62 and the first metal pad 410. The at least one charge release path may be configured for transporting the charges accumulated in the buried oxide layer 212 to the outside, which is beneficial to improve the electrical performance of the second transistor 260. For example, it can prevent the decrease of the breakdown voltage of the second transistor 260.
Specifically, the first wafer 10 may include the supporting substrate 150, the trap rich layer 140, the first substrate 110, the dielectric layer 120 and the first interconnection layer 130 from bottom to top, and may further include the first transistor 160 and the third metal structure 66. The first substrate 110 includes the buried oxide layer 112 and the semiconductor layer 114. The semiconductor layer 114 is disposed on the buried oxide layer 112. The first interconnection layer 130 is disposed on the semiconductor layer 114 of the first substrate 110. Herein, the first interconnection layer 130 is disposed on the semiconductor layer 114 through the dielectric layer 120. The trap rich layer 140 is disposed on the buried oxide layer 112 of the first substrate 110. The first transistor 160 is disposed in the semiconductor layer 114. The first transistor 160 includes the well region 164 and the two source/drain regions 166 disposed in the semiconductor layer 114, the gate structure 162 disposed on the semiconductor layer 114, and the spacer 163 disposed on the sidewall of the gate structure 162. The gate structure 162 and the two source/drain regions 166 are electrically connected with the metal interconnections 134 in the first interconnection layer 130 through the contact plugs 168. The third metal structure 66 is disposed through the dielectric layer 120 and the semiconductor layer 114 and the buried oxide layer 112 of the first substrate 110. The end 661 of the third metal structure 66 physically contacts the trap rich layer 140, and the other end 662 of the third metal structure 66 is electrically connected with the second metal pad 420. Herein, the other end 662 of the third metal structure 66 is electrically connected with the second metal pad 420 through the metal interconnections 134 in the first interconnection layer 130, the metal interconnections 234 in the second interconnection layer 230 and the fourth metal structure 68.
The second wafer 20 may include the second substrate 210, the dielectric layer 220 and the second interconnection layer 230 from top to bottom, and may further include the second transistor 260 and the diode 70. The second substrate 210 includes the buried oxide layer 212 and the semiconductor layer 214. The semiconductor layer 214 is disposed on the buried oxide layer 212. The second interconnection layer 230 is disposed on the semiconductor layer 214 of the second substrate 210. Herein, the second interconnection layer 230 is disposed on the semiconductor layer 214 through the dielectric layer 220. The second transistor 260 and the diode 70 are disposed in the semiconductor layer 214. The second transistor 260 includes the well region 264 and the two source/drain regions 266 disposed in the semiconductor layer 214, the gate structure 262 disposed on the semiconductor layer 214, and the spacer 263 disposed on the sidewall of the gate structure 262. The diode 70 includes the N-type doped region 710 and the P-type doped region 720 disposed in the semiconductor layer 214, and the diode 70 directly or physically contacts the buried oxide layer 212. The gate structure 262, the second source/drain regions 266 and the P-type doped region 720 are electrically connected with the metal interconnections 234 in the second interconnection layer 230 through the contact plugs 268.
The second interconnection layer 230 includes the metal layer 2341. The metal layer 2341 is a portion of the metal interconnections 234 in the second interconnection layer 230 and is the portion of the metal interconnections 234 closest to the second substrate 210. One of the two source/drain regions 266 (herein, the source/drain region 266 at the right side) is electrically connected with the first metal pad 410 through the contact plug 268, the metal layer 2341 and the second metal structure 64, in which the end 641 of the second metal structure 64 is connected with the metal layer 2341, and the other end 642 of the second metal structure 64 is connected with the first metal pad 410. The diode 70 is electrically connected with the first metal pad 410. Herein, the diode 70 is electrically connected with the first metal pad 410 through the contact plug 268, the metal layer 2341 and the second metal structure 64. Thereby, the diode 70, the contact plug 268, the metal layer 2341, the second metal structure 64 and the first metal pad 410 may form a charge release path, which may transport the charges accumulated in the buried oxide layer 212 to the outside, thereby the electrical performance of the second transistor 260 may be maintained. For example, it can prevent the decrease of the breakdown voltage of the second transistor 260. Furthermore, the diode 70 can utilize the existing conductive paths of the second transistor 260 (i.e., the metal layer 2341, the second metal structure 64 and the first metal pad 410) to transport the charges accumulated in the buried oxide layer 212 to the outside without fabricating an additional conductive path, which is beneficial to simply the process.
Compared with the prior art, the semiconductor device of the present disclosure includes a first metal structure. An end of the first metal structure physically contacts the buried oxide layer, so that the buried oxide layer may be grounded through the first metal structure, which is beneficial to form a charge release path for transporting the charges accumulated in the buried oxide layer during the manufacturing process to the outside, which is beneficial to improve the electrical performance of the semiconductor device. The semiconductor device may further include a diode. The diode directly or physically contacts the buried oxide layer, so that the buried oxide layer may be grounded through the diode, which may provide another charge release path for transporting the charges accumulated in the buried oxide layer to the outside, so as to further improve the electrical performance of the semiconductor device.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112147850 | Dec 2023 | TW | national |
