Patent Application
20080087912
A semiconductor device according to Embodiment 1 of the invention, that is, a high-breakdown voltage semiconductor switching device specifically, will now be described with reference to the accompanying drawings.
In the base region 206, a contact region 210 of, for example, P+-type conductivity (with, for example, an impurity concentration of 1×1019/cm3 and a depth of 2 μm) and an emitter region 208 of, for example, N+-type conductivity (with, for example, an impurity concentration of 1×1020/cm3 and a depth of 0.5 μm) are formed to be spaced from the resurf region 202. Also, a gate insulating film 203 is formed so as to cover a portion of the base region 206 disposed between the emitter region 208 and the resurf region 202, and a gate electrode 207 is formed on the gate insulating film 203.
When the gate insulating film 203 is formed to extend over the emitter region 208, a short circuit between the gate electrode 207 and the emitter region 208 can be prevented.
Furthermore, a top semiconductor layer 205 of, for example, P-type conductivity (with, for example, an impurity concentration of 1×1016/cm3 and a depth of 1 μm) is formed in a surface portion of the resurf region 202. Although not shown in the drawing, the top semiconductor layer 205 is electrically connected to the base region 206 through a given portion of the resurf region 202, an upper layer interconnect or the like.
Also, a collector region 215 of, for example, P-type conductivity (with, for example, an impurity concentration of 1×1016/cm3 and a depth of 1 μm) is formed in a surface portion of the resurf region 202 to be spaced from the top semiconductor layer 205. At this point, the collector region 215 has substantially the same impurity concentration as and is disposed at substantially the same depth as the top semiconductor layer 205.
A collector contact region 209 of, for example, P+-type conductivity (with, for example, an impurity concentration of 1×1019/cm3 and a depth of 0.5 μm) is formed in a surface portion of the collector region 215. It is noted that the collector contact region 209 can be omitted.
An interlayer film 211 is formed above the semiconductor substrate 201 having the aforementioned various impurity regions and the like with a field insulating film 204 formed between the semiconductor substrate 201 including the resurf region 202 and the interlayer film 211.
Above the semiconductor substrate 201, a collector electrode 212 penetrating the interlayer film 211 and electrically connected to the collector contact region 209 (i.e., the collector region 215) is formed, and an emitter electrode 213 penetrating the interlayer film 211 and electrically connected to both the contact region 210 (i.e., the base region 206) and the emitter region 208 is formed.
A protective film 214 is formed on the interlayer film 211 on which the collector electrode 212 and the emitter electrode 213 are formed.
In the semiconductor device of this embodiment, in the case where a positive voltage is applied to the gate electrode 207 with positive bias applied between the collector electrode 212 and the emitter electrode 213 (with a side of the collector electrode 212 set to high potential), holes are injected from the collector region 215 to the resurf region 202 when a potential difference caused between the potential of the collector region 215 and the potential of a portion of the resurf region 202 surrounding the collector region 215 becomes approximately 0.6 V, and thus, an IGBT operation is started.
In other words, the semiconductor device (the switching device) of this embodiment is a lateral type IGBT. In this IGBT, the impurity concentration in the collector region 215 is set to be as low as the impurity concentration in the top semiconductor layer 205, and therefore, as compared with the case where the collector region is made of a high concentration layer (a P+-type layer), the amount of excessive carriers injected into the semiconductor substrate 201 including the resurf region 202 during the IGBT operation can be suppressed. As a result, the amount of excessive carriers remaining in the semiconductor substrate 201 in turn off can be so reduced that time necessary for drawing the carriers can be shortened, and hence, the switching speed can be improved, resulting in reducing switching loss. In other words, a high-breakdown voltage semiconductor device in which loss can be reduced in the whole region ranging from light load to heavy load can be realized.
Moreover, in the case where the collector region is made of a high concentration layer, it is necessary to provide a buffer layer of, for example, N-type conductivity with a higher impurity concentration than the resurf region between the collector region and the resurf region for reducing the efficiency for injecting holes from the collector region to the resurf region. On the contrary, since the collector region 215 is formed to have a low concentration in the semiconductor device of this embodiment, there is no need to provide such an N-type buffer layer, and hence, the fabrication process can be simplified.
Now, an exemplified method for fabricating the switching device of this embodiment shown in
First, in a procedure shown in
Next, in a procedure shown in
It is noted that the top semiconductor layer 205 is electrically connected to a base region 206 described below although not shown in the drawing.
Then, in a procedure shown in
It is noted that the order of performing ion implantation for forming the respective impurity regions of this embodiment is not particularly specified.
Next, in a procedure shown in
Then, in a procedure shown in
Next, in a procedure shown in
In the fabrication method of this embodiment described above, the top semiconductor layer 205 and the collector region 215 are formed in one and the same impurity implantation process, and therefore, the number of procedures can be reduced and the cost can be lowered as compared with the case where they are individually formed.
As a power semiconductor device with a high voltage and high power having low on resistance and a high switching off speed, a structure composed of a lateral double diffused MOS (LDMOS) and a lateral insulating gate bipolar transistor (LIGBT) both formed on the same substrate has been proposed (see, for example, Patent Document 7).
A semiconductor device of Patent Document 7 has a double gate structure in which a gate of an LIGBT and a gate of an LDMOS are individually provided and an anode of the LIGBT and a drain of the LDMOS are isolated from each other by a trench well.
Apart from the semiconductor device of Patent Document 7, the present inventor has proposed, in Patent Document 8, a single gate lateral type IGBT structure capable of performing both the MOSFET operation and the IGBT operation with a simple structure not using trench well isolation.
Now, a semiconductor device having the IGBT structure proposed by the present inventor will be described as a comparative example with reference to the accompanying drawings.
As shown in
In the base region 106, a P+-type contact region 110 (with, for example, an impurity concentration of 1×1019/cm3 and a depth of 2 μm) and an N+-type emitter/source region 108 (with, for example, an impurity concentration of 1×1020/cm3 and a depth of 0.5 μm) are formed to be spaced from the resurf region 102. Furthermore, a gate insulating film 103 is formed so as to cover a portion of the base region 106 disposed between the emitter/source region 108 and the resurf region 102, and a gate electrode 107 is formed on the gate insulating film 103.
On the other hand, a P-type top semiconductor layer 105 (with, for example, an impurity concentration of 1×1016/cm3 and a depth of 1 μm) electrically connected to the base region 106 is formed in a surface portion of the resurf region 102.
A P+-type collector region 109 (with, for example, an impurity concentration of 1×1019/cm3 and a depth of 1 μm) is formed in a surface portion of the resurf region 102 to be spaced from the top semiconductor layer 105 (see
Furthermore, an N+-type drain region 116 (with, for example, 1×1020/cm3 and a depth of 0.5 μm) electrically connected to the collector region 109 is formed in a surface portion of the resurf region 102 to be spaced from the top semiconductor layer 105 (see
At this point, as shown in
An interlayer film 111 is formed above the semiconductor substrate 101 including the aforementioned various impurity regions and the like with a field insulating film 104 formed between the semiconductor substrate 101 including the resurf region 102 and the interlayer film 111.
Above the semiconductor substrate 101, a collector/drain electrode 112 penetrating the interlayer film 111 and electrically connected to both the collector region 109 and the drain region 116 is formed, and an emitter/source electrode 113 penetrating the interlayer film 111 and electrically connected to both the contact region 110 (i.e., the base region 106) and the emitter/source region 108 is formed.
A protective film 114 is formed on the interlayer film 111 on which the collector/drain electrode 112 and the emitter/source electrode 113 are formed.
In the semiconductor device of the comparative example, when a positive voltage is applied to the gate electrode 107 with positive bias (hereinafter sometimes referred to as the collector voltage) applied between the collector/drain electrode 112 and the emitter/source electrode 113, an electron current (hereinafter sometimes referred to as the collector current) flows from the drain region 116 toward the emitter/source electrode 113, and thus, a MOSFET operation is performed. Moreover, when the electron current, i.e., the collector current, flowing toward the emitter/source electrode 113 is increased to some extent and a potential difference caused between the potential of the collector region 109 and the potential of a portion of the resurf region 102 surrounding the collector region 109 becomes approximately 0.6 V, holes are injected from the collector region 109 to the resurf region 102, and thus, the MOSFET operation is changed to an IGBT operation.
In this manner, in the semiconductor device of the comparative example, when the collector current flowing in the device is comparatively small, the MOSFET operation can be performed while the IGBT operation can be performed when the collector current flowing in the device is increased to some extent. In other words, a semiconductor device capable of performing the MOSFET operation or the IGBT operation in accordance with the amount of collector current flowing in the device can be realized.
In the semiconductor device of the comparative example, each of the collector region 109 and the drain region 116 includes a plurality of sections separated from one another, and the sections of the collector region 109 and the sections of the drain region 116 are alternately arranged along the direction vertical to the direction extending from the collector region 109 toward the emitter/source region 108. In this manner, the length of the collector region 109 along the vertical direction (i.e., the direction along which the collector region 109 and the drain region 116 are arranged) can be reduced. Therefore, a collector voltage at which the MOSFET operation is changed to the IGBT operation (namely, a collector voltage (of, for example, approximately 1 V) at which the potential difference caused between the potential of the collector region and the potential of the portion of the resurf region surrounding the collector region becomes approximately 0.6 V through voltage drop) can be easily increased. Accordingly, more practical design can be attained by controlling a collector voltage at which the MOSFET operation is changed to the IGBT operation so as to, for example, increase the range of the collector voltage at which the MOSFET operation can be performed with high speed switching performance (namely, so as to design the device to perform the MOSFET operation with high speed switching performance until the collector voltage exceeds, for example, approximately 1 V). In other words, balance between the MOSFET operation with a good switching characteristic and the IGBT operation with low conducting resistance can be freely designed.
In the aforementioned semiconductor device of the comparative example performing the MOSFET operation or the IGBT operation, however, the following problem occurs during the IGBT operation.
The conductivity is modulated in an IGBT in the same manner as in a bipolar transistor, and hence, the conducting loss can be reduced. Therefore, as compared with a MOSFET with an equivalent chip size, the power loss can be reduced in the IGBT.
In the semiconductor device of the comparative example, however, since the collector region 109 is formed to have a much higher concentration than the top semiconductor layer 105 for reducing the on resistance, it takes longer time to draw excessive carriers remaining within the semiconductor substrate 101 at the time of turn off when an on state is switched to an off state. Therefore, the switching speed of the IGBT is lower than the switching speed of the MOSFET, and as a result, the switching loss is increased, which leads to a problem that the power loss cannot be sufficiently reduced.
In order to cope with such a problem, application of, for example, life time killing technique or the like may be employed for improving the switching speed of the IGBT. However, in this case, the cost is increased and the characteristic is degraded, and hence, this means cannot be a good way to solve the problem.
Moreover, in the semiconductor device of the comparative example, since the collector region 109 is formed to have a much higher concentration than the top semiconductor layer 105, it is necessary to provide an N-type buffer layer with a higher impurity concentration than the resurf region 102 between the collector region 109 and the resurf region 102 for reducing the efficiency for injecting holes from the collector region 109 to the resurf region 102. This increases the number of fabrication procedures and leads to another problem that the MOSFET operation is difficult to change to the IGBT operation.
In a semiconductor device according to Embodiment 2 of the invention described below, the problems of the semiconductor device of the comparative example can be solved without increasing the cost and degrading the characteristics.
The semiconductor device according to Embodiment 2 of the invention, that is, a high-breakdown voltage semiconductor switching device specifically, will now be described with reference to the accompanying drawings.
As shown in
In the base region 206, a contact region 210 of, for example, P+-type conductivity (with, for example, an impurity concentration of 1×1019/cm3 and a depth of 2 μm) and an emitter/source region 208 of, for example, N+-type conductivity (with, for example, an impurity concentration of 1×1020/cm3 and a depth of 0.5 μm) are formed to be spaced from the resurf region 202. Also, a gate insulating film 203 is formed so as to cover a portion of the base region 206 disposed between the emitter/source region 208 and the resurf region 202, and a gate electrode 207 is formed on the gate insulating film 203.
When the gate insulating film 203 is formed to extend over the emitter/source region 208, a short circuit between the gate electrode 207 and the emitter/source region 208 can be prevented.
Furthermore, a top semiconductor layer 205 of, for example, P-type conductivity (with, for example, an impurity concentration of 1×1016/cm3 and a depth of 1 μm) is formed in a surface portion of the resurf region 202. Although not shown in the drawing, the top semiconductor layer 205 is electrically connected to the base region 206 through a given portion of the resurf region 202, an upper layer interconnect or the like.
Also, a collector region 215 of, for example, P-type conductivity (with, for example, an impurity concentration of 1×1016/cm3 and a depth of 1 μm) is formed in a surface portion of the resurf region 202 to be spaced from the top semiconductor layer 205. At this point, the collector region 215 has substantially the same impurity concentration as and is disposed at substantially the same depth as the top semiconductor layer 205.
A collector contact region 209 of, for example, P+-type conductivity (with, for example, an impurity concentration of 1×1019/cm3 and a depth of 0.5 μm) is formed in a surface portion of the collector region 215. It is noted that the collector contact region 209 can be omitted.
Furthermore, a drain region 216 of, for example, N+-type conductivity (with, for example, an impurity concentration of 1×1020/cm3 and a depth of 0.5 μm) is formed in a surface portion of the resurf region 202 to be spaced from the top semiconductor layer 205.
At this point, each of the collector region 215 and the drain region 216 includes a plurality of sections separated from one another as shown in
An interlayer film 211 is formed above the semiconductor substrate 201 having the aforementioned various impurity regions and the like with a field insulating film 204 formed between the semiconductor substrate 201 including the resurf region 202 and the interlayer film 211.
Above the semiconductor substrate 201, a collector/drain electrode 212 penetrating the interlayer film 211 and electrically connected to both the collector contact region 209 (i.e., the collector region 215) and the drain region 216 is formed, and an emitter/source electrode 213 penetrating the interlayer film 211 and electrically connected to both the contact region 210 (i.e., the base region 206) and the emitter/source region 208 is formed.
A protective film 214 is formed on the interlayer film 211 on which the collector/drain electrode 212 and the emitter/source electrode 213 are formed.
In the semiconductor device of this embodiment, in the case where a positive voltage is applied to the gate electrode 207 with positive bias (hereinafter sometimes referred to as the collector voltage) applied between the collector/drain electrode 212 and the emitter/source electrode 213, an electron current (hereinafter sometimes referred to as the collector current) flows from the drain region 216 toward the emitter/source electrode 213, and thus, a MOSFET operation is performed. Furthermore, when the electron current, namely, the collector current, flowing toward the emitter/source electrode 213 is increased to some extent and a potential difference caused between the potential of the collector region 215 and the potential of a portion of the resurf region 202 surrounding the collector region 215 becomes approximately 0.6 V, holes are injected from the collector region 215 to the resurf region 202, and thus, the MOSFET operation is changed to an IGBT operation.
In this manner, in the semiconductor device of this embodiment, the MOSFET operation can be performed when the collector current flowing in the device is comparatively small, and the IGBT operation can be performed when the collector current flowing in the device is increased to some extent. In other words, a semiconductor device capable of performing the MOSFET operation or the IGBT operation in accordance with the amount of collector current flowing in the device can be realized. Furthermore, in the semiconductor device of this embodiment, the impurity concentration in the collector region 215 is set to be as low as the impurity concentration in the top semiconductor layer 205, and hence, as compared with the case where the collector region is made of a high concentration layer (a P+-type layer) (as in the comparative example), the amount of excessive carriers injected into the semiconductor substrate 201 including the resurf region 202 during the IGBT operation can be suppressed. As a result, the amount of excessive carriers remaining in the semiconductor substrate 201 in turn off can be reduced so as to shorten the time necessary for drawing the carriers. Therefore, the switching speed can be improved, so as to reduce the switching loss. In other words, a high-breakdown voltage semiconductor device in which the loss is reduced in the whole region ranging from light load to heavy load can be realized.
As shown in
As shown in
It is understood from the above-described measurement results shown in
Moreover, in the comparative example in which the collector region is made of the high concentration layer (the P+-type semiconductor layer), it is necessary to provide an N-type buffer layer with a higher impurity concentration than the resurf region between the collector region and the resurf region for reducing the efficiency for injecting holes from the collector region to the resurf region. On the contrary, since the collector region 215 is formed to have a low concentration in the semiconductor device of this embodiment, there is no need to provide such an N-type buffer layer, which can simplify the fabrication process. Furthermore, the problem of the comparative example that it is difficult to change the MOSFET operation to the IGBT operation because of the N-type buffer layer can be avoided.
In a fabrication method for the semiconductor device (the switching device) of this embodiment shown in
The semiconductor device according to Embodiment 3 of the invention, that is, a high-breakdown voltage semiconductor switching device specifically, will now be described with reference to the accompanying drawings.
As shown in
In the base region 206, a contact region 210 of, for example, P+-type conductivity (with, for example, an impurity concentration of 1×1019/cm3 and a depth of 2 μm) and an emitter/source region 208 of, for example, N+-type conductivity (with, for example, an impurity concentration of 1×1020/cm3 and a depth of 0.5 μm) are formed to be spaced from the resurf region 202. Also, a gate insulating film 203 is formed so as to cover a portion of the base region 206 disposed between the emitter/source region 208 and the resurf region 202, and a gate electrode 207 is formed on the gate insulating film 203.
When the gate insulating film 203 is formed to extend over the emitter/source region 208, a short circuit between the gate electrode 207 and the emitter/source region 208 can be prevented.
Furthermore, a buried semiconductor layer 217 of, for example, P-type conductivity (with, for example, an impurity concentration of 2×1016/cm3) is formed in the resurf region 202. The buried semiconductor layer 217 is formed at a depth of, for example, approximately 1 μm (corresponding to a depth Z of
Furthermore, a collector region 218 of, for example, P-type conductivity (with, for example, an impurity concentration of 2×1016/cm3) is formed in the resurf region 202 to be spaced from the buried semiconductor layer 217. At this point, the collector region 218 has substantially the same impurity concentration as and is disposed at substantially the same depth as the buried semiconductor layer 217. Moreover, a collector contact region 219 of, for example, P+-type conductivity (with, for example, an impurity concentration of 1×1019/cm3 and a depth of 1 μm) is formed in a surface portion of the resurf region 202 to be in contact with the collector region 218.
Furthermore, a drain region 216 of, for example, N+-type conductivity (with, for example, an impurity concentration of 1×1020/cm3 and a depth of 0.5 μm) is formed in a surface portion of the resurf region 202 to be spaced from the buried semiconductor layer 217.
At this point, each of the collector region 218 and the drain region 216 includes a plurality of sections separated from one another as shown in
An interlayer film 211 is formed above the semiconductor substrate 201 having the aforementioned various impurity regions or the like with a field insulating film 204 formed between the semiconductor substrate 201 including the resurf region 202 and the interlayer film 211.
Above the semiconductor substrate 201, a collector/drain electrode 212 penetrating the interlayer film 211 and electrically connected to both the collector contact region 219 (i.e., the collector region 218) and the drain region 216 is formed, and an emitter/source electrode 213 penetrating the interlayer film 211 and electrically connected to both the contact region 210 (i.e., the base region 206) and the emitter/source region 208 is formed.
A protective film 214 is formed on the interlayer film 211 on which the collector/drain electrode 212 and the emitter/source electrode 213 are formed.
In the semiconductor device of this embodiment, in the case where a positive voltage is applied to the gate electrode 207 with positive bias (hereinafter sometimes referred to as the collector voltage) applied between the collector/drain electrode 212 and the emitter/source electrode 213, an electron current (hereinafter sometimes referred to as the collector current) flows from the drain region 216 toward the emitter/source electrode 213, and thus, a MOSFET operation is performed. Furthermore, when the electron current, namely, the collector current, flowing toward the emitter/source electrode 213 is increased to some extent and a potential difference caused between the potential of the collector region 218 and the potential of a portion of the resurf region 202 surrounding the collector region 218 becomes approximately 0.6 V, holes are injected from the collector region 218 to the resurf region 202, and thus, the MOSFET operation is changed to an IGBT operation.
In this manner, in the semiconductor device of this embodiment, the MOSFET operation can be performed when the collector current flowing in the device is comparatively small, and the IGBT operation can be performed when the collector current flowing in the device is increased to some extent. In other words, a semiconductor device capable of performing the MOSFET operation or the IGBT operation in accordance with the amount of collector current flowing in the device can be realized. Furthermore, in the semiconductor device of this embodiment, the impurity concentration in the collector region 218 is set to be as low as the impurity concentration in the buried semiconductor layer 217, and hence, as compared with the case where the collector region is made of a high concentration layer (a P+-type layer) (as in the comparative example), the amount of excessive carriers injected into the semiconductor substrate 201 including the resurf region 202 during the IGBT operation can be suppressed. As a result, the amount of excessive carriers remaining in the semiconductor substrate 201 in turn off can be reduced so as to shorten the time necessary for drawing the carriers. Therefore, the switching speed can be improved, so as to reduce the switching loss. In other words, a high-breakdown voltage semiconductor device in which the loss is reduced in the whole region ranging from light load to heavy load can be realized.
Furthermore, in the semiconductor device (the switching device) of this embodiment in particular, the buried semiconductor layer 217 is formed in the resurf region 202, and therefore, a depletion layer can be formed to extend from the buried semiconductor layer to both the upward and downward directions. Accordingly, as compared with the case where the top semiconductor layer 205 is formed (as in Embodiment 2), the impurity concentration in the resurf region 202 can be made higher, so as to improve the switching speed and reduce the on resistance.
Also, in the comparative example in which the collector region is made of the high concentration layer (the P+-type semiconductor layer), it is necessary to provide an N-type buffer layer with a higher impurity concentration than the resurf region between the collector region and the resurf region for reducing the efficiency for injecting holes from the collector region to the resurf region. On the contrary, since the collector region 218 is formed to have a low concentration in the semiconductor device of this embodiment, there is no need to provide such an N-type buffer layer, which can simplify the fabrication process. Furthermore, the problem of the comparative example that it is difficult to change the MOSFET operation to the IGBT operation because of the N-type buffer layer can be avoided.
In this embodiment, the structure including the drain region 216, namely, the structure in which the MOSFET operation is changed to the IGBT operation, is described. As described in Embodiment 1, also in a structure not including the drain region 216, namely, a structure of a lateral type IGBT, the same effect as that of this embodiment, that is, the effect to reduce the loss in the whole region ranging from light load to heavy load, can be attained.
Now, an exemplified method for fabricating the switching device of this embodiment shown in
First, in a procedure shown in
Next, in a procedure shown in
Next, in a procedure shown in
Although not shown in the drawing, the buried semiconductor layer 217 is electrically connected to the base region 206.
It is noted that the order of performing ion implantation for forming the respective impurity regions of this embodiment is not particularly specified.
Next, in a procedure shown in
Then, in a procedure shown in
Next, in a procedure shown in
In the aforementioned fabrication method of this embodiment, since the buried semiconductor layer 217 and the collector region 218 are formed in one and the same impurity implantation process, the number of procedures can be reduced and the cost can be lowered as compared with the case they are individually formed.
A semiconductor device according to Embodiment 4 of the invention, that is, a high-breakdown voltage semiconductor switching device specifically, will now be described with reference to the accompanying drawings.
In the base region 206, a contact region 210 of, for example, P+-type conductivity (with, for example, an impurity concentration of 1×1019/cm3 and a depth of 2 μm) and an emitter region 208 of, for example, N+-type conductivity (with, for example, an impurity concentration of 1×1020/cm3 and a depth of 0.5 μm) are formed to be spaced from the resurf region 202. Also, a first gate insulating film 203 is formed so as to cover a portion of the base region 206 disposed between the emitter region 208 and the resurf region 202, and a first gate electrode 207 is formed on the first gate insulating film 203.
When the first gate insulating film 203 is formed to extend over the emitter region 208, a short circuit between the first gate electrode 207 and the emitter region 208 can be prevented.
Furthermore, a top semiconductor layer 205 of, for example, P-type conductivity (with, for example, an impurity concentration of 1×1016/cm3 and a depth of 1 μm) is formed in a surface portion of the resurf region 202. Although not shown in the drawing, the top semiconductor layer 205 is electrically connected to the base region 206 through a given portion of the resurf region 202, an upper layer interconnect or the like.
Also, a collector region 215 of, for example, P-type conductivity (with, for example, an impurity concentration of 1×1016/cm3 and a depth of 1 μm) is formed in a surface portion of the resurf region 202 to be spaced from the top semiconductor layer 205. At this point, the collector region 215 has substantially the same impurity concentration as and is disposed at substantially the same depth as the top semiconductor layer 205.
A collector contact region 209 of, for example, P+-type conductivity (with, for example, an impurity concentration of 1×1019/cm3 and a depth of 0.5 μm) is formed in a surface portion of the collector region 215. It is noted that the collector contact region 209 can be omitted.
Furthermore, a second gate insulating film 220 is formed on the resurf region 202 so as to extend from a portion on the collector region 215 to a portion on the top semiconductor layer 205. Also, a second gate electrode 221 is formed on a portion of the second gate insulating film 220 disposed between the collector region 215 and the top semiconductor layer 205. Although not shown in the drawing, the second gate electrode 221 is electrically connected to the first gate electrode 207 through a gate electrode interconnect, an upper layer interconnect or the like.
An interlayer film 211 is formed above the semiconductor substrate 201 having the aforementioned various impurity regions, gate electrodes and the like.
Above the semiconductor substrate 201, a collector electrode 212 penetrating the interlayer film 211 and electrically connected to the collector contact region 209 (i.e., the collector region 215) is formed, and an emitter electrode 213 penetrating the interlayer film 211 and electrically connected to both the contact region 210 (i.e., the base region 206) and the emitter region 208 is formed.
A protective film 214 is formed on the interlayer film 211 on which the collector electrode 212 and the emitter electrode 213 are formed.
In the semiconductor device of this embodiment, in the case where a positive voltage is applied to the first gate electrode 207 with positive bias applied between the collector electrode 212 and the emitter electrode 213 (with a side of the collector electrode 212 set to high potential), when a potential difference caused between the potential of the collector region 215 and the potential of a portion of the resurf region 202 surrounding the collector region 215 becomes approximately 0.6 V, holes are injected from the collector region 215 to the resurf region 202, and thus, an IGBT operation is started. Specifically, the semiconductor device (the switching device) of this embodiment is a lateral type IGBT.
In the semiconductor device (the switching device) of this embodiment, at the time of turn off of the switching device (namely, when the voltages of the first gate electrode 207 and the second gate electrode 221 are both lowered from, for example, 6 V to 0 V assuming that the voltage of the emitter electrode 213 is 0 V), the potential of a portion of the resurf region 202 disposed between the collector region 215 and the top semiconductor layer 205 (hereinafter sometimes referred to as the collector potential) is also increased, and hence, a P-channel MOSFET formed by using a part of the collector region 215 is turned on. Thus, excessive carriers remaining in the resurf region 202 can be drawn through a path extending from the collector region 215 and passing through the P-channel MOSFET, the top semiconductor layer 205, the base region 206 and the contact region 210. In addition, the excessive carriers remaining in the resurf region 202 can be drawn also through the top semiconductor layer 205. Therefore, the fall time tf can be shortened, namely, the switching speed can be improved by reducing the time required for drawing the carriers, and hence, the switching loss can be reduced.
In this embodiment, the excessive carriers (holes) remaining in the resurf region 202 are drawn by increasing the collector potential in turn off, and thereafter, a hole current passing through the path including the P-channel MOSFET from the collector electrode 212 can be stopped since a depletion layer extends from the top semiconductor layer 205 in the resurf region 202. Accordingly, the breakdown voltage characteristic of the device is never degraded.
Also, in the semiconductor device of this embodiment, the impurity concentration in the collector region 215 is set to be as low as the impurity concentration in the top semiconductor layer 205, and hence, as compared with the case where the collector region is made of a high concentration layer (a P+-type layer), the amount of excessive carriers injected into the semiconductor substrate 201 including the resurf region 202 during the IGBT operation can be suppressed. As a result, since the amount of excessive carriers remaining in the semiconductor substrate 201 in turn off can be reduced, the time necessary for drawing the carriers can be shortened. Therefore, the switching speed can be improved, so as to reduce the switching loss. Specifically, a high-breakdown voltage semiconductor device in which the loss can be reduced in the whole region ranging from light load to heavy load can be realized.
Moreover, in the case where the collector region is made of a high concentration layer, it is necessary to provide a buffer layer of, for example, N-type conductivity with a higher impurity concentration than the resurf region between the collector region and the resurf region for reducing the efficiency for injecting holes from the collector region to the resurf region. On the contrary, since the collector region 215 is formed to have a low concentration in the semiconductor device of this embodiment, there is no need to provide such an N-type buffer layer, and hence, the fabrication process can be simplified.
Although a structure in which a drain region is not formed, namely, a structure in which a MOSFET operation is not changed to an IGBT operation, is described in this embodiment, the same effect as that of this embodiment, namely, the effect to reduce the loss in the whole region ranging from light load to heavy load, can be attained also when a drain region is provided as described in Embodiment 2 or 3. Also in this case, each of the collector region 215 and the drain region may include a plurality of sections separated from one another, and the sections of the collector region 215 and the sections of the drain region may be alternately arranged along a direction vertical to a direction extending from the collector region 215 toward the emitter region 208 (the emitter/source region in this case).
Now, an exemplified method for fabricating the switching device of this embodiment shown in
First, in a procedure shown in
Next, in a procedure shown in
It is noted that the top semiconductor layer 205 is electrically connected to a base region 206 described below although not shown in the drawing.
Then, in a procedure shown in
It is noted that the order of performing ion implantation for forming the respective impurity regions of this embodiment is not particularly specified.
Next, in a procedure shown in
Then, in a procedure shown in
Next, in a procedure shown in
In the fabrication method of this embodiment described above, the top semiconductor layer 205 and the collector region 215 are formed in one and the same impurity implantation process, and therefore, the number of procedures can be reduced and the cost can be lowered as compared with the case where they are individually formed.
A semiconductor device according to Embodiment 5 of the invention, that is, a high-breakdown voltage semiconductor switching device specifically, will now be described with reference to the accompanying drawings.
In the base region 206, a contact region 210 of, for example, P+-type conductivity (with, for example, an impurity concentration of 1×1019/cm3 and a depth of 2 μm) and an emitter region 208 of, for example, N+-type conductivity (with, for example, an impurity concentration of 1×1020/cm3 and a depth of 0.5 μm) are formed to be spaced from the resurf region 202. Also, a first gate insulating film 203 is formed so as to cover a portion of the base region 206 disposed between the emitter region 208 and the resurf region 202, and a first gate electrode 207 is formed on the first gate insulating film 203.
When the first gate insulating film 203 is formed to extend over the emitter region 208, a short circuit between the first gate electrode 207 and the emitter region 208 can be prevented.
Furthermore, a top semiconductor layer 222 of, for example, P-type conductivity (with, for example, an impurity concentration of 1×1016/cm3 and a depth of 1 μm) is formed in a surface portion of the resurf region 202.
Also, a buried semiconductor layer 217 of, for example, P-type conductivity (with, for example, an impurity concentration of 2×1016/cm3) is formed in the resurf region 202 beneath the top semiconductor layer 222 so as to be in contact with the top semiconductor layer 222. The buried semiconductor layer 217 is formed at a depth of, for example, approximately 1 μm from the top face of the substrate 201 in a width along the depth direction of, for example, approximately 1 μm. Although not shown in the drawing, the buried semiconductor layer 217 is electrically connected to the base region 206 through a given portion of the resurf region 202, an upper layer interconnect or the like. In other words, the top semiconductor layer 222 and the base region 206 are electrically connected to each other through the buried semiconductor layer 217.
Furthermore, a collector region 215 of, for example, P-type conductivity (with, for example, an impurity concentration of 1×1016/cm3 and a depth of 1 μm) is formed in a surface portion of the resurf region 202 to be spaced from the top semiconductor layer 222. At this point, the collector region 215 has substantially the same impurity concentration as and is disposed at substantially the same depth as the top semiconductor layer 222.
While the buried semiconductor layer 217 is formed in the resurf region 202 so as to extend from the vicinity of the collector region 215 to the vicinity of the base region 206, the top semiconductor layer 222 is formed in the resurf region 202 merely in the vicinity of the collector region 215. Also, the top semiconductor layer 222 includes a plurality of sections separated from one another arranged in a direction vertical to a direction extending from the collector region 215 toward the base region 206. This is for securing a path for drawing carriers described below.
A collector contact region 209 of, for example, P+-type conductivity (with, for example, an impurity concentration of 1×1019/cm3 and a depth of 0.5 μm) is formed in a surface portion of the collector region 215. It is noted that the collector contact region 209 can be omitted.
Furthermore, a second gate insulating film 220 is formed above the resurf region 202 so as to extend from a portion on the collector region 215 at least to a portion on the top semiconductor layer 222. Also, a second gate electrode 221 is formed on a portion of the second gate insulating film 220 disposed between the collector region 215 and the top semiconductor layer 222. Although not shown in the drawing, the second gate electrode 221 is electrically connected to the first gate electrode 207 through a gate electrode interconnect, an upper layer interconnect or the like.
An interlayer film 211 is formed above the semiconductor substrate 201 having the aforementioned various impurity regions, gate electrodes and the like.
Above the semiconductor substrate 201, a collector electrode 212 penetrating the interlayer film 211 and electrically connected to the collector contact region 209 (i.e., the collector region 215) is formed, and an emitter electrode 213 penetrating the interlayer film 211 and electrically connected to both the contact region 210 (i.e., the base region 206) and the emitter region 208 is formed.
A protective film 214 is formed on the interlayer film 211 on which the collector electrode 212 and the emitter electrode 213 are formed.
The operation of the semiconductor device of this embodiment is basically the same as that of Embodiment 4. Specifically, in the case where a positive voltage is applied to the first gate electrode 207 with positive bias applied between the collector electrode 212 and the emitter electrode 213 (with a side of the collector electrode 212 set to high potential), when a potential difference caused between the potential of the collector region 215 and the potential of a portion of the resurf region 202 surrounding the collector region 215 becomes approximately 0.6 V, holes are injected from the collector region 215 to the resurf region 202, and thus, an IGBT operation is started. Specifically, the semiconductor device (the switching device) of this embodiment is a lateral type IGBT.
In the semiconductor device (the switching device) of this embodiment, at the time of turn off of the switching device (namely, when the voltages of the first gate electrode 207 and the second gate electrode 221 are both lowered from, for example, 6 V to 0 V assuming that the voltage of the emitter electrode 213 is 0 V), the potential of a portion of the resurf region 202 disposed between the collector region 215 and the top semiconductor layer 222 (hereinafter sometimes referred to as the collector potential) is also increased, and hence, a P-channel MOSFET formed by using a part of the collector region 215 is turned on. Thus, excessive carriers remaining in the resurf region 202 can be drawn through a path extending from the collector region 215 and passing through the P-channel MOSFET, the top semiconductor layer 222, the buried semiconductor layer 217, the base region 206 and the contact region 210. In addition, the excessive carriers remaining in the resurf region 202 can be drawn also through the top semiconductor layer 222 and the buried semiconductor layer 217. Therefore, the fall time tf can be shortened, namely, the switching speed can be improved by reducing the time required for drawing the carriers, and hence, the switching loss can be reduced.
In this embodiment, the excessive carriers (holes) remaining in the resurf region 202 are drawn by increasing the collector potential in turn off, and thereafter, a hole current passing through the path including the P-channel MOSFET from the collector electrode 212 can be stopped since a depletion layer extends from the top semiconductor layer 222 and the buried semiconductor layer 217 in the resurf region 202. Accordingly, the breakdown voltage characteristic of the device is never degraded.
Also, in the semiconductor device of this embodiment, the impurity concentration in the collector region 215 is set to be as low as the impurity concentration in the top semiconductor layer 222, and hence, as compared with the case where the collector region is made of a high concentration layer (a P+-type layer), the amount of excessive carriers injected into the semiconductor substrate 201 including the resurf region 202 during the IGBT operation can be suppressed. As a result, since the amount of excessive carriers remaining in the semiconductor substrate 201 in turn off can be reduced, the time necessary for drawing the carriers can be shortened. Therefore, the switching speed can be improved, so as to reduce the switching loss. Specifically, a high-breakdown voltage semiconductor device in which the loss can be reduced in the whole region ranging from light load to heavy load can be realized.
Moreover, in the case where the collector region is made of a high concentration layer, it is necessary to provide a buffer layer of, for example, N-type conductivity with a higher impurity concentration than the resurf region between the collector region and the resurf region for reducing the efficiency for injecting holes from the collector region to the resurf region. On the contrary, since the collector region 215 is formed to have a low concentration in the semiconductor device of this embodiment, there is no need to provide such an N-type buffer layer, and hence, the fabrication process can be simplified.
Furthermore, since the buried semiconductor layer 217 is additionally formed in the resurf region 202 in the semiconductor device of this embodiment, a depletion layer can be formed to extend in both the upward and downward directions from the buried semiconductor layer 217 as compared with the case where the top semiconductor layer 205 alone is formed in the resurf region 202 (as in Embodiment 4). Therefore, the impurity concentration in the resurf region 202 can be further increased, so as to improve the switching speed and reduce the on resistance.
Although a structure in which a drain region is not formed, namely, a structure in which a MOSFET operation is not changed to an IGBT operation, is described in this embodiment, the same effect as that of this embodiment, namely, the effect to reduce the loss in the whole region ranging from light load to heavy load, can be attained also when a drain region is provided as described in Embodiment 2 or 3. Also in this case, each of the collector region 215 and the drain region may include a plurality of sections separated from one another, and the sections of the collector region 215 and the sections of the drain region may be alternately arranged along a direction vertical to a direction extending from the collector region 215 toward the emitter region 208 (the emitter/source region in this case).
Now, an exemplified method for fabricating the switching device of this embodiment shown in
First, in a procedure shown in
Next, in a procedure shown in
Then, in a procedure shown in
Thereafter, a buried semiconductor layer 217 of, for example, P-type conductivity is selectively formed in the resurf region 202 beneath the top semiconductor layer 222 by, for example, high-energy boron ion implantation, so as to be in contact with the top semiconductor layer 222. The impurity concentration in the buried semiconductor layer 217 is, for example, approximately 2×1016/cm3. Also, the buried semiconductor layer 217 is formed at a depth of, for example, approximately 1 μm from the top face of the substrate 201 in a width along the depth direction of, for example, approximately 1 μm. Although not shown in the drawing, the buried semiconductor layer 217 is electrically connected to the base region 206.
It is noted that the order of performing ion implantation for forming the respective impurity regions of this embodiment is not particularly specified.
Next, in a procedure shown in
Then, in a procedure shown in
Next, in a procedure shown in
In the fabrication method of this embodiment described above, the top semiconductor layer 222 and the collector region 215 are formed in one and the same impurity implantation process, and therefore, the number of procedures can be reduced and the cost can be lowered as compared with the case where they are individually formed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-282440 | Oct 2006 | JP | national |
| 2007-110782 | Apr 2007 | JP | national |
