Patent Application
20210151664
The invention relates to a semiconductor device and method for fabricating the same, and more particularly to a magnetoresistive random access memory (MRAM) and method for fabricating the same.
Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices, which typically has the advantage of keeping stored data even when the device is not connected to an electrical source.
The aforementioned MR effect has also been used in magnetic field sensor areas including but not limited to for example electronic compass components used in global positioning system (GPS) of cellular phones for providing information regarding moving location to users. Currently, various magnetic field sensor technologies such as anisotropic magnetoresistance (AMR) sensors, GMR sensors, magnetic tunneling junction (MTJ) sensors have been widely developed in the market. Nevertheless, most of these products still pose numerous shortcomings such as high chip area, high cost, high power consumption, limited sensibility, and easily affected by temperature variation and how to come up with an improved device to resolve these issues has become an important task in this field.
According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.
According to another aspect of the present invention, a semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, an inter-metal dielectric (IMD) layer on the substrate and around the MTJ, and a top electrode on the MTJ. Preferably, a top view of the MTJ comprises at least one corner and the at least one corner is less than 90 degrees.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Referring to
Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer could also be formed on top of the substrate 12. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate 12, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain region, spacer, epitaxial layer, and contact etch stop layer (CESL). The ILD layer could be formed on the substrate 12 to cover the MOS transistors, and a plurality of contact plugs could be formed in the ILD layer to electrically connect to the gate structure and/or source/drain region of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.
Next, metal interconnect structure 16 is formed on the ILD layer on the MTJ region 14 and the logic region to electrically connect the aforementioned contact plugs, in which the metal interconnect structure 16 includes an inter-metal dielectric (IMD) layer 18 and metal interconnections 20 embedded in the IMD layer 18. In this embodiment, each of the metal interconnections 20 from the metal interconnect structure 16 preferably includes a via conductor, and each of the metal interconnections 20 could be interconnected within the IMD layer 18 according to a single damascene process or dual damascene process. For instance, each of the metal interconnections 20 could further include a barrier layer and a metal layer, in which the barrier layer could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. In this embodiment, the IMD layer 18 is preferably made of silicon oxide or ultra low-k (ULK) dielectric material and the metal interconnections 20 are preferably made of tungsten, but not limited thereto.
Next, a bottom electrode 22 is formed on the surface of the IMD layer 18, a MTJ stack 24 made of a pinned layer, a barrier layer, and a free layer are formed on the bottom electrode 22, and a top electrode 28 and a hard mask 30 are formed on the MTJ stack thereafter. It should be noted that since none of the above layers are patterned at this stage, the top view of the hard mask 30 shown on bottom portion of
In this embodiment, the bottom electrode 22 and the top electrode 28 are preferably made of conductive material including but not limited to for example Ta, Pt, Cu, Au, Al, or combination thereof. The pinned layer could be made of antiferromagnetic (AFM) material including but not limited to for example ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), or combination thereof, in which the pinned layer is formed to fix or limit the direction of magnetic moment of adjacent layers. The barrier layer could be made of insulating material including but not limited to for example oxides such as aluminum oxide (AlOx) or magnesium oxide (MgO). The free layer could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), in which the magnetized direction of the free layer could be altered freely depending on the influence of outside magnetic field. Preferably, the stop layer 26 could be made of any material having etching selectivity with the top electrode 28 such as silicon oxide or silicon nitride and the hard mask 30 is preferably made of silicon nitride.
Next, as shown in
Next, as shown in
Next, as shown in
Referring to
Viewing from a more detailed perspective, the top view of each of the top electrodes 28 could include a quadrilateral having four corners 58, 60, 62, 64, in which at least one corner 58 from the four corners could be less than 90 degrees, each of at least two corners 58, 60 could be less than 90 degrees, each of at least three corners 58, 60, 62 could be less than 90 degrees, or each of the four corners 58, 60, 62, 64 could be less than 90 degrees. Preferably, the quadrilateral includes a first side 42 and a second side 44 extending along a first direction such as Y-direction, a third side 46 connecting the first side 42 and the second side 44, and a fourth side 48 connecting the first side 42 and the second side 44, in which each of the third side 46 and the fourth side 48 includes a curve or more specifically a concave curve.
Referring to
In this embodiment, the top view of each of the top electrodes 28 could include a hexagon having at least four corners 66, 68, 70, 72, in which at least one corner 66 from the four corners could be less than 90 degrees, each of at least two corners 66, 68 could be less than 90 degrees, each of at least three corners 66, 68, 70 could be less than 90 degrees, or each of the four corners 66, 68, 70, 72 could be less than 90 degrees. Preferably, the hexagon includes a first side 50 and a second side 52 extending along a first direction such as Y-direction, a third side 54 connecting the first side 50 and the second side 52, and a fourth side 56 connecting the first side 50 and the second side 52, in which each of the third side 54 and the fourth side 56 includes a V-shape.
Overall, the present invention preferably employs a double patterning and double etching (2P2E) approach to pattern the MTJ stack into a plurality of MTJs, in which the double patterning and double etching process could be accomplished by first conducting a first patterning process along a first direction to remove part of the top electrode, conducting a first stage etching process of the second patterning process along a second direction to remove part of the hard mask and part of the top electrode, and then conducting a second stage etching process of the second patterning process to remove part of the MTJ stack and part of the bottom electrode to form a plurality of MTJs. By using the aforementioned 2P2E approach to form the MTJs it would not only be desirable to obtain the top view outlines shown in
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201911117619.X | Nov 2019 | CN | national |
