Patent Grant
7316959
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically a semiconductor device which can increase the carrier mobility while suppressing the short channel effect, and a method for fabricating the semiconductor device.
Recently, to realize high speed and micronization of MOSFETs it is noted to use SOI (Silicon On Insulator) substrates.
A proposed semiconductor device using an SOI substrate will be explained with reference to
As shown in
In the proposed semiconductor device using the SOI substrate, because of the insulation film 112 formed between the lower surface of the source/drain diffused layer 124 and the silicon substrate 110, a parasitic capacitance between the source/drain diffused layer 124 and the silicon substrate 110 can be small. The SOI substrate permits the source/drain diffused layer to be formed by shallow junction.
Then, recently, the semiconductor device is increasingly micronized. As the semiconductor devices are more micronized, the semiconductor layer 114 is increasingly thinned so as to prevent the short channel effect.
However, as the semiconductor layer 114 is increasingly thinned, the carrier surface scattering and the phonon scattering are increased in the interface between the semiconductor layer 114 and the buried diffused layer 112, which lower a carrier mobility (Reference: The division of the Japan Society of Applied Physics, Silicon Technology, No. 35, 22th Jan. 2002, pp. 88-93). The decrease of the carrier mobility has been a barrier to higher speed of the semiconductor device.
An object of the present invention is to provide a semiconductor device which can increase the carrier mobility while suppressing the short channel effect, and a method for fabricating the semiconductor device.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor layer formed on an insulation layer; a gate electrode formed on the semiconductor layer with a gate insulation film formed therebetween; a source/drain region formed in the semiconductor layer on both sides of the gate electrode; and a semiconductor region buried in the insulation layer in a region below the gate electrode.
According to another aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming a mask on a first semiconductor layer formed on a substrate; oxidizing the first semiconductor layer on both sides of the mask to thereby form the first semiconductor layer outside the mask into an insulation film; forming a second semiconductor layer on the first semiconductor layer and the insulation layer; forming a gate insulation film on the second semiconductor layer on the second semiconductor layer; forming a gate electrode on the gate insulation film; and forming a source/drain region in the second semiconductor layer on both sides of the gate electrode.
The present invention can prevent the surface scattering of carriers and the phonon scattering while suppressing the short channel effect. Thus, the present invention can provide a semiconductor device having high mobility and high speed.
The semiconductor device according to a first embodiment of the present invention and a method for fabricating the semiconductor device will be explained with reference to
(The Semiconductor Device)
First, the semiconductor device according to the present embodiment will be explained with reference to
As shown in
On the insulation film 12, a semiconductor region 14 of, e.g., a 20 nm-thickness p type Si. The semiconductor region 14 is single crystallized.
An insulation film 16 of SiO2 is formed on both sides of the semiconductor region 14. The insulation layer 16 is formed by oxidizing a semiconductor layer.
In the present embodiment, an SOI substrate 8 is used. The substrate 10 is the base substrate of the SOI substrate 8. The insulation layer 12 is a buried oxide film (BOX, Buried OXide) of the SOI substrate 8. The semiconductor region 14 is a part of an Si layer formed on the buried oxide film of the SOI substrate 8.
A 10 nm-thickness semiconductor layer 18 of intrinsic Si is formed on the semiconductor region 14 and the insulation layer 16. The semiconductor layer 18 is epitaxially grown on the semiconductor region 14.
A gate electrode 22 of polysilicon is formed on the semiconductor layer 18 with a gate insulation film 20 of, e.g., below 2 nm-thickness SiO2 therebetween.
A sidewall insulation film 23 of, e.g., SiO2 is formed on the side wall of the gate electrode 22.
A source/drain region 24 of Pt silicide is formed on the semiconductor layer 18 on both sides of the gate electrode 22.
In the present embodiment, the source/drain region 24 is formed of Pt silicide but is not essentially formed of Pt silicide. The source/drain region 24 may be formed of, e.g., Er silicide, Ti silicide, W silicide, Co silicide, Ni silicide, Gd silicide, Pd silicide or others, or silicides of other metals.
A metal silicide film 26 of Pt silicide is formed on the gate electrode 22.
Source/drain electrodes 28 are formed respectively on the source/drain region 24.
Thus, the semiconductor device according to the present embodiment is constituted.
The semiconductor device according to the present embodiment is characterized mainly in that the semiconductor region 14 is formed below the semiconductor layer 18, and the insulation layer 16 is formed below the source/drain region 24, i.e., on both sides of the semiconductor region 14.
In the proposed semiconductor device shown in
In contrast to this, according to the present embodiment, because of the semiconductor region 14 formed below the semiconductor layer 18, the energy band structure shown in
As shown in
Furthermore, according to the present embodiment, the insulation film 16 is formed below the source/drain region 24, i.e., on both sides of the semiconductor region 14, where by radial extension of electric fields from the source/drain region 24 can be prevented. Thus, according to the present embodiment, the short channel effect can be prevented.
As described above, according to the present embodiment, the surface scattering of the carriers and phonon scattering can be prevented while suppressing the short channel effect. Resultantly the semiconductor device can have high mobility and high speed.
The semiconductor device according to the present embodiment is called a channel barrier (CB) MOSFET for confining the carriers in the semiconductor layer 18 by the potential barrier.
(The Method for Fabricating the Semiconductor Device)
Then, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to
First, as shown in
Then, an SiN film is formed on the entire surface by, e.g., sputtering. Then, the SiN film is patterned by photolithography. Thus, as shown in
Then, as shown in
Next, as shown in
Then, boron, a p type dopant is implanted in the semiconductor region 14 by ion implantation. Thus, the semiconductor region 14 has p type conduction.
Next, as shown in
Then, as shown in
Then, the gate insulation film 20 of an SiO2 film of, e.g., 2 nm-thickness on the entire surface by thermal oxidation.
Next, a polysilicon film of, e.g., a 180 nm-thickness is formed on the entire surface by CVD. Then, the polysilicon film is patterned by photolithography. Thus, the gate electrode 22 of polysilicon is formed.
Next, an SiO2 film of, e.g., a 150 nm-thickness is formed on the entire surface by, e.g., CVD. Next, the SiO2 film is anisotropically etched to thereby form the sidewall insulation film 23 of SiO2 on the side wall of the gate electrode 22 (see
Then, as shown in
Then, the semiconductor layer 18 on both sides of the gate electrode 20 is silicided by thermal processing. Thus, the source/drain region 24 of Pt silicide is formed. Then, the unreacted metal film 36 is etched. Thus, the source/drain region 24 of Pt silicide is formed on the semiconductor layer 18 on both sides of the gate electrode 22 (see
Then, as shown in
Thus, the semiconductor device according tot he present embodiment is fabricated.
(Modification 1)
Modification 1 of the semiconductor device according to the present embodiment will be explained with reference to
The semiconductor device according to the present embodiment is characterized mainly in that a source/drain region 24a of a metal is buried in a semiconductor layer 18 on both sides of a gate electrode 22.
As shown in
In the present modification, the source/drain region 24a is formed of Pt but is not essentially formed of Pt. The source/drain region 24a may be formed of, e.g., Er, Ti, W, Co, Ni, Gd, Pd or other metals.
Thus, the semiconductor device according to the present modification is constituted.
Next, the method for fabricating the semiconductor device according to the present modification will be explained with reference to
First, the steps up to the step of forming the sidewall insulation film 23 including the sidewall insulation film step are the same as those of the method for fabricating the semiconductor device shown in
Next, a resist film 38 is formed on the entire surface. Next, openings 40 are formed in the resist film 38 down to the conductor layer 18 by photolithography (see
Then, as shown in
Next, as shown in
Then, as shown in
Thus, the semiconductor device according to the present modification is fabricated.
(Modification 2)
Next, Modification 2 of the semiconductor device according to the present embodiment will be explained with reference to
The semiconductor device according to the present modification is characterized mainly in that a dopant is implanted in the semiconductor layer 18 on both sides of the gate electrode 22 by ion implantation to form the source/drain diffused layer 24b.
As shown in
Metal silicide films 26, 28a are formed respectively on the gate electrode 22 and the source/drain diffused layer 24b.
Thus, the semiconductor device according to the present modification is constituted.
Then, the method for fabricating the semiconductor device according to the present modification will be explained with reference to
First, the steps up to the step of forming the sidewall insulation film 23 including the sidewall insulation film forming step are the same as those of the method for fabricating the semiconductor device shown in
Then, a dopant is implanted in the semiconductor layer 18 by, e.g., ion implantation by self alignment with the gate electrode 22 with the sidewall insulation film 23 formed on. The source/drain diffused layer 24b is also formed on both sides of the gate electrode 22.
Then, a metal silicide film 28 is formed on the gate electrode 22 and the source/drain diffused layer 24b over the entire surface by SALICIDE (Self-Aligned Silicide) process.
That is, first, a metal film of, Ti, Co or Ni is deposited on the entire surface by, e.g., vapor deposition. Then, acetal silicide film is formed on the expose gate electrode 22 and the source/drain diffused layer 24b by self-alignment at low temperature by RTA (Rapid Thermal Anneal). Then, the unreacted metal film is etched by wet etching, RIE (Reactive Ion Etching) or ion milling. Then, thermal processing is performed by RTA to improve the film quality of the metal silicide film. Thus, the metal silicide film 26, 28a are formed respectively on the gate electrode 22 and the source/drain region 24b by SALICIDE process (see
Thus, the semiconductor device according to the present modification is fabricated.
(Modification 3)
Next, Modification 3 of the semiconductor device according to the present embodiment will be explained with reference to
The semiconductor device according to the present modification is characterized mainly in that a semiconductor region 14a of intrinsic Si is formed below a semiconductor layer 18 of intrinsic Si.
In the semiconductor device shown in
In the present modification, the semiconductor region 14a of intrinsic Si is formed below the semiconductor layer 18 of intrinsic Si, whereby the energy band structure shown in
However, in the present modification, the semiconductor region 14a of intrinsic Si is formed below the semiconductor layer 18 of intrinsic Si, whereby a total film thickness of the semiconductor layers below the gate electrode 22 is larger than that of the semiconductor layer 18 alone forming the channel layer. That is, in the present modification, the surface scattering of the carriers and the phonon scattering can be depressed almost as much as in a semiconductor device having the channel layer formed of a thick semiconductor layer.
Furthermore, generally the short channel effect tends to occur in a semiconductor device having the channel layer formed of a thick semiconductor layer. However, in the present modification, because of the insulation layer 16 formed on both sides of the semiconductor region 14a, i.e., below the source/drain region 24, the short channel effect can be suppressed.
Accordingly, the semiconductor device according to the present modification can have high mobility and high speed while suppressing the short channel effect.
(Modification 4)
Then, Modification 4 of the semiconductor device according to the present embodiment will be explained with reference to
The semiconductor device according to the present embodiment is characterized mainly in that a semiconductor region 14b of p type SiGe is formed below a semiconductor layer 18a of intrinsic SiGe.
As shown in
The substrate 10a is the base substrate of an SiGeOI (SiGe On Insulator) substrate 8a. An insulation layer 12 is a buried oxide film of the SiGeOI substrate 8a. The semiconductor region 14b is a SiGe layer formed on the buried oxide film of the SiGeOI substrate 8a. The SiGeOI substrate is a substrate comprising a semiconductor layer of SiGe formed on a buried oxide film formed on a base substrate.
In the semiconductor device according to the present modification, the semiconductor region 14b of p type SiGe is formed below the semiconductor layer 18a of intrinsic SiGe, whereby the carriers can be confined in the semiconductor layer 18a, as can be in the semiconductor device shown in
Thus, the semiconductor device according to the present modification can prevent the surface scattering of carriers and phonon scattering while suppressing the short channel effect, and resultantly, can have high mobility and high speed.
(Modification 5)
Next, Modification 5 of the semiconductor device according to the present embodiment will be explained with reference to
The semiconductor device according to the present modification is characterized mainly in that a semiconductor region 14c of intrinsic SiGe is formed below a semiconductor layer 18a of intrinsic SiGe.
In the semiconductor device shown in
In the present modification, however, the semiconductor region 14b of intrinsic SiGe is formed below the semiconductor layer 18a of intrinsic SiGe, whereby the energy band structure shown in
As seen in
However, as can the semiconductor device shown in
Furthermore, as described above, generally the short channel effect tends to occur in a semiconductor device having the channel layer formed of a thick semiconductor layer. However, in the present modification, because of the insulation layer 16 formed on both sides of the semiconductor region 14b, i.e., below the source/drain region 24, the short channel effect can be suppressed.
Accordingly, the semiconductor device according to the present modification can have high mobility and high speed while suppressing the short channel effect.
The semiconductor device according to a second embodiment of the present invention will be explained with reference to
The semiconductor device according to the present modification is characterized mainly in that a semiconductor region 14a of Si is formed below the semiconductor layer 18a of SiGe.
As shown in
Because of the lattice constant different between SiGe and Si, when the semiconductor layer 18a of SiGe is grown on the semiconductor region 14a of Si, the semiconductor layer 18a of SiGe is strained. Specifically, because the lattice constant of SiGe is larger than that of Si, compression strains are applied to the semiconductor layer 18a of SiGe. When strains are applied to the semiconductor layer 18a of SiGe, a mobility of the electrons and holes is improved.
Thus, the semiconductor device according to the present embodiment can realize further mobility increase.
In the semiconductor device according to the present embodiment, because of the semiconductor region 14a of Si formed below the semiconductor layer 18a of SiGe, the energy band structure is as shown in
As seen in
According to the present embodiment, because the semiconductor layer 18a of SiGe functions as a quantum well for either of the electrons and holes, either of a p-channel MOSFET and an n-channel MOSFET can be formed.
As described above, according to the present embodiment, because of the semiconductor layer 18a of SiGe formed on the semiconductor region 14a of Si, strains are applied to the semiconductor layer 18a of SiGe. Thus, the semiconductor device according to the present embodiment can have higher mobility.
The semiconductor layer 18a of SiGe functions as a quantum well for either of the electrons and the holes. Thus, the semiconductor device according to the present embodiment can include either of p-channel MOSFETs and n-channel MOSFETs.
(A Modification)
Next, a modification of the semiconductor device according to the present embodiment will be explained with reference to
The semiconductor device according to the present modification is characterized mainly in that a semiconductor region 14c of SiGe is formed below a semiconductor layer 18 of Si.
As shown in
Si has the lattice constant, which is different from that of SiGe, and when the semiconductor layer 18 of Si grown on the semiconductor region 14c of SiGe, strains are applied to the semiconductor layer 18 of Si. Specifically, because of the lattice constant of Si, which is smaller than that of SiGe, tensile stresses are applied to the semiconductor layer 18 of Si. When such strains are applied to the semiconductor layer 18 of Si, a mobility of the electrons and the holes in the semiconductor layer 18 of Si is increased.
Thus, according to the present modification, further improvement of the mobility can be realized.
In the semiconductor device according to the present modification, because of the semiconductor region 14c of SiGe formed below the channel layer 18 of Si, an energy band structure is as shown in
As seen in
In the present modification, the semiconductor layer 18 of Si functions as a quantum well for the electrons. On the other hand, the semiconductor region 14c of SiGe functions as a quantum well for the holes.
As described above, according to the present modification, because of the semiconductor layer 18 of Si formed on the semiconductor region 14c of SiGe, strains are applied to the semiconductor layer 18 of Si. Thus, the semiconductor device according to the present modification can realize further mobility increase.
The semiconductor device according to a third embodiment of the present invention and the method for fabricating the semiconductor device will be explained with reference to
(The Semiconductor Device)
First, the semiconductor device according to the present embodiment will be explained with reference to
The semiconductor device according to the present embodiment is characterized mainly in that a semiconductor region 14a of Si is formed below a semiconductor layer 18a of SiGe, and a semiconductor layer 32 of Si is further formed on the semiconductor layer 18a of SiGe.
As shown in
The semiconductor layer 32 of intrinsic SiGe is formed on the semiconductor layer 18a of Si. A composition of the semiconductor layer 32 is, e.g., Si0.5Ge0.5.
In the semiconductor device according to the present embodiment, the semiconductor region 14a of Si is formed below the semiconductor layer 18a of SiGe, and the semiconductor layer 32 of Si is formed on the semiconductor layer 18a of SiGe, whereby the energy band structure is as shown in
As seen in
In the present embodiment, a p-channel is formed in the semiconductor 18a of SiGe. On the other hand, an n-channel is formed in the semiconductor layer 32 of Si.
The semiconductor device according to the present embodiment can form a p-channel in the semiconductor layer 18a, and an n-channel in the semiconductor layer 32 and is called a heterochannel CBMOSFET (Channel Barrier MOSFET).
Furthermore, in the semiconductor device according to the present embodiment, the semiconductor layer 32 of Si is formed between the semiconductor layer 18a of SiGe and a gate insulation film 20, whereby the carriers can be confined in a region paced from the interface with the gate insulation film 20.
In the semiconductor device according to the first and the second embodiments, the carriers can be confined in a region spaced from the buried oxide film 12 but cannot confine the carriers in the region spaced form the interface with the gate insulation film 20. Accordingly, in the semiconductor device according to the first and the second embodiments, the scattering of the carriers in the interface with the gate insulation film 20 cannot be prevented.
In contrast to this, according to the present embodiment, the semiconductor layer 32 of Si is formed between the semiconductor layer 18a of SiGe and the gate insulation film 20, whereby the carriers can be confined in the region spaced from the interface with the gate insulation film 20. Thus, according to the present embodiment, the scattering of the carriers in the interface with the gate insulation film 20 can be prevented. Thus, the semiconductor device according to the present embodiment can have higher mobility and higher speed.
(The Method for Fabricating the Semiconductor Device)
Then, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to
The steps up to the step of removing a hardmask 30 including the hard mask removing step are the same as those of the method for fabricating the semiconductor device described above with reference to
Then, as shown in
Then, an amorphous silicon film 17b of, e.g., a 10 nm-thickness is formed on the entire surface by, e.g., CVD. A raw material gas is, e.g., SiH4. A film forming temperature is, e.g., about 400° C.
Then, as shown in
The following semiconductor fabrication steps shown in
Thus the semiconductor device according to the present embodiment is fabricated.
(Modification 1)
Next, Modification 1 of the semiconductor device according to the present embodiment will be explained with reference to
The semiconductor device according to the present modification is characterized mainly in that a semiconductor region 14c of SiGe is formed below a semiconductor layer 18 of Si, and a semiconductor layer 34 of SiGe is formed on the semiconductor layer 18 of Si.
As shown in
The semiconductor layer 34 of SiGe is formed on the semiconductor layer 18 of Si. A composition of the semiconductor layer 34 is, e.g., Si0.5Ge0.5.
In the semiconductor device according to the present modification, because the semiconductor region 14c of SiGe is formed below the semiconductor layer 18 of Si, and the semiconductor layer 34 of SiGe is formed on the semiconductor layer 18 of Si, the energy band structure is as shown in
As seen in
The semiconductor layer 18 of Si functions as a quantum well for the electrons. On the other hand, the semiconductor layer 34 of SiGe functions as a quantum well for the holes.
In the present modification, because of the semiconductor layer 34 of SiGe formed between the semiconductor layer 18 of Si and the gate insulation film 20, the carriers can be confined in the regin spaced form the interface with the gate insulation film 20.
Thus, it is possible that the semiconductor region 14c of SiGe is formed below the semiconductor layer 18 of Si, and the semiconductor layer 34 of SiGe is formed on the semiconductor layer 18 of Si.
(Modification 2)
Next, Modification 2 of the semiconductor device according to the present embodiment will be explained with reference to
The semiconductor device according to the present modification is characterized mainly in that a semiconductor layer 18b of SiGe is formed on a semiconductor region 14c of SiGe with a Ge concentration of the semiconductor layer 18b higher than that of the semiconductor region 14c, and a semiconductor layer 32 of Si is formed on the semiconductor layer 18b.
As shown in
In the present modification, because the Ge composition ratio of the semiconductor layer 18b is set larger than that of the semiconductor region 14c, the lattice constant of the semiconductor layer 18b is larger than that of the semiconductor region 14c, whereby compression strains can be generated in the semiconductor layer 18b.
According to the present modification, because of compression strains generated in the semiconductor layer 18b, the semiconductor device can realize further higher mobility.
The present invention is not limited to the above-described embodiments and can cover other various modification.
For example, in the above-described embodiments, n-channel MOSFETs have been exemplified, but the present invention is applicable to the fabrication of p-channel MOSFETs.
In the semiconductor device according to the first embodiment, the semiconductor layer 18 is formed of intrinsic Si, but an n type dopant or a p type dopant maybe suitably implanted in the semiconductor layer 18. That is, unless the carrier mobility is extremely decreased, an n type dopant and a p type dopant may be implanted in the semiconductor layer 18.
In the above-described embodiments, a Ge composition ratio X of the semiconductor layer of Si1-xGex is, e.g., 0.5, but the composition ratio is not limited to 0.5. A Ge composition ratio X can be suitably set in a range of 0<X≦1. Accordingly, semiconductor layers of Ge may be suitably formed.
Conduction types of the respective layers are not limited to those of the above-described embodiments and can be suitably set.
In the semiconductor device according to Modifications 3 to 5 of the first embodiment, and the semiconductor device according to the second and the third embodiments, the source/drain region 24 is formed of a metal silicide but may be formed of a metal. It is possible to implant dopant ions in the semiconductor layer on both sides of the gate electrode to thereby form the source/drain diffused layer.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2002-63370 | Mar 2002 | JP | national |
This application is a division of U.S. application Ser. No. 10/382,855, filed on Mar. 7, 2003 now U.S. Pat. No. 6,855,987 which is based upon and claims priority of Japanese Patent Application No. 2002-63370, filed on Mar. 8, 2002, the contents being incorporated herein by reference.
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| Number | Date | Country | |
|---|---|---|---|
| 20050085027 A1 | Apr 2005 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10382855 | Mar 2003 | US |
| Child | 11004836 | US |
