Patent Application
20200194581
Embodiments of the present disclosure relate to a semiconductor device, and in particular they relate to a semiconductor device having a deep trench isolation structure and a method for forming the same.
Semiconductor devices have been widely used in various electronic products, such as personal computers, cellular phones, and digital cameras, for example. These semiconductor devices are usually fabricated by forming insulating layers or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using a photolithography process to pattern the various formed material layers, thereby forming electrical circuit parts and components on the semiconductor substrate.
Although existing semiconductor devices and methods of fabricating the same may generally meet basic demands, with the continued demand for miniaturization of semiconductor devices, they are not satisfactory in every respect.
Some embodiments of the present disclosure relate to a semiconductor device. The semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate, a first well region disposed in the semiconductor substrate on the buried layer, and a second well region disposed in the semiconductor substrate on the buried layer. The second well region surrounds the first well region. The semiconductor device also includes a third well region and a fourth well region disposed in the semiconductor substrate on the buried layer. The third well region and the fourth well region are located on opposite sides of the second well region. The semiconductor device also includes a source region disposed in the second well region, a drain region disposed in the first well region, a gate structure disposed on the first well region and the second well region, and a deep trench isolation structure disposed in the semiconductor substrate and surrounding the source region and the drain region. The deep trench isolation structure penetrates through the buried layer.
Some embodiments of the present disclosure further relate to a semiconductor device. The semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate, a first well region disposed in the semiconductor substrate on the buried layer, and a second well region disposed in the semiconductor substrate on the buried layer. The second well region surrounds the first well region. The semiconductor device also includes a third well region and a fourth well region disposed in the semiconductor substrate on the buried layer. The third well region and the fourth well region are adjacent to the second well region, and the third well region and the fourth well region are separate from each other. The buried layer, the first well region, the third well region and the fourth well region have a first conductivity type, while the second well region has a second conductivity type that is the opposite of the first conductivity type. The semiconductor device also includes a source region disposed in the second well region, a drain region disposed in the first well region, a gate structure disposed on the first well region and the second well region, and a deep trench isolation structure disposed in the semiconductor substrate and surrounding the second well region. The bottom surface of the deep trench isolation structure is lower than the bottom surface of the buried layer.
Some embodiments of the present disclosure relate to a method for forming a semiconductor device. The method includes providing a semiconductor substrate. A buried layer is disposed in the semiconductor substrate. The method also includes forming a first well region, a second well region, a third well region and a fourth well region in the semiconductor substrate on the buried layer. The second well region surrounds the first well region. The third well region and the fourth well region partially surround the second well region, and the third well region and the fourth well region are separate from each other. The buried layer, the first well region, the third well region and the fourth well region have a first conductivity type, while the second well region has a second conductivity type that is the opposite of the first conductivity type. The method also includes forming a source region in the second well region, forming a drain region in the first well region, forming a gate structure on the first well region and the second well region, and forming a deep trench isolation structure in the semiconductor substrate.
Aspects of the embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.
It should be understood that additional steps may be implemented before, during, or after the illustrated methods, and some steps might be replaced or omitted in other embodiments of the illustrated methods.
Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It should be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the embodiments of the present disclosure.
The semiconductor device, according to the embodiments of the present disclosure, includes a plurality of wells (e.g., the third well 106 and the fourth well 108 which will be described below) partially surrounding a source region, and includes a deep trench isolation structure surrounding the source region and a drain region. Therefore, the size of the semiconductor device may be reduced, the occurrence of leakage current in the substrate may be reduced or avoided, and the latch-up effect may be avoided or reduced.
First, referring to
As shown in
As shown in
The semiconductor substrate 100 may have a second conductivity type. Hereinafter, an embodiment in which the second conductivity type of the semiconductor substrate 100 is P-type (i.e. the semiconductor substrate 100 is a P-type semiconductor substrate) will be described for the sake of brevity. However, in some other embodiments, the second conductivity type of the semiconductor substrate 100 may also be N-type.
As shown in
The buried layer 202 may have a first conductivity type that is the opposite of the second conductivity type. In some embodiments, the semiconductor substrate 100 is a P-type substrate, so the buried layer 202 is an N-type buried layer. In some embodiments, the N-type buried layer 202 may include dopants such as nitrogen, phosphorus, arsenic, antimony, or bismuth, the doping concentration of which may be between 1017 and 1018 cm−3. For example, appropriate dopants may be implanted into a portion of the semiconductor substrate 100 by an ion implantation process to form the buried layer 202.
Referring to
The first well region 102 may have the first conductivity type, while the second well region 104 may have the second conductivity type. In other words, the conductivity type of the first well region 102 is the opposite of the conductivity type of the second well region 104. In some embodiments, the first well region 102 is an N-type well region, while the second well region 104 is a P-type well region. In some embodiments, the N-type first well region 102 may include dopants such as nitrogen, phosphorus, arsenic, antimony, or bismuth, the doping concentration of which may be between 1016 and 1017 cm−3. In some embodiments, the P-type second well region 104 may include dopants such as boron, aluminum, gallium, indium, or thallium, the doping concentration of which may be between 1016 and 1017 cm−3. For example, appropriate dopants may be implanted into a portion of the semiconductor substrate 100 by an ion implantation process to form the first well region 102 and the second well region 104.
In some embodiments, the first well region 102 and the buried layer 202 are separate from each other as shown in
Referring to
In some embodiments, as shown in
The third well region 106 and the fourth well region 108 may have the first conductivity type. In other words, the conductivity type of the third well region 106 and the fourth well region 108 is the same as the conductivity type of the buried layer 202. In some embodiments, the buried layer 202 is an N-type buried layer, so the third well region 106 and the fourth well region 108 are N-type well regions. In some embodiments, the N-type third well region 106 includes dopants such as nitrogen, phosphorus, arsenic, antimony, or bismuth, the doping concentration of which may be between 1016 and 1017 cm−3. In some embodiments, the N-type fourth well region 108 includes dopants such as nitrogen, phosphorus, arsenic, antimony, or bismuth, the doping concentration of which may be between 1016 and 1017 cm−3. The doping concentration of the third well region 106 may substantially be equal to the doping concentration of fourth well region 108. However, the embodiments of the present disclosure are not limited thereto. For example, appropriate dopants may be implanted into a portion of the semiconductor substrate 100 by an ion implantation process to form the third well region 106 and the fourth well region 108.
Referring to
The doped region 204 may have the second conductivity type. In other words, the doped region 204 may have the same conductivity type as the second well region 104. In some embodiments, the second well region 104 is a P-type well region, so the doped region 204 is a P-type doped region. In some embodiments, the P-type doped region 204 may include dopants such as boron, aluminum, gallium, indium, or thallium, the doping concentration of which may be between 1017 and 1018 cm−3. In some embodiments, the doping concentration of the doped region 204 is higher than the doping concentration of the second well region 104. For example, appropriate dopants may be implanted into a portion of the semiconductor substrate 100 by an ion implantation process to form the doped region 204 in the second well region 104.
Referring to
The source region 110 and the drain region 112 may have the first conductivity type. In other words, the conductivity type of the source region 110 and the drain region 112 may be the opposite of the conductivity type of the second well region 104. In some embodiments, the second well region 104 is a P-type well region, so the source region 110 and the drain region 112 are an N-type source region and an N-type drain region. In some embodiments, the N-type source region 110 includes dopants such as nitrogen, phosphorus, arsenic, antimony, or bismuth, the doping concentration of which may be between 1018 and 1019 cm−3. In some embodiments, the N-type drain region 112 includes dopants such as nitrogen, phosphorus, arsenic, antimony, or bismuth, the doping concentration of which may be between 1018 and 1019 cm−3. For example, appropriate dopants may be implanted into a portion of the semiconductor substrate 100 by an ion implantation process to form the source region 110 and the drain region 112.
Referring to
In some embodiments, the source region 110 is an N-type source region, so the doped region 206 is a P-type doped region. In some embodiments, the P-type doped region 206 may include dopants such as boron, aluminum, gallium, indium, or thallium, the doping concentration of which may be between 1018 and 1019 cm−3. In some embodiments, the doping concentration of the doped region 206 is higher than the doping concentration of the doped region 204. For example, appropriate dopants may be implanted into a portion of the semiconductor substrate 100 by an ion implantation process to form the doped region 206 in the doped region 204.
Referring to
Referring to
The conductivity type of the doped region 207 may be the same as the conductivity type of the drain region 112. In some embodiments, the drain region 112 is an N-type drain region, so the doped region 207 is an N-type doped region. In some embodiments, the N-type doped region 207 includes dopants such as nitrogen, phosphorus, arsenic, antimony, or bismuth, the doping concentration of which may be between 1016 and 1017 cm−3. In some embodiments, the doping concentration of the doped region 207 is lower than the doping concentration of the drain region 112. For example, appropriate dopants may be implanted into a portion of the semiconductor substrate 100 by an ion implantation process to form the doped region 207 in the first well region 102.
Referring to
In some embodiments, the conductivity type of the doped region 114 and the doped region 116 is the same as the conductivity type of the third well region 106 and the fourth well region 108 (i.e. the doped region 114, the doped region 116, the third well region 106 and the fourth well region 108 all have the first conductivity type). In some embodiments, the third well region 106 and the fourth well region 108 are N-type well regions, so the doped region 114 and the doped region 116 are N-type doped regions. In some embodiments, the N-type doped region 114 includes dopants such as nitrogen, phosphorus, arsenic, antimony, or bismuth, the doping concentration of which may be between 1018 and 1019 cm−3. In some embodiments, the N-type doped region 116 includes dopants such as nitrogen, phosphorus, arsenic, antimony, or bismuth, the doping concentration of which may be between 1018 and 1019 cm−3. In some embodiments, the doping concentration of the doped region 114 and the doped region 116 is higher than the doping concentration of the third well region 106 and the fourth well region 108. For example, appropriate dopants may be implanted into a portion of the semiconductor substrate 100 by an ion implantation process to form the doped region 114 and the doped region 116.
Referring to
In some embodiments, the deep trench isolation structure 118 surrounds the second well region 104 as shown in
In some embodiments, the deep trench isolation structure 118 is in direct contact with the second well region 104, the third well region 106 and the fourth well region 108. In some embodiments, the deep trench isolation structure 118 is in direct contact with a third side 104c and a fourth side 104d opposite to the third side 104c of the second well region 104, as shown in
In some embodiments, a suitable etching process may be performed to form a trench 118a in the semiconductor substrate 100, and then the trench 118a may be filled with suitable insulating materials (e.g., silicon oxide, silicon nitride or silicon oxynitride) to form the deep trench isolation structure 118. In some embodiments, the etching process is an anisotropic etching process (e.g., a plasma etching process), such that the trench 118a may have a larger aspect ratio (i.e. H/W). For example, the aspect ratio of the trench 118a may be between 10 and 20. In some embodiments, a suitable planarization process (e.g., chemical-mechanical polishing process) may be performed to remove the insulating material outside the trench 118a, such that a top surface of the deep trench isolation structure 118 is substantially coplanar with the top surface 100T of the semiconductor substrate 100.
Referring to
For example, the gate dielectric layer 208a may be formed of silicon oxide, silicon nitride, silicon oxynitride, high-κ dielectric material, any other suitable dielectric materials or a combination thereof. For example, the high-κ dielectric material may be LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfO2, HfO3, HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfSiO, HfTaTiO, HfAlON, (Ba, Sr)TiO3 (BST), Al2O3, other suitable high-κ dielectric materials or a combination thereof. In some embodiments, the gate dielectric layer 208a may be formed by a chemical vapor deposition, an atomic layer deposition or other suitable methods. For example, the chemical vapor deposition may be a low pressure chemical vapor deposition, a low temperature chemical vapor deposition, a rapid thermal chemical vapor deposition or a plasma-enhanced chemical vapor deposition.
For example, the gate electrode layer 208b may be formed of polycrystalline silicon, metal, metal alloy, metal nitride, metal silicide, metal oxide, other suitable conductive materials or a combination thereof. For example, the gate electrode layer 208b may be formed by a chemical vapor deposition process, a physical vapor deposition process (e.g., a vacuum evaporation process or sputtering process), other suitable processes or a combination thereof.
In some embodiments, the semiconductor device 10 may include a gate sidewall spacer 210 formed on the sidewall of the gate structure 208. For example, the gate sidewall spacer 210 may be formed of insulating materials, such as SiO2, SiN, SiON, SiOCN or SiCN. For example, a blanket layer of an insulating material may be formed by the chemical vapor deposition process or other suitable processes, and then an anisotropic etching may be performed on the blanket layer of the insulating material to form the gate sidewall spacer 210 on the sidewall of the gate structure 208.
In summary, the semiconductor device 10 according to the embodiments of the present disclosure includes a third well region 106 located on the first side 104a of the second well region 104, a fourth well region 108 located on the second side 104b of the second well region 104, and a deep trench isolation structure 118 surrounding the first well region 102, the second well region 104, the third well region 106 and the fourth well region 108. Thereby the size of the semiconductor device 10 may be reduced, the occurrence of leakage current in the substrate may be reduced or avoided, and the latch-up effect may be avoided or reduced.
In some embodiments, a plurality of the semiconductor devices 10 may be disposed in and/or on the semiconductor substrate 100 as shown in
In summary, the semiconductor device of the embodiments of the present disclosure includes a deep trench isolation structure surrounding the source region and the drain region, and thus the occurrence of leakage current in the substrate may be reduced or avoided. Furthermore, in the semiconductor device of the embodiments of the present disclosure, the drain region is formed in the first well region, the source region is formed in the second well region, and the third well region and the fourth well region that are electrically connected to the buried layer only partially surround the second well region, and thus the size of the semiconductor device may be reduced and the latch-up effect may be avoided or reduced.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection should be determined by the claims. In addition, although some embodiments of the present disclosure are disclosed above, they are not intended to limit the scope of the present disclosure. Furthermore, not all advantages of the embodiments of the present disclosure are discussed.
