Semiconductor device and method for manufacturing semiconductor device

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view schematically showing the structure of a semiconductor device according to one embodiment (first embodiment) of the present invention;

FIG. 2 is a sectional view schematically showing the structure of a semiconductor device according to one embodiment (second embodiment) of the present invention;

FIG. 3 is a sectional view schematically showing the structure of a semiconductor device according to one embodiment (third embodiment) of the present invention;

FIG. 4 is a sectional view schematically showing the structure of a semiconductor device according to one embodiment (fourth embodiment) of the present invention;

FIG. 5 is a sectional view schematically showing the structure of a semiconductor device according to one embodiment (fifth embodiment) of the present invention;

FIGS. 6A to 6H are sectional views showing manufacturing steps of a method for manufacturing a semiconductor device according to one embodiment (first embodiment) of the present invention;

FIGS. 7A to 7I are sectional views showing manufacturing steps of a method for manufacturing a semiconductor device according to one embodiment (second embodiment) of the present invention;

FIGS. 8A to 8C are sectional views showing manufacturing steps of a method for manufacturing a semiconductor device according to one embodiment (third embodiment) of the present invention;

FIGS. 9A to 9C are sectional views showing manufacturing steps of a method for manufacturing a semiconductor device according to one embodiment (fourth embodiment) of the present invention;

FIGS. 10A and 10D are sectional views showing manufacturing steps of a method for manufacturing a semiconductor device according to one embodiment (fifth embodiment) of the present invention;

FIG. 11 is a sectional view schematically showing the structure of one example of an existing semiconductor device;

FIGS. 12A to 12D are diagrams showing the schematic structure and operation of an existing thyristor-structure semiconductor device; and

FIG. 13 is a diagram showing the voltage-current (V-I) characteristic of an existing thyristor-structure semiconductor device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A semiconductor device according to one embodiment (first embodiment) of the present invention will be described below with reference to FIG. 1 as a sectional view of a schematic structure.

As shown in FIG. 1, a semiconductor device 1 includes a thyristor 2 arising from sequential joining of a first region (hereinafter, referred to as a first p-region) p1 of a first conductivity type (hereinafter, defined as the p-type), a second region (hereinafter, referred to as a first n-region) n1 of a second conductivity type (hereinafter, defined as the n-type) opposite to the first conductivity type, a third region (hereinafter, referred to as a second p-region) p2 of the first conductivity type (p-type), and a fourth region (hereinafter, referred to as a second n-region) n2 of the second conductivity type (n-type). Details of the semiconductor device 1 will be described below.

A germanium layer 12 is formed on a semiconductor substrate 11. In this germanium layer 12, the second p-region p2 of the first conductivity type (p-type) is formed. It is also possible to form the second p-region p2 in the whole of the germanium layer 12. Furthermore, it is also possible to employ a silicon germanium layer as the germanium layer 12. That is, this layer is composed of a material having a carrier mobility higher than that of silicon. As the semiconductor substrate 11, e.g. a silicon substrate is used.

The second p-region p2 is formed by introducing, as a p-type dopant, e.g. boron (B) with a dopant concentration of about 5×10¹⁷cm⁻³. It is desirable that the dopant concentration in the second p-region p2 be about 1×10¹⁶cm⁻³to 1×10¹⁹cm⁻³. Basically, this dopant concentration should be lower than that in the first n-region n1 of the second conductivity type (n-type) to be described later. As the p-type dopant, besides boron (B), another p-type impurity such as indium (In) is available.

Over the second p-region p2, a gate electrode 14 is formed with the intermediary of a gate insulating film 13. A hard mask (not shown) may be formed over the gate electrode 14. The gate insulating film 13 is formed of e.g. a silicon oxide (SiO₂) film and has a thickness of about 1 nm to 10 nm. The material of the gate insulating film 13 is not limited to silicon oxide (SiO₂), but it is also possible to use silicon oxynitride (SiON) or use another gate insulating film material applicable to a typical CMOS transistor, such as hafnium oxide (HfO₂), hafnium oxynitride (HfON), aluminum oxide (Al₂O₃), hafnium silicate (HfSiO), nitrided hafnium silicate (HfSiON), or lanthanum oxide (La₂O₃).

The gate electrode 14 is generally formed of poly-crystalline silicon. It is also possible to employ a metal gate electrode as the gate electrode 14 or alternatively form the gate electrode 14 by using silicon germanium (SiGe) or the like. A hard mask used in the formation of the gate electrode 14 may be left over the gate electrode 14. This hard mask is formed of e.g. a silicon oxide (SiO₂) film, silicon nitride (Si₃N₄) film, or the like.

Sidewalls 16 and 17 are formed on the side faces of the gate electrode 14. These sidewalls 16 and 17 are formed of a silicon oxide (SiO₂) film, silicon nitride (Si₃N₄) film, or a multi-layer film of these films. Over the area from the second region n1 to the gate electrode 14, a salicide block (not shown) used when a salicide process is carried out for the anode side and cathode side may be formed.

In the second p-region p2 on one lateral side of the gate electrode 14, the first n-region n1 of the second conductivity type (n-type) is formed. This first n-region n1 is formed by introducing e.g. phosphorous (P) as an n-type dopant to a dopant concentration of e.g. 1.5×10¹⁹cm⁻³. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²⁰cm⁻³, and this dopant concentration should be higher than that in the second p-region p2. Instead of phosphorous, another n-type dopant such as arsenic or antimony can also be used.

In the second p-region p2 on the other lateral side of the gate electrode 14, the second n-region n2 of the second conductivity type (n-type) is formed. This second n-region n2 is formed by introducing e.g. arsenic (As) as an n-type dopant to a dopant concentration of e.g. 5×10²⁰cm⁻³. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²¹cm⁻³, and this dopant concentration should be higher than that in the second p-region p2. Instead of arsenic, another n-type dopant such as phosphorous or antimony can also be used.

Furthermore, on the first n-region n1, the first p-region p1 of the first conductivity type (p-type) is formed. The first p-region p1 is so formed that the concentration of boron (B) in the film is set to 1×10²⁰cm⁻³for example. It is desirable that this dopant (boron) concentration be about 1×10¹⁸cm⁻³to 1×10²¹cm⁻³.

An anode electrode A is connected to the first p-region p1, and a cathode electrode K is connected to the second n-region n2. Over the first p-region p1, the second n-region n2, and the gate electrode 14, a silicide (titanium silicide, cobalt silicide, nickel silicide, or the like) may be formed, although not shown in the drawing.

In the semiconductor device 1 in which the above-described thyristor 2 is used as a memory cell, a field effect transistor (not'shown) may be formed as a selection transistor in the semiconductor substrate 11. Specifically, although not shown in the drawing, e.g. a well region of the first conductivity type (p-type) is formed in the semiconductor substrate 11, and the field effect transistor is formed by using this well region. For this field effect transistor, a gate electrode is formed over the p-type well region with the intermediary of a gate insulating film, and sidewalls are formed on both the sides of the gate electrode. Furthermore, in the p-type well region under the sidewalls, extension regions of the source and drain are formed. In addition, a drain region and a source region are formed in the p-type well region on one and the other lateral sides of the gate electrode with the intermediary of the extension region. The source region is connected to the second n-region n2 (cathode side) in the thyristor 2 via an interconnection (cathode electrode K). Furthermore, the drain region is connected to a bit line.

In the semiconductor device 1 according to an embodiment of the present invention, the first n-region n1 as the second region in the thyristor 2 and the first p-region p1 as the first region are formed in the germanium layer 12 or silicon germanium layer having mobility higher than that of silicon. Thus, the mobility of carriers in the first n-region n1 and the first p-region p1 as the first region can be enhanced. This can increase the speed of sweeping of the carriers out of the first n-region n1 and the first p-region p1 as the first region, which can enhance the speed of switching from the on-state to the off-state. Furthermore, because the carrier mobility is enhanced, increase in the speed of switching from the off-state to the on-state can also be expected as a synergetic effect. It is generally known that the carrier mobility of germanium is higher than that of silicon. For example, the mobility of electrons and holes in silicon is 1600 cm²/V·s and 430 cm²/V·s, respectively. In contrast, the mobility of electrons and holes in germanium is 3900 cm²/V·s and 1900 cm²/V·s, respectively. That is, both the mobility of electrons and that of holes in germanium are higher, and in particular, the mobility of holes in germanium is as high as about five times that in silicon. Therefore, by using germanium or silicon germanium, which is a mixture of silicon and germanium with high carrier mobility, as the material of at least a region in which the first n-region n1 and the first p-region p1 are formed, the switching speed of the thyristor 2 can be enhanced. This offers an advantage that the semiconductor device 1 having a high-speed thyristor can be provided.

A semiconductor device according to one embodiment (second embodiment) of the present invention will be described below with reference to FIG. 2 as a sectional view of a schematic structure.

As shown in FIG. 2, a semiconductor device 3 includes a thyristor 4 arising from sequential joining of a first, region (hereinafter, referred to as a first p-region) p1 of a first conductivity type (hereinafter, defined as the p-type), a second region (hereinafter, referred to as a first n-region) n1 of a second conductivity type (hereinafter, defined as the n-type) opposite to the first conductivity type, a third region (hereinafter, referred to as a second p-region) p2 of the first conductivity type (p-type), and a fourth region (hereinafter, referred to as a second n-region) n2 of the second conductivity type (n-type). Details of the semiconductor device 3 will be described below.

In a semiconductor substrate 11, the second p-region p2 of the first conductivity type (p-type) is formed. As a semiconductor substrate 11, e.g. a bulk silicon substrate is used. The second p-region p2 is formed by introducing, as a p-type dopant, e.g. boron (B) with a dopant concentration of about 5×10¹⁷cm⁻³. It is desirable that the dopant concentration in the second p-region p2 be about 1×10¹⁶cm⁻³to 1×10¹⁹cm⁻³. Basically, this dopant concentration should be lower than that in the first n-region n1 of the second conductivity type (n-type) to be described later. As the p-type dopant, besides boron (B), another p-type impurity such as indium (In) is available.

Sidewalls 16 and 17 are formed on the side faces of the gate electrode 14. These sidewalls 16 and 17 are formed of a silicon oxide (SiO₂) film, silicon nitride (Si₃N₄) film, or a multi-layer film of these films. Over the area from the second region n1 to the gate electrode 14, a salicide block (not shown) used when a salicide process is carried out for the anode side and cathode side may be formed.

In the second p-region p2 on one lateral side of the gate electrode 14, the first n-region n1 of the second conductivity type (n-type) is formed. The first n-region n1 is formed of a germanium layer or silicon germanium layer having a carrier mobility higher than that of silicon. The first n-region n1 is formed by epitaxially growing a germanium layer or silicon germanium layer in a recess 18 formed in the second p-region p2, and is formed by introducing e.g. phosphorous (P) as an n-type dopant to a dopant concentration of e.g. 1×10¹⁸cm⁻³. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²⁰cm⁻³, and this dopant concentration should be higher than that in the second p-region p2. Instead of phosphorous, another n-type dopant such as arsenic or antimony can also be used.

In the semiconductor device 3 in which the above-described thyristor 4 is used as a memory cell, a field effect transistor (not shown) may be formed as a selection transistor in the semiconductor substrate 11. Specifically, although not shown in the drawing, e.g. a well region of the first conductivity type (p-type) is formed in the semiconductor substrate 11, and the field effect transistor is formed by using this well region. For this field effect transistor, a gate electrode is formed over the p-type well region with the intermediary of a gate insulating film, and sidewalls are formed on both the sides of the gate electrode. Furthermore, in the p-type well region under the sidewalls, extension regions of the source and drain are formed. In addition, a drain region and a source region are formed in the p-type well region on one and the other lateral sides of the gate electrode with the intermediary of the extension region. The source region is connected to the second n-region n2 (cathode side) in the thyristor 4 via an interconnection (cathode electrode K). Furthermore, the drain region is connected to a bit line.

In the semiconductor device 3 according to an embodiment of the present invention, the first n-region n1 as the second region in the thyristor is formed in a germanium layer or silicon germanium layer having mobility higher than that of silicon. Thus, the mobility of carriers in the first n-region n1 can be enhanced. This can increase the speed of sweeping of the carriers out of the first n-region n1, which can enhance the speed of switching from the on-state to the off-state. Furthermore, because the carrier mobility is enhanced, increase in the speed of switching from the off-state to the on-state can also be expected as a synergetic effect. It is generally known that the carrier mobility of germanium is higher than that of silicon. For example, the mobility of electrons and holes in silicon is 1600 cm²/V·s and 430 cm²/V·s, respectively. In contrast, the mobility of electrons and holes in germanium is 3900 cm²/V·s and 1900 cm²/V·s, respectively. That is, both the mobility of electrons and that of holes in germanium are higher, and in particular, the mobility of holes in germanium is as high as about five times that in silicon. Therefore, by using germanium or silicon germanium as the material of at least the first n-region n1, the switching speed of the thyristor 4 can be enhanced. This offers an advantage that the semiconductor device 3 having a high-speed thyristor can be provided.

A semiconductor device according to one embodiment (third embodiment) of the present invention will be described below with reference to FIG. 3 as a sectional view of a schematic structure.

As shown in FIG. 3, a semiconductor device 5 includes a thyristor 6 arising from sequential joining of a first region (hereinafter, referred to as a first p-region) p1 of a first conductivity type (hereinafter, defined as the p-type), a second region (hereinafter, referred to as a first n-region) n1 of a second conductivity type (hereinafter, defined as the n-type) opposite to the first conductivity type, a third region (hereinafter, referred to as a second p-region) p2 of the first conductivity type (p-type), and a fourth region (hereinafter, referred to as a second n-region) n2 of the second conductivity type (n-type). Details of the semiconductor device 5 will be described below.

In a semiconductor substrate 11, the second p-region p2 of the first conductivity type (p-type) is formed. As this semiconductor substrate 11, e.g. a bulk silicon substrate is used. The second p-region p2 is formed by introducing, as a p-type dopant, e.g. boron (B) with a dopant concentration of about 5×10¹⁷cm⁻³. It is desirable that the dopant concentration in the second p-region p2 be about 1×10¹⁶cm⁻³to 1×10¹⁹cm⁻³. Basically, this dopant concentration should be lower than that in the first n-region n1 of the second conductivity type (n-type) to be described later. As the p-type dopant, besides boron (B), another p-type impurity such as indium (In) is available.

Over the second p-region p2, a gate electrode 14 is formed with the intermediary of a gate insulating film 13. An insulating film 15 serving as a hard mask may be formed over the gate electrode 14. The gate insulating film 13 is formed of e.g. a silicon oxide (SiO₂) film and has a thickness of about 1 nm to 10 nm. The material of the gate insulating film 13 is not limited to silicon oxide (SiO₂), but it is also possible to use silicon oxynitride (SiON) or use another gate insulating film material applicable to a typical CMOS transistor, such as hafnium oxide (HfO₂), hafnium oxynitride (HfON), aluminum oxide (Al₂O₃), hafnium silicate (HfSiO), nitrided hafnium silicate (HfSiON), or lanthanum oxide (La₂O₃).

Furthermore, on the first n-region n1, the first p-region p1 of the first conductivity type (p-type) is formed by using e.g. an epitaxially grown silicon layer. The first p-region p1 is so formed that the concentration of boron (B) in the film is set to 1×10²⁰cm⁻³for example. It is desirable that this dopant (boron) concentration be about 1×10¹¹cm⁻³to 1×10²¹cm⁻³.

In the semiconductor device 5 in which the above-described thyristor 6 is used as a memory cell, a field effect transistor (not shown) may be formed as a selection transistor in the semiconductor substrate 11. Specifically, although not shown in the drawing, e.g. a well region of the first conductivity type (p-type) is formed in the semiconductor substrate 11, and the field effect transistor is formed by using this well region. For this field effect transistor, a gate electrode is formed over the p-type well region with the intermediary of a gate insulating film, and sidewalls are formed on both the sides of the gate electrode. Furthermore, in the p-type well region under the sidewalls, extension regions of the source and drain are formed. In addition, a drain region and a source region are formed in the p-type well region on one and the other lateral sides of the gate electrode with the intermediary of the extension region. The source region is connected to the second n-region n2 (cathode side) in the thyristor 6 via an interconnection (cathode electrode K). Furthermore, the drain region is connected to a bit line.

In the semiconductor device 5 according to an embodiment of the present invention, the first n-region n1 as the second region in the thyristor is, formed in a germanium layer or silicon germanium layer having mobility higher than that of silicon. Thus, the mobility of carriers in the first n-region n1 can be enhanced. This can increase the speed of sweeping of the carriers out of the first n-region n1, which can enhance the speed of switching from the on-state to the off-state. Furthermore, because the carrier mobility is enhanced, increase in the speed of switching from the off-state to the on-state can also be expected as a synergetic effect. It is generally known that the carrier mobility of germanium is higher than that of silicon. For example, the mobility of electrons and holes in silicon is 1600 cm²/V·s and 430 cm²/V·s, respectively. In contrast, the mobility of electrons and holes in germanium is 3900 cm²/V·s and 1900 cm²/V·s, respectively. That is, both the mobility of electrons and that of holes in germanium are higher, and in particular, the mobility of holes in germanium is as high as about five times that in silicon. Therefore, by using germanium or silicon germanium as the material of at least the first n-region n1, the switching speed of the thyristor 6 can be enhanced. This offers an advantage that the semiconductor device 5 having a high-speed thyristor can be provided.

A semiconductor device according to one embodiment (fourth embodiment) of the present invention will be described below with reference to FIG. 4 as a sectional view of a schematic structure.

As shown in FIG. 4, a semiconductor device 7 includes a thyristor 8 arising from sequential joining of a first region (hereinafter, referred to as a first p-region) p1 of a first conductivity type (hereinafter, defined as the p-type), a second region (hereinafter, referred to as a first n-region) n1 of a second conductivity type (hereinafter, defined as the n-type) opposite to the first conductivity type, a third region (hereinafter, referred to as a second p-region) p2 of the first conductivity type (p-type), and a fourth region (hereinafter, referred to as a second n-region) n2 of the second conductivity type (n-type). Details of the semiconductor device 7 will be described below.

In a semiconductor substrate 11, the second p-region p2 of the first conductivity type (p-type) is formed. As this semiconductor substrate 11, e.g. a bulk silicon substrate is used. The second p-region p2 is formed by introducing, as a p-type dopant, e.g. boron (B) with a dopant concentration of about 5×10¹⁷cm⁻³. It is desirable that the dopant concentration in the second p-region p2 be about 1×10^{16 cm}⁻³to 1×10¹⁹cm⁻³. Basically, this dopant concentration should be lower than that in the first n-region n1 of the second conductivity type (n-type) to be described later. As the p-type dopant, besides boron (B), another p-type impurity such as indium (In) is available.

Sidewalls 16 and 17 are formed on the side faces of the gate electrode 14. These sidewalls 16 and 17 are formed of a silicon oxide (SiO₂) film, silicon nitride (Si₃N₄) film, or a multi-layer film of these films. An insulating film 42 is formed over the semiconductor substrate 11. Specifically, the insulating film 42 is formed over the area from a part of the gate electrode 14 to the side in which the region on one lateral side of the gate electrode 14 (second n-region n2) is formed. This insulating film 42 serves as a mask at the time of epitaxial growth, as described later in detail in the explanation of a manufacturing method. In addition, an insulating film 43 is formed over the semiconductor substrate 11. Specifically, the insulating film 43 is formed over the area from a part of the gate electrode 14 to the side in which the region on the other lateral side of the gate electrode 14 (first n-region n1) is formed. This insulating film 43 serves as a mask at the time of epitaxial growth of the first p-region p1, as described later in detail in the explanation of a manufacturing method.

On the second p-region p2 on one lateral side of the gate electrode 14, the first n-region n1 of the second conductivity type (n-type) is formed. The first n-region n1 is formed of a germanium layer or silicon germanium layer having a carrier mobility higher than that of silicon. The first n-region n1 is formed by epitaxially growing a germanium layer or silicon germanium layer, and is formed by introducing e.g. phosphorous (P) as an n-type dopant to a dopant concentration of e.g. 1×10¹⁸cm⁻³. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²⁰cm⁻³, and this dopant concentration should be higher than that in the second p-region p2. Instead of phosphorous, another n-type dopant such as arsenic or antimony can also be used.

In the semiconductor device 7 in which the above-described thyristor 8 is used as a memory cell, a field effect transistor (not shown) may be formed as a selection transistor in the semiconductor substrate 11. Specifically, although not shown in the drawing, e.g. a well region of the first conductivity type (p-type) is formed in the semiconductor substrate 11, and the field effect transistor is formed by using this well region. For this field effect transistor, a gate electrode is formed over the p-type well region with the intermediary of a gate insulating film, and sidewalls are formed on both the sides of the gate electrode. Furthermore, in the p-type well region under the sidewalls, extension regions of the source and drain are formed. In addition, a drain region and a source region are formed in the p-type well region on one and the other lateral sides of the gate electrode with the intermediary of the extension region. The source region is connected to the second n-region n2 (cathode side) in the thyristor 8 via an interconnection (cathode electrode K). Furthermore, the drain region is connected to a bit line.

In the semiconductor device 7 according to an embodiment of the present invention, the first n-region n1 as the second region in the thyristor is formed in a germanium layer or silicon germanium layer having mobility higher than that of silicon. Thus, the mobility of carriers in the first n-region n1 can be enhanced. This can increase the speed of sweeping of the carriers out of the first n-region n1, which can enhance the speed of switching from the on-state to the off-state. Furthermore, because the carrier mobility is enhanced, increase in the speed of switching from the off-state to the on-state can also be expected as a synergetic effect. It is generally known that the carrier mobility of germanium is higher than that of silicon. For example, the mobility of electrons and holes in silicon is 1600 cm²/V·s and 430 cm²/V·s, respectively. In contrast, the mobility of electrons and holes in germanium is 3900 cm²/V·s and 1900 cm²/V·s, respectively. That is, both the mobility of electrons and that of holes in germanium are higher, and in particular, the mobility of holes in germanium is as high as about five times that in silicon. Therefore, by using germanium or silicon germanium as the material of at least the first n-region n1, the switching speed of the thyristor 8 can be enhanced. This offers an advantage that the semiconductor device 7 having a high-speed thyristor can be provided.

A semiconductor device according to one embodiment (fifth embodiment) of the present invention will be described below with reference to FIG. 5 as a sectional view of a schematic structure.

As shown in FIG. 5, a semiconductor device 9 includes a thyristor 10 arising from sequential joining of a first region (hereinafter, referred to as a first p-region) p1 of a first conductivity type (hereinafter, defined as the p-type), a second region (hereinafter, referred to as a first n-region) n1 of a second conductivity type (hereinafter, defined as the n-type) opposite to the first conductivity type, a third region (hereinafter, referred to as a second p-region) p2 of the first conductivity type (p-type), and a fourth region (hereinafter, referred to as a second n-region) n2 of the second conductivity type (n-type). Details of the semiconductor device 9 will be described below.

Sidewalls 16 and 17 are formed on the side faces of the gate electrode 14. These sidewalls 16 and 17 are formed of a silicon oxide (SiO₂) film, silicon nitride (Si₃N₄) film, or a multi-layer film of these films. Over the area from the second region n1 to the gate electrode 14, a salicide block (not shown) used when a salicide process is carried out for the anode side and cathode side may be formed.

In the second p-region p2 on one lateral side of the gate electrode 14, the first n-region n1 of the second conductivity type (n-type) is formed. The first n-region n1 is formed of a germanium layer or silicon germanium layer having a carrier mobility higher than that of silicon. The first n-region n1 is formed by epitaxially growing a germanium layer or silicon germanium layer in a recess 18 formed in the second p-region p2, and introducing e.g. phosphorous (P) as an n-type dopant to a dopant concentration of e.g. 1×10¹⁸cm⁻³. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²⁰cm⁻³, and this dopant concentration should be higher than that in the second p-region p2. Instead of phosphorous, another n-type dopant such as arsenic or antimony can also be used.

Furthermore, in a recess 19 formed in the first n-region n1, the first p-region p1 of the first conductivity type (p-type) is formed by using e.g. an epitaxially grown silicon layer. The first p-region p1 is so formed that the concentration of boron (B) in the film is set to 1×10²⁰cm⁻³, for example. It is desirable that this dopant (boron) concentration be about 1×10¹⁸cm⁻³to 1×10²¹cm⁻³.

In the semiconductor device 9 in which the above-described thyristor 10 is used as a memory cell, a field effect transistor (not shown) may be formed as a selection transistor in the semiconductor substrate 11. Specifically, although not shown in the drawing, e.g. a well region of the first conductivity type (p-type) is formed in the semiconductor substrate 11, and the field effect transistor is formed by using this well region. For this field effect transistor, a gate electrode is formed over the p-type well region with the intermediary of a gate insulating film, and sidewalls are formed on both the sides of the gate electrode. Furthermore, in the p-type well region under the sidewalls, extension regions of the source and drain are formed. In addition, a drain region and a source region are formed in the p-type well region on one and the other lateral sides of the gate electrode with the intermediary of the extension region. The source region is connected to the second n-region n2 (cathode side) in the thyristor 10 via an interconnection (cathode electrode K). Furthermore, the drain region is connected to a bit line.

In the semiconductor device 9 according to an embodiment of the present invention, the first n-region n1 as the second region in the thyristor is formed in a germanium layer or silicon germanium layer having mobility higher than that of silicon. Thus, the mobility of carriers in the first n-region n1 can be enhanced. This can increase the speed of sweeping of the carriers out of the first n-region n1, which can enhance the speed of switching from the on-state to the off-state. Furthermore, because the carrier mobility is enhanced, increase in the speed of switching from the off-state to the on-state can also be expected as a synergetic effect. It is generally known that the carrier mobility of germanium is higher than that of silicon. For example, the mobility of electrons and holes in silicon is 1600 cm²/V·s and 430 cm²/V·s, respectively. In contrast, the mobility of electrons and holes in germanium is 3900 cm²/V·s and 1900 cm²/V·s, respectively. That is, both the mobility of electrons and that of holes in germanium are higher, and in particular, the mobility of holes in germanium is as high as about five times that in silicon. Therefore, by using germanium or silicon germanium as the material of at least the first n-region n1, the switching speed of the thyristor 10 can be enhanced. This offers an advantage that the semiconductor device 9 having a high-speed thyristor can be provided.

A method for manufacturing a semiconductor device according to one embodiment (first embodiment) of the present invention will be described below with reference to FIGS. 6A to 6H as sectional views of manufacturing steps. This manufacturing method is one example of a method for manufacturing the semiconductor device 1 described with FIG. 1.

Referring initially to FIG. 6A, e.g. a silicon substrate is used as the semiconductor substrate 11. Specifically, e.g. a bulk silicon substrate such as a CZ silicon wafer is used. Over the semiconductor substrate 11, the germanium layer 12 or silicon germanium layer having mobility higher than that of silicon is formed by e.g. epitaxial growth. As one example of the condition of the epitaxial growth, germane (GeH₄) is used as the source gas, and the deposition temperature is set to e.g. 700° C. The film thickness of the germanium layer 12 is so designed depending on the depth of the junction between the second p-region p2 as the third region and the first n-region n1, which will be formed later, that the lower face of the germanium layer 12 is disposed at a position deeper than the junction. It is also preferable to form a silicon germanium layer (not shown) as a buffer layer for lattice matching between the semiconductor substrate 11 formed of a silicon substrate and the germanium layer 12. Moreover, a silicon cap layer (not shown) may be deposited over the germanium layer 12. The purpose of the deposition of the silicon cap layer is to suppress reaction of the germanium layer, which is very highly reactive, and to obtain, in a later step of forming a gate insulating film and so on, the same film thickness of an oxide layer as that of an oxide layer formed on silicon. In FIG. 6B and the subsequent drawings, illustration of the semiconductor substrate 11 is omitted.

Referring next to FIG. 6B, the germanium layer 12 is turned into a region of the first conductivity type (p-type). This p-region will serve as the second p-region p2 of a thyristor. As one example of the condition of the ion implantation, boron (B) is used as a p-type dopant, and the dose amount is so set that a dopant concentration of 5×10¹⁷cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁶cm⁻³to 1×10¹⁹cm⁻³. Basically, this dopant concentration should be lower than that in the first n-region of the second conductivity type (n-type) to be formed later. As the p-type dopant, besides boron (B), another p-type dopant such as indium (In) is available. Alternatively, at the time of the formation of an epitaxial layer as the germanium layer 12, the epitaxial growth accompanied by addition of diborane (B₂H₆) may be carried out.

Referring next to FIG. 6C, the gate insulating film 13 is formed over the second p-region p2. This gate insulating film 13 is formed of e.g. a silicon oxide (SiO₂) film and deposited to a thickness of about 1 nm to 10 nm. The material of the gate insulating film 13 is not limited to silicon-oxide (SiO₂), but it is also possible to use silicon oxynitride (SiON) or use another gate insulating film material presently studied for a typical CMOS, such as hafnium oxide (HfO₂), hafnium oxynitride (HfON), aluminum oxide (Al₂O₃), hafnium silicate (HfSiO), nitrided hafnium silicate (HfSiON), or lanthanum oxide (La₂O₃).

Subsequently, the gate electrode 14 is formed on the gate insulating film 13 over the region that is to serve as the second p-region p2. The gate electrode 14 is generally formed of poly-crystalline silicon. It is also possible to employ a metal gate electrode as the gate electrode 14 or alternatively form the gate electrode 14 by using silicon germanium (SiGe) or the like.

The gate electrode 14 is formed in the following manner for example. Specifically, a gate electrode forming film is deposited on the gate insulating film 13, and then an etching mask is formed through typical resist application and lithography. Subsequently, by an etching technique with use of the etching mask, the gate electrode forming film is etch-processed. As this etching technique, general dry etching can be used. Alternatively, it is also possible to form the gate electrode 14 by wet etching. Furthermore, over the gate electrode forming film, a silicon oxide (SiO₂) film, silicon nitride (Si₃N₄) film, or the like may be formed as a hard mask 41 (insulating film 15).

Referring next to FIG. 6D, by typical resist application and lithography, an ion implantation mask 31 is formed in which an aperture is formed over the region on one lateral side of the gate electrode 14, i.e., over the region in which the second n-region is to be formed. Subsequently, by ion implantation with use of the ion implantation mask 31, an n-type dopant is introduced into the second p-region p2 formed on one lateral side of the gate electrode 14 to thereby form the second n-region n2. As an example of the condition of the ion implantation, phosphorous (P) is used as a dopant, and the dose amount is so set that a dopant concentration of 5×10²⁰cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²¹cm⁻³, and this dopant concentration should be higher than that in the second p-region p2. Instead of phosphorous, another n-type dopant such as gallium, arsenic or antimony can also be used. After the ion implantation, the ion implantation mask 31 is removed.

Subsequently, as activation annealing, e.g. spike annealing at 1050° C. for about zero seconds is carried out. The conditions of this annealing may be any as long as the dopants can be activated.

Referring next to FIG. 6E, the sidewalls 16 and 17 are formed on the side faces of the gate electrode 14. These sidewalls 16 and 17 can be formed by depositing a sidewall forming film that covers the gate electrode 14 and then etching back this sidewall forming film, for example. The sidewalls 16 and 17 may be formed of either one of a silicon oxide (SiO₂) film and silicon nitride (Si₃N₄) film, or alternatively may be formed of a multi-layer film of these films. The sidewalls may be formed before the ion implantation step for forming the second n-region.

Referring next to FIG. 6F, by typical resist application and lithography, an ion implantation mask 33 is formed in which an aperture is formed over the region on the other lateral side of the gate electrode 14, i.e., over the region in which the first n-region is to be formed. Subsequently, by ion implantation with use of the ion implantation mask 33, a dopant of the second conductivity type (n-type) is introduced into the second p-region p2 positioned on the other lateral side of the gate electrode 14 with the intermediary of the sidewall 17, to thereby form the first n-region n1 of the second conductivity type (n-type). As an example of the condition of the ion implantation, phosphorous (P) is used as a dopant, and the dose amount is so set that a dopant concentration of 1.5×10¹⁹cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²⁰cm⁻³, and this dopant concentration should be higher than that in the second p-region p2. Instead of phosphorous, another n-type dopant such as gallium, arsenic or antimony can also be used. After the ion implantation, the ion implantation mask 33 is removed.

Subsequently, as activation annealing, e.g. spike annealing at 1050° C. for about zero seconds is carried out. The conditions of this annealing may be any as long as the dopants can be activated.

Referring next to FIG. 6G, by typical resist application and lithography, an ion implantation mask 35 is formed in which an aperture is formed over the region in the first n-region n1 in which the first p-region is to be formed. Subsequently, by ion implantation with use of the ion implantation mask 35, a p-type dopant is introduced into an upper part of the first n-region n1 to thereby form the first p-region p1. As an example of the condition of the ion implantation, boron (B) is used as a dopant, and the dose amount is so set that a dopant concentration of 1×10²⁰cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²¹cm⁻³, and this dopant concentration should be higher than that in the first n-region n1. The sidewalls may be formed before the ion implantation. The dopant may be another p-type impurity such as indium (In) or aluminum (Al). After the ion implantation, the ion implantation mask 35 is removed.

Subsequently, as activation annealing, e.g. spike annealing at 1000° C. for about zero seconds is carried out. The conditions of this annealing may be any as long as the dopants can be activated.

Referring next to FIG. 6H, by a typical electrode formation technique, the anode electrode A connected to the first p-region p1 and the cathode electrode K connected to the second n-region n2 are formed. At this time, it is preferable to form a silicide (TiSi, CoSi, NiSi, or the like) at the both-end electrode formation parts on the first p-region p1 and the second n-region n2 through a salicide step. In this case, it is preferable to form a salicide block covering the first n-region n1. After the electrode formation, a wiring step similar to that in a typical CMOS step is carried out.

In the manufacturing method of the first embodiment, the first n-region n1 in the thyristor is formed by using the germanium layer 12 or silicon germanium layer having mobility higher than that of silicon. Thus, the mobility of carriers in the first n-region n1 can be enhanced. This can increase the speed of sweeping of the carriers out of the first n-region n1, which can enhance the speed of switching from the on-state to the off-state. Furthermore, because the carrier mobility is enhanced, increase in the speed of switching from the off-state to the on-state can also be expected as a synergetic effect. It is generally known that the carrier mobility of germanium is higher than that of silicon. For example, the mobility of electrons and holes in silicon is 1600 cm²/V·s and 430 cm²/V·s, respectively. In contrast, the mobility of electrons and holes in germanium is 3900 cm²/V·s and 1900 cm²/V·s, respectively. That is, both the mobility of electrons and that of holes in germanium are higher, and in particular, the mobility of holes in germanium is as high as about five times that in silicon. Therefore, by using germanium or silicon germanium, which is a mixture of silicon and germanium with high carrier mobility, as the material of at least the second region, the switching speed of one thyristor 2 formed of the first p-region p1, the first n-region n1, the second p-region p2, and the second n-region n2 can be enhanced. This offers an advantage that a semiconductor device having the high-speed thyristor 2 can be manufactured.

A method for manufacturing a semiconductor device according to one embodiment (second embodiment) of the present invention will be described below with reference to FIGS. 7A to 7I as sectional views of manufacturing steps. This manufacturing method is one example of a method for manufacturing the semiconductor device 3 described with FIG. 2.

Referring initially to FIG. 7A, e.g. a silicon substrate is used as the semiconductor substrate 11. Specifically, e.g. a bulk silicon substrate such as a CZ silicon wafer is used. A region of the first conductivity type (p-type) is formed in an upper part of the semiconductor substrate 11. This p-region will serve as the second p-region p2 of a thyristor. As one example of the condition of the ion implantation, boron (B) is used as a p-type dopant, and the dose amount is so set that a dopant concentration of 5×10¹⁷cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁶cm⁻³to 1×10¹⁹cm⁻³; Basically, this dopant concentration should be lower than that in the first n-region of the second conductivity type (n-type) to be formed later. As the p-type dopant, besides boron (B), another p-type dopant such as indium (In) is available. Alternatively, at the time of the formation of an epitaxial layer as the germanium layer 12, the epitaxial growth accompanied by addition of diborane (B₂H₆) may be carried out. In FIG. 7B and the subsequent drawings, illustration of a lower part of the semiconductor substrate 11 is omitted.

Referring-next to FIG. 7B, the gate insulating film 13 is formed over the second p-region p2. This gate insulating film 13 is formed of e.g. a silicon oxide (SiO₂) film and deposited to a thickness of about 1 nm to 10 nm. The material of the gate insulating film 13 is not limited to silicon oxide (SiO₂), but it is also possible to use silicon oxynitride (SiON) or use another gate insulating film material presently studied for a typical CMOS, such as hafnium oxide (HfO₂), hafnium oxynitride (HfON), aluminum oxide (Al₂O₃), hafnium silicate (HfSiO), nitrided hafnium silicate (HfSiON), or lanthanum oxide (La₂O₃).

The gate electrode 14 is formed in the following manner, for example. Specifically, a gate electrode forming film is deposited on the gate insulating film 13, and then an etching mask is formed through typical resist application and lithography. Subsequently, by an etching technique with use of the etching mask, the gate electrode forming film is etch-processed. As this etching technique, general dry etching can be used. Alternatively, it is also possible to form the gate electrode 14 by wet etching. Furthermore, over the gate electrode forming film, a silicon oxide (SiO₂) film, silicon nitride (Si₃N₄) film, or the like may be formed as a hard mask 41 (insulating film 15).

Referring next to FIG. 7C, by typical resist application and lithography, an ion implantation mask 31 is formed in which an aperture is formed over the region on one lateral side of the gate electrode 14, i.e., over the region in which the second n-region is to be formed. Subsequently, by ion implantation with use of the ion implantation mask 31, an n-type dopant is introduced into the second p-region p2 formed on one lateral side of the gate electrode 14 to thereby form the second n-region n2. As an example of the condition of the ion implantation, phosphorous (P) is used as a dopant, and the dose amount is so set that a dopant concentration of 5×10²⁰cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²⁰cm⁻³, and this dopant concentration should be higher than that in the second p-region p2. Instead of phosphorous, another n-type dopant such as gallium, arsenic or antimony can also be used. After the ion implantation, the ion implantation mask 31 is removed.

Subsequently, as activation annealing, e.g. spike annealing at 1050° C. for about zero seconds is carried out. The conditions of this annealing may be any as long as the dopants can be activated.

Referring next to FIG. 7D, the sidewalls 16 and 17 are formed on the side faces of the gate electrode 14. These sidewalls 16 and 17 can be formed by depositing a sidewall forming film that covers the gate electrode 14 and then etching back this sidewall forming film, for example. The sidewalls 16 and 17 may be formed of either one of a silicon oxide (SiO₂) film and silicon nitride (Si₃N₄) film, or alternatively may be formed of a multi-layer film of these films. The sidewalls may be formed before the ion implantation step for forming the second n-region.

Referring next to FIG. 7E, the insulating film 42 that is to serve as a mask at the time of epitaxial growth is formed. This insulating film 42 is formed of e.g. a silicon nitride film. The film thickness thereof is set to e.g. 20 nm. Thereafter, by typical resist application and lithography, an etching mask (not shown) is formed in which an aperture is formed over the region on the other lateral side of the gate electrode 14, i.e., over the region in which the first n-region is to be formed. Subsequently, by an etching technique with use of this etching mask, the insulating film 42 on the other lateral side of the gate electrode 14 is etched. In this etching, the gate insulating film 13 in the etching area may be etched. This etching exposes the surface of the semiconductor substrate 11 in the region in which the first n-region is to be formed. In this example, a silicon nitride film is used in order to ensure the selectivity at the time of the epitaxial growth. However, another kind of film may be used as long as the selectivity can be ensured. Furthermore, this step may be carried out simultaneously with the sidewall forming step.

Referring next to FIG. 7F, the recess 18 is formed by etching the second p-region p2 with use of the insulating film 42 and the sidewall 17 as the mask. At this time, if the gate insulating film 13 remains, this gate insulating film 13 is removed through the etching. This recess 18 is formed by etching the semiconductor substrate 11 to a depth of e.g. 200 nm. This etching depth is equivalent to the depth of the junction between the first n-region n1 and the second p-region p2, and therefore, may be adequately changed depending on device characteristics.

Referring next to FIG. 7G, the first n-region n1 of the second conductivity type (n-type) is formed in the recess 18 by epitaxial growth. This first n-region n1 is formed by using selective epitaxial growth of germanium or silicon germanium. As one example of the condition of this epitaxial growth, germane (GeH₄), phosphine (PH₃), and hydrogen chloride (HCl) gas are used as the source gas, and the substrate temperature (deposition temperature) is set to 750° C. Furthermore, the condition is so set that a dopant concentration (e.g., phosphorous concentration) of e.g. 1×10¹⁸cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²¹cm⁻³. Instead of phosphine (PH₃), another n-type impurity source such as arsine (AsH₃) or an organic source of any of these substances may be used. Thereafter, the ion implantation mask 33 is removed. Before the epitaxial growth, the surface of the silicon substrate may be cleaned by using a chemical such as hydrof luoric acid (HF), hydrogen (H₂) gas, and so on according to need.

Referring next to FIG. 7H, by typical resist application and lithography, an ion implantation mask 35 is formed in which an aperture is formed over the region in the first n-region n1 in which the first p-region is to be formed. Subsequently, by ion implantation with use of the ion implantation mask 35, a p-type dopant is introduced into an upper part of the first n-region n1 to thereby form the first p-region p1. As an example of the condition of the ion implantation, boron (B) is used as a dopant, and the dose amount is so set that a dopant concentration of 1×10²⁰cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²¹cm⁻³, and this dopant concentration should be higher than that in the first n-region n1. The sidewalls may be formed before the ion implantation. The dopant may be another p-type impurity such as indium (In) or aluminum (Al). After the ion implantation, the ion implantation mask 35 is removed.

Subsequently, as activation annealing, e.g. spike annealing at 1000° C. for about zero seconds is carried out. The conditions of this annealing may be any as long as the dopants can be activated.

Referring next to FIG. 7I, by a typical electrode formation technique, the anode electrode A connected to the first p-region p and the cathode electrode K connected to the second n-region n2 are formed. At this time, it is preferable to form a silicide (TiSi, CoSi, NiSi, or the like) at the both-end exposed parts on the first p-region p1 and the second n-region n2 through a salicide step. After the electrode formation, a wiring step similar to that in a typical CMOS step is carried out.

In the manufacturing method of the second embodiment, the first n-region n1 in the thyristor 4 is formed by using a germanium layer or silicon germanium layer having mobility higher than that of silicon. Thus, the mobility of carriers in the first n-region n1 can be enhanced. This can increase the speed of sweeping of the carriers out of the first n-region n1, which can enhance the speed of switching from the on-state to the off-state. Furthermore, because the carrier mobility is enhanced, increase in the speed of switching from the off-state to the on-state can also be expected as a synergetic effect. It is generally known that the carrier mobility of germanium is higher than that of silicon. For example, the mobility of electrons and holes in silicon is 1600 cm²/V·s and 430 cm²/V·s, respectively. In contrast, the mobility of electrons and holes in germanium is 3900 cm²/V·s and 1900 cm²/V·s, respectively. That is, both the mobility of electrons and that of holes in germanium are higher, and in particular, the mobility of holes in germanium is as high as about five times that in silicon. Therefore, by using germanium or silicon germanium, which is a mixture of silicon and germanium with high carrier mobility, as the material of at least the second region, the switching speed of the thyristor 4 formed of the first p-region p1, the first n-region n1, the second p-region p2, and the second n-region n2 can be enhanced. This offers an advantage that the semiconductor device 3 having the high-speed thyristor 4 can be manufactured.

A method for manufacturing a semiconductor device according to one embodiment (third embodiment) of the present invention will be described below with reference to FIGS. 8A to 8C as sectional views of manufacturing steps. This manufacturing method is one example of a method for manufacturing the semiconductor device 3 described with FIG. 3.

The steps described with FIGS. 7A to 7F are carried out. These steps described with FIGS. 7A to 7F are the same as those in the manufacturing method of the second embodiment, and therefore, the description thereof is omitted. As the result of the steps, as shown in FIG. 8A, the second p-region p2 is formed in the semiconductor substrate 11, and the gate electrode 14 is formed over the second p-region p2 with the intermediary of the gate insulating film 13. The hard mask 41 is formed on the gate electrode 14. The sidewalls 16 and 17 are formed on the side faces of the gate electrode 14, and the second n-region n2 is formed in the second p-region p2 on one lateral side of the gate electrode 14. Subsequently, the insulating film 42 that is to serve as a mask at the time of epitaxial growth is formed. This insulating film 42 is formed of e.g. a silicon nitride film. The film thickness thereof is set to e.g. 20 nm. Thereafter, by typical resist application and lithography, an etching mask (not shown) is formed in which an aperture is formed over the region on the other lateral side of the gate electrode 14, i.e., over the region in which the first n-region is to be formed. Subsequently, by an etching technique with use of this etching mask, the insulating film 42 on the other lateral side of the gate electrode 14 is etched to thereby expose the surface of the semiconductor substrate 11 in the region in which the first n-region is to be formed. The recess 18 is formed by etching the second p-region p2 with use of the insulating film 42 and the sidewall 17 as the mask. Subsequently, the first n-region n1 of the second conductivity type (n-type), composed of germanium or silicon germanium, is formed in the recess 18 by selective epitaxial growth. This first n-region n1 is so formed that the upper face thereof is higher than the surface of the semiconductor substrate (silicon substrate) 11 by about 50 nm to 100 nm. This can prevent the short-circuit between the second p-region p2 and the first p-region p1 to be formed later.

As one example of the condition of this selective epitaxial growth, germane (GeH₄), phosphine (PH₃), and hydrogen chloride (HCl) gas are used as the source gas, and the substrate temperature (deposition temperature) is set to 750° C. Furthermore, the condition is so set that a dopant concentration (e.g., phosphorous concentration) of e.g. 1×10¹⁸cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁷cm⁻³to 1×10²¹cm⁻³. Instead of phosphine (PH₃), another n-type impurity source such as arsine (AsH₃) or an organic source of any of these substances may be used. Before the epitaxial growth, the surface of the silicon substrate may be cleaned by using a chemical such as hydrofluoric acid (HF), hydrogen (H₂) gas, and so on according to need. In FIGS. 8B and 8C, illustration of a lower part of the semiconductor substrate 11 is omitted.

Referring next to FIG. 8B, the first p-region p1 of the first conductivity type (p-type), formed of an epitaxially grown silicon layer, is formed on the first n-region n1 by selective epitaxial growth. As one example of the condition of this selective epitaxial growth, monosilane (SiH₄), diborane (B₂H₆), and hydrogen chloride (HCl) gas are used as the source gas, and the substrate temperature (deposition temperature) is set to 750° C. Furthermore, the condition is so set that a dopant concentration (e.g., boron concentration) of e.g. 1×10²⁰cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²¹cm⁻³. Instead of monosilane (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), dichlorosilane (SiH₂Cl₂), trichlorosilane (SiHCl₃), tetrachlorosilane (SiCl₄), or the like may be used. Furthermore, instead of diborane (B₂H₆), another p-type impurity source such as an organic source may be used. In addition, a silicon germanium (SiGe) film may be deposited instead of the silicon (Si) film by selective epitaxial growth. However, because this film should have a band gap wider than that of germanium (Ge), the composition ratio of silicon (Si) to germanium (Ge) should be adequately adjusted.

After this film deposition, as activation annealing, e.g. spike annealing at 1000° C. for about zero seconds is carried out according to need. The conditions of this annealing may be any as long as the dopants can be activated. This activation annealing may be carried out after the first n-region n1 is formed.

Referring next to FIG. 8C, by a typical electrode formation technique, the anode electrode A connected to the first p-region p1 and the cathode electrode K connected to the second n-region n2 are respectively formed. At this time, it is preferable to form a silicide (TiSi, CoSi, NiSi, or the like) at the both-end exposed parts on the first p-region p1 and the second n-region n2 through a salicide step. After the electrode formation, a wiring step similar to that in a typical CMOS step is carried out.

In the manufacturing method of the third embodiment, the first n-region n1 in the thyristor 6 is formed by using a germanium layer or silicon germanium layer having mobility higher than that of silicon. Thus, the mobility of carriers in the first n-region n1 can be enhanced. This can increase the speed of sweeping of the carriers out of the first n-region n1, which can enhance the speed of switching from the on-state to the off-state. Furthermore, because the carrier mobility is enhanced, increase in the speed of switching from the off-state to the on-state can also be expected as a synergetic effect. It is generally known that the carrier mobility of germanium is higher than that of silicon. For example, the mobility of electrons and holes in silicon is 1600 cm²/V·s and 430 cm²/V·s, respectively. In contrast, the mobility of electrons and holes in germanium is 3900 cm²/V·s and 1900 cm²/V·s, respectively. That is, both the mobility of electrons and that of holes in germanium are higher, and in particular, the mobility of holes in germanium is as high as about five times that in silicon. Therefore, by using germanium or silicon germanium, which is a mixture of silicon and germanium with high carrier mobility, as the material of at least the second region, the switching speed of the thyristor 6 formed of the first p-region p1, the first n-region n1, the second p-region p2, and the second n-region n2 can be enhanced. This offers an advantage that the semiconductor device 5 having the high-speed thyristor 6 can be manufactured.

A method for manufacturing a semiconductor device according to one embodiment (fourth embodiment) of the present invention will be described below with reference to FIGS. 9A to 9C as sectional views of manufacturing steps. This manufacturing method is one example of a method for manufacturing the semiconductor device 7 described with FIG. 4.

The steps described with FIGS. 7A to 7E are carried out. These steps described with FIGS. 7A to 7E are the same as those in the manufacturing method of the second embodiment, and therefore, the description thereof is omitted. As the result of the steps, as shown in FIG. 9A, the second p-region p2 is formed in the semiconductor substrate 11, and the gate electrode 14 is formed over the second p-region p2 with the intermediary of the gate insulating film 13. The hard mask 41 (insulating film 15) is formed on the gate electrode 14. The sidewalls 16 and 17 are formed on the side faces of the gate electrode 14, and the second n-region n2 is formed in the second p-region p2 on one lateral side of the gate electrode 14. Subsequently, the insulating film 42 that is to serve as a mask at the time of epitaxial growth is formed. This insulating film 42 is formed of e.g. a silicon nitride film. The film thickness thereof is set to e.g. 20 nm. Thereafter, by typical resist application and lithography, an etching mask (not shown) is formed in which an aperture is formed over the region on the other lateral side of the gate electrode 14, i.e., over the region on which the first n-region is to be formed. Subsequently, by an etching technique with use of this etching mask, the insulating film 42 on the other lateral side of the gate electrode 14 is etched to thereby expose the surface of the semiconductor substrate 11 in the region on which the first n-region is to be formed. Subsequently, the first n-region n1 of the second conductivity type (n-type), composed of silicon germanium or germanium, is formed on the exposed semiconductor substrate 11 (second p-region p2) by selective epitaxial growth. In this example, the first n-region n1 is formed by using silicon germanium as one example.

As one example of the condition of this selective epitaxial growth, monosilane (SiH₄), germane (GeH₄), diborane (B₂H₆), phosphine (PH₃), and hydrogen chloride (HCl) gas are used as the source gas, and the substrate temperature (deposition temperature) is set to 750° C. Furthermore, the conditions are so set that a dopant concentration (e.g., phosphorpus concentration) of e.g. 1×10¹⁸cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁷cm⁻³to 1×10²¹cm⁻³. The film thickness of the first n-region n1 is set to e.g. 50 nm to 300 nm. In this example, the thickness is set to 100 nm as one example. In this epitaxial growth, the flow rate of monosilane (SiH₄) and germane (GeH₄) is changed in a continuous or step manner in such a way that a part closer to the surface of the silicon substrate will have a higher composition ratio of germanium (Ge) and the composition ratio of silicon. (Si) will become higher as the deposition progresses. This scheme can achieve continuous changes of the band gap, and thus makes it possible to generate a self electric field in the silicon germanium (SiGe) layer. As a result, carriers can be accelerated, which permits high-speed operation. Instead of monosilane (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), dichlorosilane (SiH₂Cl₂), trichlorosilane (SiHCl₃), tetrachlorosilane (SiCl₄), or the like may be used. Instead of phosphine (PH₃), another n-type impurity source such as arsine (AsH₃) or an organic source of any of these substances may be used. Before the epitaxial growth, the surface of the silicon substrate may be cleaned by using a chemical such as hydrofluoric acid (HF), hydrogen (H₂) gas, and so on according to need. In FIGS. 9B and 9C, illustration of a lower part of the semiconductor substrate 11 is omitted.

Referring next to FIG. 9B, the first p-region p1 of the first conductivity type (p-type), formed of an epitaxially grown silicon layer, is formed on the first n-region n1 by selective epitaxial growth. As one example of the condition of this selective epitaxial growth, monosilane (SiH₄), diborane (B₂H₆), and hydrogen chloride (HCl) gas are used as the source gas, and the substrate temperature (deposition temperature) is set to 750° C. Furthermore, the conditions are so set that a dopant concentration (e.g., boron concentration) of e.g. 1×10²⁰cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁸cm⁻³to 1×10²¹cm⁻³. Instead of monosilane (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), dichlorosilane (SiH₂Cl₂), trichlorosilane (SiHCl₃), tetrachlorosilane (SiCl₄), or the like may be used. Furthermore, instead of diborane (B₂H₆), another p-type impurity source such as an organic source may be used. In addition, a silicon germanium (SiGe) film may be deposited instead of the silicon (Si) film by selective epitaxial growth. However, because this film should have a band gap wider than that of the uppermost part of the n-type region (first n-region n1), the composition ratio of silicon (Si) to germanium (Ge) should be adequately adjusted.

Referring next to FIG. 9C, by a typical electrode formation technique, the anode electrode A connected to the first p-region p1 and the cathode electrode K connected to the second n-region n2 are formed. At this time, it is preferable to form a silicide (TiSi, CoSi, NiSi, or the like) at the both-end exposed parts on the first p-region p1 and the second n-region n2 through a salicide step. After the electrode formation, a wiring step similar to that in a typical CMOS step is carried out.

In the manufacturing method of the fourth embodiment, the first n-region n1 in the thyristor 8 is formed by using a germanium layer or silicon germanium layer having mobility higher than that of silicon. Thus, the mobility of carriers in the first n-region n1 can be enhanced. This can increase the speed of sweeping of the carriers out of the first n-region n1, which can enhance the speed of switching from the on-state to the off-state. Furthermore, because the carrier mobility is enhanced, increase in the speed of switching from the off-state to the on-state can also be expected as a synergetic effect. It is generally known that the carrier mobility of germanium is higher than that of silicon. For example, the mobility of electrons and holes in silicon is 1600 cm²/V·s and 430 cm²/V·s, respectively. In contrast, the mobility of electrons and holes in germanium is 3900 cm²/V·s and 1900 cm²/V·s, respectively. That is, both the mobility of electrons and that of holes in germanium are higher, and in particular, the mobility of holes in germanium is as high as about five times that in silicon. Therefore, by using germanium or silicon germanium, which is a mixture of silicon and germanium with high carrier mobility, as the material of at least the second region, the switching speed of the thyristor 8 formed of the first p-region p1, the first n-region n1, the second p-region p2, and the second n-region n2 can be enhanced. This offers an advantage that the semiconductor device 7 having the high-speed thyristor 8 can be manufactured.

A method for manufacturing a semiconductor device according to one embodiment (fifth embodiment) of the present invention will be described below with reference to FIGS. 10A and 10D as sectional views of manufacturing steps. This manufacturing method is one example of a method for manufacturing the semiconductor device 9 described with FIG. 5.

The steps described with FIGS. 7A to 7G are carried out. These steps described with FIGS. 7A to 7G are the same as those in the manufacturing method of the second embodiment, and therefore, the description thereof is omitted. As the result of the steps, as shown in FIG. 10A, the second p-region p2 is formed in the semiconductor substrate 11, and the gate electrode 14 is formed over the second p-region p2 with the intermediary of the gate insulating film 13. The hard mask 41 (insulating film 15) is formed on the gate electrode 14. The sidewalls 16 and 17 are formed on the side faces of the gate electrode 14, and the second n-region n2 is formed in the second p-region p2 on one lateral side of the gate electrode 14. Subsequently, the insulating film 42 that is to serve as a mask at the time of epitaxial growth is formed. This insulating film 42 is formed of e.g. a silicon nitride film. The film thickness thereof is set to e.g. 20 nm. Thereafter, by typical resist application and lithography, an etching mask (not shown) is formed in which an aperture is formed over the region on the other lateral side of the gate electrode 14, i.e., over the region in which the first n-region is to be formed. Subsequently, by an etching technique with use of this etching mask, the insulating film 42 on the other lateral side of the gate electrode 14 is etched to thereby expose the surface of the semiconductor substrate 11 in the region in which the first n-region is to be formed. The recess 18 is formed by etching the second p-region p2 with use of the insulating film 42 and the sidewall 17 as the mask. Subsequently, the first n-region n1 of the second conductivity type (n-type), composed of germanium or silicon germanium, is formed in the recess 18 by selective epitaxial growth. This first n-region n1 is so formed that the upper face thereof is higher than the surface of the semiconductor substrate (silicon substrate) 11 by about 50 nm to 100 nm. This can prevent the short-circuit between the second p-region p2 and the first p-region p1 to be formed later.

As one example of the condition of this selective epitaxial growth, monosilane (SiH₄), germane (GeH₄), diborane (B₂H₆), phosphine (PH₃), and hydrogen chloride (HCl) gas are used as the source gas, and the substrate temperature (deposition temperature) is set to 750° C. Furthermore, the condition is so set that a dopant concentration (e.g., phosphorpus concentration) of e.g. 1×10¹⁸cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁷cm⁻³to 1×10²¹cm⁻³. The film thickness of the first n-region n1 is set to e.g. 50 nm to 300 nm. In this example, the thickness is set to 100 nm as one example. In this epitaxial growth, the flow rate of monosilane (SiH₄) and germane (GeH₄) is changed in a continuous or step manner in such a way that a part closer to the surface of the silicon substrate will have a higher composition ratio of germanium (Ge) and the composition ratio of silicon (Si) will become higher as the deposition progresses. This scheme can achieve continuous changes of the band gap, and thus makes it possible to generate a self electric field in the silicon germanium (SiGe) layer. As a result, carriers can be accelerated, which permits high-speed operation. Instead of monosilane (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), dichlorosilane (SiH₂Cl₂), trichlorosilane (SiHCl₃), tetrachlorosilane (SiCl₄), or the like may be used. Instead of phosphine (PH₃), another n-type impurity source such as arsine (AsH₃) or an organic source of any of these substances may be used. Before the epitaxial growth, the surface of the silicon substrate may be cleaned by using a chemical such as hydrofluoric acid (HF), hydrogen (H₂) gas, and so on according to need.

The insulating film 43 that is to serve as a mask at the time of epitaxial growth is formed. This insulating film 43 is formed of e.g. a silicon nitride film. The film thickness thereof is set to e.g. 20 nm. Thereafter, by typical resist application and lithography, an etching mask (not shown) is formed in which an aperture is formed over the region on the other lateral side of the gate electrode 14, i.e., over the region in the first n-region n1 in which the first p-region p1 is to be formed. Subsequently, by an etching technique with use of this etching mask, the insulating film 43 on the region in which the first p-region p1 is to be formed on the other lateral side of the gate electrode 14 is etched. This etching exposes the surface of the semiconductor substrate 11 (first n-region n1) in the region in which the first p-region is to be formed. In this example, a silicon nitride film is used in order to ensure the selectivity at the time of the epitaxial growth. However, another kind of film may be used as long as the selectivity can be ensured. In FIG. 10B and the subsequent drawings, illustration of a lower part of the semiconductor substrate 11 is omitted.

Referring next to FIG. 10B, the recess 19 is formed by etching the first n-region n1 with use of the insulating film 43 and the insulating film 42 as the mask. This recess 19 is formed by etching the semiconductor substrate 11 to a depth of e.g. 100 nm. This etching depth is equivalent to the depth of the junction between the first n-region n1 and the first p-region p1, and therefore may be adequately changed depending on device characteristics. In this etching, the insulating film 43 on the insulating film 42 on one lateral side of the gate electrode 14 may be removed. The drawing shows the case where the insulating film 43 on this side is removed. Alternatively, it may be left.

Referring next to FIG. 10C, the first p-region p1 of the first conductivity type (p-type), formed of an epitaxially grown silicon layer, is formed by selective epitaxial growth in the recess 19 formed in the first n-region n1. As one example of the condition of this selective epitaxial growth, monosilane (SiH₄), diborane (B₂H₆), and hydrogen chloride (HCl) gas are used as the source gas, and the substrate temperature (deposition temperature) is set to 750° C. Furthermore, the condition is so set that a dopant concentration (e.g., boron concentration) of e.g. 1×10²⁰cm⁻³is obtained. It is desirable that this dopant concentration be about 1×10¹⁷cm⁻³to 1×10²¹cm⁻³. Instead of monosilane (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), dichlorosilane (SiH₂Cl₂), trichlorosilane (SiHCl₃), tetrachlorosilane (SiCl₄), or the like may be used. Furthermore, instead of diborane (B₂H₆), another p-type impurity source such as an organic source may be used. In addition, a silicon germanium (SiGe) film may be deposited instead of the silicon (Si) film by selective epitaxial growth. However, because this film should have a band gap wider than that of the uppermost part of the n-type region (first n-region n1), the composition ratio of silicon (Si) to germanium (Ge) should be adequately adjusted. Before the epitaxial growth, the surface of the silicon substrate may be cleaned by using a chemical such as hydrof luoric acid (HF), hydrogen (H₂) gas, and so on according to need.

Referring next to FIG. 10D, by a typical electrode formation technique, the anode electrode A connected to the first p-region p1 and the cathode electrode K connected to the second n-region n2 are formed. At this time, it is preferable to form a silicide (TiSi, CoSi, NiSi, or the like) at the both-end exposed parts on the first p-region p1 and the second n-region n2 through a salicide step. After the electrode formation, a wiring step similar to that in a typical CMOS step is carried out.

In the manufacturing method of the fifth embodiment, the first n-region n1 in the thyristor 10 is formed by using a germanium layer or silicon germanium layer having mobility higher than that of silicon. Thus, the mobility of carriers in the first n-region n1 can be enhanced. This can increase the speed of sweeping of the carriers out of the first n-region n1, which can enhance the speed of switching from the on-state to the off-state. Furthermore, because the carrier mobility is enhanced, increase in the speed of switching from the off-state to the on-state can also be expected as a synergetic effect. It is generally known that the carrier mobility of germanium is higher than that of silicon. For example, the mobility of electrons and holes in silicon is 1600 cm²/V·s and 430 cm²/V·s, respectively. In contrast, the mobility of electrons and holes in germanium is 3900 cm²/V·s and 1900 cm²/V·s, respectively. That is, both the mobility of electrons and that of holes in germanium are higher, and in particular, the mobility of holes in germanium is as high as about five times that in silicon. Therefore, by using germanium or silicon germanium, which is a mixture of silicon and germanium with high carrier mobility, as the material of at least the second region, the switching speed of the thyristor 10 formed of the first p-region p1, the first n-region n1, the second p-region p2, and the second n-region n2 can be enhanced. This offers an advantage that the semiconductor device 9 having the high-speed thyristor 10 can be manufactured.

The above-described first to fifth embodiments are based on the premise that a bulk silicon substrate is used as the semiconductor substrate 11. However, the semiconductor devices of the embodiments can be manufactured also by use of an SOI (Silicon on insulator) substrate, GOI (Germanium on insulator) substrate, SiGeOI (Silicon Germanium on insulator) substrate, silicon germanium (SiGe) substrate, or the like.

Furthermore, in the above-described first to fifth embodiments, the n-type regions and p-type regions may be interchanged.

In the first to fifth embodiments, all the epitaxial growth is accompanied by doping. However, all or part of the epitaxially grown layers may be formed by carrying out epitaxial growth without doping and then executing doping with an impurity by ion implantation or solid-state diffusion.

In the second and third embodiments, the recess 18 is formed in the semiconductor substrate (silicon substrate) 11. However, the first n-region n1 may be formed by selective epitaxial growth without the formation of the recess 18 like in the fourth embodiment.

In the first to fifth embodiments, ion implantation is used to form the second n-region n2. However, the second n-region n2 may be formed by selective epitaxial growth in a recess formed in the second p-region p2 for example. Alternatively, without the formation of a recess, the second n-region n2 may be formed on the second p-region p2 by selective epitaxial growth. When the second n-region n2 is formed on the silicon substrate by selective epitaxial growth, a large effective distance between the first n-region n1 and the second n-region n2 can be obtained, which allows the second p-region p2 to have a large thickness. Because the second p-region p2 is equivalent to the base layer in an NPN bipolar device, this scheme permits adjustment of device characteristics.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Semiconductor device and method for manufacturing semiconductor device

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